CN212624804U - Storage device - Google Patents
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- CN212624804U CN212624804U CN202021255441.3U CN202021255441U CN212624804U CN 212624804 U CN212624804 U CN 212624804U CN 202021255441 U CN202021255441 U CN 202021255441U CN 212624804 U CN212624804 U CN 212624804U
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- memory chip
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Abstract
The application discloses storage device, storage device includes: a circuit board; the memory chip is arranged on the circuit board; the memory chips at least comprise a first memory chip and a second memory chip which are symmetrically arranged on the top surface and the bottom surface of the circuit board; the pin structures of the first memory chip and the second memory chip are different, and when the first memory chip and the second memory chip are attached to the circuit board, the pins of the first memory chip and the pins of the second memory chip with corresponding functions are arranged oppositely. By the mode, the performance of the storage device can be improved, and the design cost of the storage device is reduced.
Description
Technical Field
The present application relates to the field of storage technologies, and in particular, to a storage device.
Background
The storage device comprises a plurality of storage chips, the storage chips adopt the pin layout of international standard JEDECJESD79-xx, the pin layout of DDR chips with different bit widths (x4, x8 and x16) conforms to the corresponding standard, and the pin layout of the same DDR chip is the same.
The DDR chip has the disadvantages that when a plurality of DDR chips are used, the DDR chips are often used in an opposite-pasting mode, so that the connection between pins among the chips and through holes of a circuit board is too long, and the performance is insufficient.
SUMMERY OF THE UTILITY MODEL
The technical problem that this application mainly solved provides a storage device, can promote storage device's performance, reduces storage device's design cost.
A technical solution adopted by the present application is to provide a storage device, including: a circuit board; the memory chip is arranged on the circuit board; the memory chips at least comprise a first memory chip and a second memory chip which are symmetrically arranged on the top surface and the bottom surface of the circuit board; the pin structures of the first memory chip and the second memory chip are different, and when the first memory chip and the second memory chip are attached to the circuit board, the pins of the first memory chip and the pins of the second memory chip with corresponding functions are arranged oppositely.
The bottom surface of the first memory chip is provided with a first pin area, a second pin area, a third pin area and a fourth pin area; the second memory chip is provided with a fifth pin area, a sixth pin area, a seventh pin area and an eighth pin area; the first pin area corresponds to a fifth pin area, the second pin area corresponds to a sixth pin area, the third pin area corresponds to a seventh pin area, and the fourth pin area corresponds to an eighth pin area.
The circuit board comprises a via hole, a first connecting line and a second connecting line; one end of the first connecting wire is connected with one end of the through hole, and the other end of the first connecting wire is connected with a first pin of the first memory chip; the other end of the through hole is connected with one end of a second connecting wire, and the other end of the second connecting wire is connected with a second pin of the second memory chip; the pin area where the first pin is located corresponds to the pin area where the second pin is located, and the distance between the projection of the first pin on the second memory chip and the second pin is smaller than the preset distance.
The first pins and the second pins are symmetrically arranged, and the projection positions of the first pins on the second memory chip are overlapped with the positions of the second pins.
Wherein the via hole is a through hole.
The memory chip is a DDR memory.
The storage device is a memory bank.
Wherein the storage device is an onboard memory.
The beneficial effect of this application is: be different from prior art's condition, what this application provided sets up to different overall arrangement through the pin region to the memory chip who pastes, and the pin that makes two symmetries set up when pasting is corresponding, and then makes the wiring of circuit board simpler, and the connecting wire between via hole and the pin is shorter to promote whole storage device's operating frequency. And the design cost is reduced because the wiring of the circuit board is simple.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic structural diagram of an embodiment of a memory device provided in the present application;
FIG. 2 is a schematic structural diagram of an embodiment of a first memory chip provided in the present application;
FIG. 3 is a schematic structural diagram of an embodiment of a second memory chip provided in the present application;
FIG. 4 is a schematic structural diagram of a memory device provided herein;
FIG. 5 is a schematic diagram of a pin connection structure in a memory device provided in the present application
Fig. 6 is a schematic partial structure diagram of an embodiment of a memory device provided in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some of the structures related to the present application are shown in the drawings, not all of the structures. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a memory device provided in the present application. The memory device 10 includes a circuit board 11 and a memory chip 12. The memory chip 12 is disposed on the circuit board 11. The memory chip 12 includes a first memory chip 121 and a second memory chip 122.
In some embodiments, the circuit board 11 is a double-sided board. Copper is coated on both sides of the circuit board, so that wires are arranged between the two layers, and the wires can be connected through the through holes to form required network connection. The circuit board 11 may be a Flexible Printed Circuit (FPC), a rigid Printed Circuit (PCB), or a Flexible Printed Circuit Board (FPCB).
The first memory chip 121 and the second memory chip 122 are symmetrically arranged on the top surface and the bottom surface of the circuit board, respectively; the first memory chip 121 and the second memory chip 122 have different pin structures, and when the first memory chip 121 and the second memory chip 122 are attached to a circuit board, the pins of the first memory chip 121 and the pins of the second memory chip 122 having corresponding functions are arranged oppositely.
Referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment of a first memory chip provided in the present application.
The bottom surface of the first memory chip 121 is provided with a first lead area a, a second lead area B, a third lead area C, and a fourth lead area D. The first pin area A, the second pin area B, the third pin area C and the fourth pin area D are respectively provided with pins with corresponding functions.
Referring to fig. 3, fig. 3 is a schematic structural diagram of an embodiment of a second memory chip provided in the present application.
The second memory chip 122 is provided with a fifth lead region a, a sixth lead region b, a seventh lead region c, and an eighth lead region d. Pins with corresponding functions are arranged in the fifth pin area a, the sixth pin area b, the seventh pin area c and the eighth pin area d respectively.
Referring to fig. 2 and 3, the first lead area a corresponds to a fifth lead area a, the second lead area B corresponds to a sixth lead area B, the third lead area C corresponds to a seventh lead area C, and the fourth lead area D corresponds to an eighth lead area D. The corresponding pin area between the first memory chip 121 and the second memory chip 122 is connected to the same via hole, thereby reducing the length of the connection line with the via hole. Reduce signal interference and improve the working performance of the chip.
When attached to the circuit board 11, the following description will be made with reference to fig. 4:
the first memory chip 121 and the second memory chip 122 are attached to the circuit board 11, the first lead area a of the first memory chip 121 corresponds to the fifth lead area a of the second memory chip 122, the second lead area B of the first memory chip 121 corresponds to the sixth lead area B of the second memory chip 122, the third lead area C of the first memory chip 121 corresponds to the seventh lead area C of the second memory chip 122, and the fourth lead area D of the first memory chip 121 corresponds to the eighth lead area D of the second memory chip 122. The circuit board 11 includes a via hole and first and second connection lines; one end of the first connecting wire is connected with one end of the through hole, and the other end of the first connecting wire is connected with a first pin of the first memory chip; the other end of the through hole is connected with one end of a second connecting wire, and the other end of the second connecting wire is connected with a second pin of the second memory chip; the pin area where the first pin is located corresponds to the pin area where the second pin is located, and the distance between the projection of the first pin on the second memory chip and the second pin is smaller than the preset distance. For example, referring to fig. 5, taking the pin a0 as an example, the TOP surface (TOP surface) of the circuit board 11 is attached to the first memory chip 121, for example, the a0 is located at the N3 position of the first memory chip 121, the BOT surface (bottom surface) is attached to the second memory chip 122, and the a0 position of the second memory chip 122 may be located at the corresponding positions a0-0(N7) and the peripheral pins a0-1(M7), a0-2(P7), and a0-3(N8) directly below the first memory chip 121.
Referring to fig. 6, the third lead region C of the first memory chip 121 corresponds to the seventh lead region C of the second memory chip 122 for example: e in fig. 5 represents an enlarged view of the connection of pin C1 with a via. E in fig. 5 represents an enlarged view of the connection of pin c1 with a via.
The pin C1 in the third pin area C corresponds to the pin C1 in the seventh pin area C, and is connected to a via. The pin C1 is connected to the via end 111a through a first connection line F, and the pin C1 is connected to the via end 111b through a second connection line F. Control signals and address signals are input to the pin C1 and the pin C1 through the via hole, the first connection line F, and the second connection line F to operate the first memory chip 121 and the second memory chip 122. The pin area where the first pin is located corresponds to the pin area where the second pin is located, and the distance between the projection of the first pin on the second memory chip and the second pin is smaller than the preset distance. I.e. the lengths of the first connecting line F and the second connecting line F do not differ much. Specifically, the first pin and the second pin are symmetrically arranged, and the projection position of the first pin on the second memory chip coincides with the position of the second pin.
Specifically, the lengths of the first connection line F and the second connection line F are equal.
It is understood that the pins in the pin areas of the first memory chip 121 and the second memory chip 122, which correspond to each other, are connected to the vias in the above-described manner. The via hole is a through hole.
In some embodiments, the memory chip is a DDR memory. The storage device is a memory bank.
In some embodiments, the storage device is on-board memory. It is understood that when the on-board memory is used, the same circuit board is shared with the rest of the functional modules of the electronic device, and the first memory chip and the second memory chip and the corresponding wiring of the circuit board are arranged in the area of the circuit board corresponding to the memory function in the manner of the above-described embodiment.
Be different from prior art's condition, the storage device that this application provided sets up to different overall arrangement through the pin region to the memory chip who pastes, and the pin that makes two symmetries set up when pasting is corresponding, and then makes the wiring of circuit board simpler, and the connecting wire between via hole and the pin is shorter to promote whole storage device's operating frequency. And the design cost is reduced because the wiring of the circuit board is simple.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (8)
1. A storage device, comprising:
a circuit board;
the memory chip is arranged on the circuit board;
the memory chips at least comprise a first memory chip and a second memory chip which are symmetrically arranged on the top surface and the bottom surface of the circuit board; the pin structures of the first memory chip and the second memory chip are different, and when the first memory chip and the second memory chip are attached to the circuit board, the pins of the first memory chip and the pins of the second memory chip with corresponding functions are arranged oppositely.
2. The memory device according to claim 1, wherein the bottom surface of the first memory chip is provided with a first lead area, a second lead area, a third lead area and a fourth lead area;
the second memory chip is provided with a fifth pin area, a sixth pin area, a seventh pin area and an eighth pin area;
the first lead area corresponds to the fifth lead area, the second lead area corresponds to the sixth lead area, the third lead area corresponds to the seventh lead area, and the fourth lead area corresponds to the eighth lead area.
3. The storage device of claim 2,
the circuit board comprises a via hole, a first connecting line and a second connecting line;
one end of the first connecting line is connected with one end of the via hole, and the other end of the first connecting line is connected with a first pin of the first memory chip;
the other end of the through hole is connected with one end of the second connecting wire, and the other end of the second connecting wire is connected with a second pin of the second memory chip; the pin area where the first pin is located corresponds to the pin area where the second pin is located, and the distance between the projection of the first pin on the second memory chip and the second pin is smaller than a preset distance.
4. The storage device of claim 3,
the first pins and the second pins are symmetrically arranged, and the projection positions of the first pins on the second memory chip are superposed with the positions of the second pins.
5. The storage device of claim 3,
the through holes are through holes.
6. The memory device according to claim 1, wherein the memory chip is a DDR memory.
7. The memory device of claim 1, wherein the memory device is a memory bank.
8. The storage device of claim 1, wherein the storage device is an on-board memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021255441.3U CN212624804U (en) | 2020-07-01 | 2020-07-01 | Storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021255441.3U CN212624804U (en) | 2020-07-01 | 2020-07-01 | Storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212624804U true CN212624804U (en) | 2021-02-26 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021255441.3U Active CN212624804U (en) | 2020-07-01 | 2020-07-01 | Storage device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN212624804U (en) |
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2020
- 2020-07-01 CN CN202021255441.3U patent/CN212624804U/en active Active
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