CN214671816U - Memory structure and notebook computer - Google Patents
Memory structure and notebook computer Download PDFInfo
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- CN214671816U CN214671816U CN202120248328.0U CN202120248328U CN214671816U CN 214671816 U CN214671816 U CN 214671816U CN 202120248328 U CN202120248328 U CN 202120248328U CN 214671816 U CN214671816 U CN 214671816U
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- 239000002245 particle Substances 0.000 claims abstract description 72
- 238000003466 welding Methods 0.000 claims abstract description 63
- 230000009977 dual effect Effects 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 claims 3
- 239000008187 granular material Substances 0.000 abstract description 21
- 238000005476 soldering Methods 0.000 description 12
- 238000012795 verification Methods 0.000 description 3
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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Abstract
The utility model provides a memory structure and notebook computer, the memory structure includes printed circuit board, memory buffer chip and a plurality of memory granule, memory buffer chip sets up printed circuit board is last, just printed circuit board has the routing layer, preset welding area on the routing layer, a plurality of the memory granule is fixed through the welded mode welding area, wherein, each the memory granule all with memory buffer chip connects. The welding area is preset on the routing layer of the printed circuit board, so that a plurality of memory particles can be directly welded in the welding area, the routing rule of the routing layer on the printed circuit board can be directly applied to the memory particles, the convenience of memory particle layout is improved, and the debugging and verifying time is saved.
Description
Technical Field
The utility model relates to a notebook computer field, in particular to memory structure and notebook computer.
Background
At present, memory granules of notebook computers generally adopt a memory layout mode of welding to a mainboard. However, in the existing scheme, the memory particle layout needs to be subjected to a series of verification to obtain the final determination, and after the memory particle position is determined, routing layout is performed, so that the problems that routing is incorrect, lines are unequal in length and insufficient in line distance may exist, and the memory particle layout and the routing need to be determined again are caused.
SUMMERY OF THE UTILITY MODEL
The main objective of the utility model is to provide a memory structure and notebook computer aims at having solved in the definite back of memory granule position, walks the line overall arrangement again, probably has to walk the line incorrect, the line and the line between vary the length and the line apart from the not enough condition, lead to the problem that needs redetermine memory granule overall arrangement and walk the line.
In order to achieve the above object, the utility model provides a memory structure, the memory structure includes:
the memory buffer chip is arranged on the printed circuit board, the printed circuit board is provided with a wiring layer, and a welding area is preset on the wiring layer;
the memory particles are fixed in the welding area in a welding mode, and each memory particle is connected with the memory buffer chip.
In an alternative embodiment, the welding area has a welding position, and a plurality of memory particles are welded at the welding position.
In an alternative embodiment, a plurality of the memory particles form a single channel.
In an alternative embodiment, the welding site is in the shape of a straight line.
In an alternative embodiment, there are two weld sites within the weld region, including:
the memory chip comprises a first welding position and a second welding position, wherein part of the memory particles in the memory particles are welded at the first welding position, and other memory particles in the memory particles are welded at the second welding position.
In an alternative embodiment, a plurality of the memory particles form a dual channel.
In an alternative embodiment, the first bonding site and the second bonding site are combined to form a straight-line layout or an L-shape.
In an optional embodiment, the first soldering site is disposed on the routing layer, the second soldering site is disposed on a surface of the printed circuit board facing away from the routing layer, and a position of the first soldering site corresponds to a position of the second soldering site, wherein the first soldering site and the second soldering site are in a straight shape.
In an alternative embodiment, the memory granule has a specification of DDR 4.
In order to achieve the above object, the present invention provides a notebook computer, which includes the above-mentioned memory structure.
The utility model provides a memory structure and notebook computer, the memory structure includes printed circuit board, memory buffer chip and a plurality of memory granule, memory buffer chip sets up printed circuit board is last, just printed circuit board has the routing layer, preset welding area on the routing layer, a plurality of the memory granule is fixed through the welded mode welding area, wherein, each the memory granule all with memory buffer chip connects. The welding area is preset on the routing layer of the printed circuit board, so that a plurality of memory particles can be directly welded in the welding area, the routing rule of the routing layer on the printed circuit board can be directly applied to the memory particles, the convenience of memory particle layout is improved, and the debugging and verifying time is saved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or examples of the present invention, the drawings used in the embodiments or examples will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic front view of a memory structure according to an embodiment of the present invention;
fig. 2 is a schematic front view of an implementation manner of a memory structure according to another embodiment of the present invention;
fig. 3 is a schematic front view of another implementation manner of a memory structure according to another embodiment of the present invention;
fig. 4 is a schematic front view of an implementation manner of a memory structure according to another embodiment of the present invention;
fig. 5 is a schematic front view of another implementation manner of a memory structure according to another embodiment of the present invention;
fig. 6 is a schematic diagram of a memory structure corresponding to fig. 1.
The objects, features and advantages of the present invention will be further described with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that all the directional indicators (such as upper, lower, left, right, front and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present invention.
The utility model provides a memory structure.
In an embodiment, as shown in fig. 1, the memory structure includes a printed circuit board 1, a memory buffer chip 2, and a plurality of memory particles 3, the memory buffer chip 2 is disposed on the printed circuit board 1, the printed circuit board 1 has a routing layer 11 (routing is not shown in fig. 1), a welding area a is preset on the routing layer 11, the memory particles 3 are fixed in the welding area a by welding, and each memory particle 3 is connected to the memory buffer chip 2. Namely, the utility model provides an among the technical scheme, through preset on printed circuit board 1's routing layer 11 welding area A, so that a plurality of memory granule 3 can the lug weld at this welding area A, thereby make memory granule 3 can directly apply mechanically the routing rule of routing layer 11 on printed circuit board 1, and then improve the convenience of 3 overall arrangements of memory granule saves the debugging verification time.
Since the routing layout is performed after the position of the memory particle 3 is determined in the exemplary technology, at this time, situations that the routing is incorrect, the lengths of the lines are unequal, and the line spacing is insufficient may exist, that is, the memory particle layout and the routing need to be determined again; in addition, since the routing of the memory grain 3 is a high-speed signal, the previous scheme may have the situation that the routing layer is not available or is not complete, so that the whole system cannot operate. Based on this, the routing layer 11 is a routing arranged on the printed circuit board 1 according to the routing specification and Layout of the memory particles, and a welding area a for welding the memory particles 3 is reserved on the routing layer 11, so that the printed circuit board 1, the routing layer 11 and the welding area a can form a memory Layout module, and at this time, the memory particles 3 can be matched with the routing of the routing layer 11 only by welding and fixing the memory particles 3 in the welding area a and finely adjusting the routing position of the routing layer 11, so that the time and cost for repeated verification can be realized, and the Layout of the memory particles 3 is facilitated; and the data of the line width, line distance, equal length and the like of the wires in the memory Layout module are matched with the data of the memory particles 3 welded in the welding area A, so that the integrity of signals transmitted by the wires on the wire routing layer 11 is ensured, and the quality and the performance of products are improved.
Further, in the memory structure, the memory particles 3 are firmly fixed on the printed circuit board 1 in a welding mode, and compared with a scheme that a memory bank in an exemplary technology is fixed on the printed circuit board through a DIMM slot, the memory particles 3 can be prevented from shaking, and poor contact is avoided.
Optionally, as shown in fig. 1, the welding area a has a welding position a1, and a plurality of memory particles 3 are welded at the welding position a 1.
Specifically, the memory particles 3 include four memory particles, that is, in this embodiment, four memory particles 3 are welded at the welding position a1, and all four memory particles 3 are connected to the memory buffer chip 2, so that a single channel is formed between the four memory particles 3.
In this embodiment, the welding position a1 is placed in a straight line. The bonding position a1 is placed on one side of the memory buffer chip 2, and may be specifically an upper side, a lower side, a left side, a right side, and the like (fig. 1 shows that the bonding position a1 is located on the lower side of the memory buffer chip 2), which is not limited herein.
It can be understood that four welding points are disposed in the welding position a1, and each welding point is correspondingly welded to one memory particle 3, so that the four memory particles 3 are independent and do not interfere with each other.
Further, the memory granules 3 are connected to the memory buffer chip 2, and the number of the memory granules 3 is not limited to four, for example, when the number of the memory granules 3 is eight, the eight memory granules 3 can realize a dual channel through the memory buffer chip 2.
Specifically, as shown in fig. 2 to 3, the welding area a has two welding positions, including a first welding position a2 and a second welding position A3, a plurality of memory particles 3 are partially welded to the first welding position a2, and a plurality of memory particles 3 are welded to the second welding position A3, where the plurality of memory particles 3 form a dual channel. That is, four memory particles 3 are used as a first group of memory particles, and another four memory particles 3 are used as a second group of memory particles, in this case, the first group of memory particles is disposed at the first welding position a2, and the second group of memory particles is disposed at the second welding position A3.
Of course, in this embodiment, as shown in fig. 4 to 5, two memory particles 3 may be used as a first group of memory particles, and another six memory particles 3 may be used as a second group of memory particles, at this time, the first group of memory particles is disposed at the first welding position a2, and the second group of memory particles is disposed at the second welding position A3; alternatively, the eight memory particles 3 may be combined in other ways, which is not limited herein.
Further, the first bonding site a2 and the second bonding site A3 are combined to form a straight line shape (as shown in fig. 2 to 3), wherein the first bonding site a2 and the second bonding site A3 are disposed on one side of the memory buffer chip 2, specifically, the side may be an upper side, a lower side, a left side, a right side, and the like, which is not limited herein.
Or, as shown in fig. 4 to 5, the first bonding site a2 and the second bonding site A3 are combined to form an L-shape, wherein the first bonding site a2 is located at the left side of the memory buffer chip 2, and the second bonding site A3 is located at the upper side or the lower side of the memory buffer chip 2; or, the first bonding site a2 is placed on the right side of the memory buffer chip 2, and the second bonding site A3 is placed on the upper side or the lower side of the memory buffer chip 2; alternatively, the first welding position a2 and the second welding position A3 may be formed in an L-shape in other combinations, which is not limited herein.
Of course, in this embodiment, the first bonding site a2 and the second bonding site A3 may be disposed on two opposite sides of the memory buffer chip 2, respectively, and the disclosure is not limited thereto.
In this embodiment, in order to reduce the layout space, as shown in fig. 1 and 6, the first soldering position a2 is disposed on the routing layer 11, the second soldering position A3 is disposed on the surface B of the printed circuit board 1 facing away from the routing layer 11, and the position of the first soldering position a2 corresponds to the position of the second soldering position A3, wherein the first soldering position a2 and the second soldering position A3 are both in a straight shape, that is, the first group of memory particles and the second group of memory particles are soldered on the routing layer 11 and the surface B of the printed circuit board 1.
That is, the memory structure in this embodiment can implement a single channel and a dual channel through the memory buffer chip 2, so as to meet the requirements of different application scenarios.
Based on the above embodiment, the specification of the memory particle 3 is DDR 4. Alternatively, in other embodiments, the specification of the memory granule 3 may also be DDR3, DDR2, DDR, etc., which is not limited herein.
Further, the memory structure further includes a power circuit (not shown) disposed on the printed circuit board 1, and the power circuit is respectively connected to the memory buffer chip 2 and each memory particle 3; the power supply circuit is used for supplying power to the memory buffer chip 2 and each memory particle 3.
The utility model provides an among the technical scheme, the memory structure includes printed circuit board 1, memory buffer chip 2 and a plurality of memory granule 3, memory buffer chip 2 sets up printed circuit board 1 is last, just printed circuit board 1 has routing layer 11, welding area A, a plurality of have been preset on routing layer 11 memory granule 3 is fixed through the welded mode welding area A, wherein, each memory granule 3 all with memory buffer chip 2 is connected. The welding area a is preset on the routing layer 11 of the printed circuit board 1, so that a plurality of memory particles 3 can be directly welded in the welding area a, and the memory particles 3 can directly apply the routing rule of the routing layer 11 on the printed circuit board 1, thereby improving the convenience of the layout of the memory particles 3 and saving the debugging and verifying time.
Based on the above embodiment, the utility model also provides a notebook computer.
The notebook computer comprises the memory structure of the embodiment.
Since the notebook computer described in this embodiment includes the memory structure of the above embodiment, that is, the notebook computer described in this embodiment includes all the technical features and technical effects of the memory structure of the above embodiment, specific reference is made to the description of the above embodiment, and details are not repeated here.
The above is only the optional embodiment of the present invention, and not therefore the limit to the patent scope of the present invention, all the concepts of the present invention utilize the equivalent transformation made by the contents of the specification and the drawings, or the direct/indirect application in other related technical fields are included in the patent protection scope of the present invention.
Claims (10)
1. A memory structure, the memory structure comprising:
the memory buffer chip is arranged on the printed circuit board, the printed circuit board is provided with a wiring layer, and a welding area is preset on the wiring layer;
the memory particles are fixed in the welding area in a welding mode, and each memory particle is connected with the memory buffer chip.
2. The memory structure of claim 1 wherein said bonding area has a bonding site therein, and a plurality of said memory particles are bonded to said bonding site.
3. The memory structure of claim 2, wherein a number of the memory particles form a single channel.
4. The memory structure of claim 3, wherein the solder sites are in a straight line.
5. The memory structure of claim 1, wherein there are two bond sites within the bond region, comprising:
the memory chip comprises a first welding position and a second welding position, wherein part of the memory particles in the memory particles are welded at the first welding position, and other memory particles in the memory particles are welded at the second welding position.
6. The memory structure of claim 5, wherein a number of the memory particles form a dual channel.
7. The memory structure of claim 6, wherein the first solder site and the second solder site are combined to form a straight line or an L-shape.
8. The memory structure of claim 6, wherein the first bonding sites are disposed on the routing layer, the second bonding sites are disposed on a surface of the printed circuit board facing away from the routing layer, and the first bonding sites correspond to the second bonding sites, wherein the first bonding sites and the second bonding sites are in a straight shape.
9. The memory structure according to any one of claims 1 to 8, wherein the memory grain has a specification of DDR 4.
10. A notebook computer, characterized in that the notebook computer comprises a memory structure according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120248328.0U CN214671816U (en) | 2021-01-28 | 2021-01-28 | Memory structure and notebook computer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120248328.0U CN214671816U (en) | 2021-01-28 | 2021-01-28 | Memory structure and notebook computer |
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| Publication Number | Publication Date |
|---|---|
| CN214671816U true CN214671816U (en) | 2021-11-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120248328.0U Active CN214671816U (en) | 2021-01-28 | 2021-01-28 | Memory structure and notebook computer |
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| CN (1) | CN214671816U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115360159A (en) * | 2022-10-19 | 2022-11-18 | 北京登临科技有限公司 | Integrated circuit package, coprocessor chip, printed circuit board, board card and electronic equipment |
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2021
- 2021-01-28 CN CN202120248328.0U patent/CN214671816U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115360159A (en) * | 2022-10-19 | 2022-11-18 | 北京登临科技有限公司 | Integrated circuit package, coprocessor chip, printed circuit board, board card and electronic equipment |
| CN115360159B (en) * | 2022-10-19 | 2023-01-31 | 北京登临科技有限公司 | Integrated circuit package, coprocessor chip, printed circuit board, board card and electronic equipment |
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| Date | Code | Title | Description |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20231111 Address after: 518000, 4th Floor, No. 31, Xiacun Community, Gongming Street, Guangming District, Shenzhen City, Guangdong Province Patentee after: Shenzhen Baoxinchuang Information Technology Co.,Ltd. Address before: 518000 501-2, building a, wisdom Plaza, 4068 Qiaoxiang Road, Gaofa community, Shahe street, Nanshan District, Shenzhen City, Guangdong Province Patentee before: Shenzhen baoxinchuang Technology Co.,Ltd. |
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| TR01 | Transfer of patent right |