WO2022021855A1

WO2022021855A1 - Impedance matching apparatus and method for pcb wiring of solid state drive, device and medium

Info

Publication number: WO2022021855A1
Application number: PCT/CN2021/076945
Authority: WO
Inventors: 郭丹萍
Original assignee: 苏州浪潮智能科技有限公司
Priority date: 2020-07-30
Filing date: 2021-02-19
Publication date: 2022-02-03
Also published as: CN111985180B; CN111985180A

Abstract

An impedance matching apparatus and method for a PCB wiring of a solid state drive, an electronic device and a computer-readable storage medium. Said apparatus comprises: a line width calculation module, configured to calculate the line width of a continuous wiring according to an impedance value; a first line width determination module, configured to determine a first impedance value of a main wiring, take same as an actual impedance value of a DDR string, and invoke the line width calculation module to determine the line width of the main wiring according to the first impedance value; an impedance matching model, configured to output an impedance value range of the continuous wiring having the same length as the total length of all wiring segments in the DDR string, a lower limit value of the impedance value range being greater than the actual impedance value; a training module, configured to pre-train to generate the impedance matching model; and a second line width determination module, configured to receive a second impedance value which is within the impedance value range, and invoke the line width calculation module to determine the line width of the wiring segments on the basis of the second impedance value. Said apparatus effectively achieves impedance matching, improves signal quality, and is efficient and simple.

Description

Impedance matching device, method, device and medium for solid-state hard disk PCB traces

This application claims the priority of the Chinese patent application filed on July 30, 2020, with the application number CN202010751225.6 and the invention titled "An Impedance Matching Device, Method, Equipment and Medium for PCB Routing of Solid State Disks", The entire contents of which are incorporated herein by reference.

technical field

The present application relates to the technical field of PCB wiring, and in particular, to an impedance matching device, method, electronic device, and computer-readable storage medium for PCB wiring of a solid-state hard disk.

Background technique

In the field of electronic storage, SSD (Solid State Drive, solid-state drive) is extremely widely used. With the increasing transmission rate of DDR (Double Data Rate, double-rate synchronous dynamic random access memory) and the market's increasing demand for SSD capacity, in the current SSD products in the market, the main control chip CPU usually It is required to hang many DDR chips to improve its storage performance and read and write speed. The addition of DDR particles will introduce a certain load capacitance to the circuit traces, causing the unit capacitance of the circuit traces to increase and the impedance to decrease, which in turn causes the impedance mismatch of the entire trace before and after the DDR particles are attached, causing signal reflections. Seriously affect the integrity of the DDR signal, resulting in the performance of the DDR rate and other performance cannot meet the expected requirements.

In view of this, providing a solution to the above-mentioned technical problems is an urgent need for those skilled in the art.

SUMMARY OF THE INVENTION

The purpose of this application is to provide an impedance matching device, method, electronic device, and computer-readable storage medium for PCB wiring of solid-state hard disks, so as to simply and efficiently solve the problem of wiring impedance mismatch caused by adding DDR particles, thereby improving DDR signal transmission performance.

In order to solve the above technical problems, in the first aspect, the present application discloses an impedance matching device for PCB wiring of a solid-state hard disk. The solid-state hard disk includes a main control chip and a DDR string connected by a backbone wiring. A plurality of DDR particles connected in series by the trace segments; the impedance matching device includes:

The line width calculation module is used to calculate the line width of the corresponding continuous trace according to the input impedance value and stacking parameters;

The first line width determination module is used to determine the first impedance value of the trunk line, and use it as the actual impedance value of the DDR string; call the line width calculation module, which will be calculated based on the first impedance value. The first line width of is used as the line width of the trunk line;

The impedance matching model is used to output the impedance value range of the continuous trace corresponding to the actual impedance value and having the same length as the total length of each trace segment in the DDR string; the lower limit of the impedance value range value is greater than the actual impedance value;

a training module, configured to pre-train and generate the impedance matching model according to the impact on the impedance reduction of the continuous wiring after the DDR particles are connected in series;

The second line width determination module is used to receive the input second impedance value whose value is within the impedance value range; call the line width calculation module, and use the second line width calculated based on the second impedance value as the line width of the trace segment.

Optionally, the first line width determination module is specifically used for:

Receive the input model information and signal type information of the main control chip; query a chip database to obtain the first impedance value corresponding to the model information and the signal type information.

Optionally, also include:

The calibration module is configured to generate a signal simulation eye diagram according to the input second impedance value, so that the user can adjust the second impedance value according to the effect of the signal simulation eye diagram.

Optionally, the training module is specifically used for:

According to the preset DDR string impedance calculation formula, calculate the overall impedance value of the sample DDR string after the DDR particles reduce the trace impedance; according to the continuous trace impedance calculation formula, calculate the total length of each trace segment in the sample DDR string, etc. The associated impedance value of the long continuous trace; taking the overall impedance value as an input, and taking the corresponding value range of the associated impedance value as an output, training to generate the DDR string impedance matching model.

Optionally, the preset DDR string impedance calculation formula is specifically:

Wherein, L and C are the parasitic inductance and parasitic capacitance of the continuous traces of the same length as the total length of each trace segment in the DDR string, respectively; m is the total number of DDR particles; C _L is the equivalent capacitance of the DDR particles; X is the length of each trace segment.

Optionally, the stacking parameters include copper foil thickness, sheet dielectric constant and sheet thickness of the PCB board.

In a second aspect, the present application discloses a method for impedance matching of PCB wiring of a solid-state hard disk. The solid-state hard disk includes a main control chip and a DDR string connected by a backbone wiring, and the DDR string comprises a plurality of wiring segments connected in series. DDR particles; the impedance matching method includes:

determining the first impedance value of the trunk line as the actual impedance value of the DDR string;

Taking the first line width of the continuous wiring calculated based on the first impedance value and the stacking parameters as the line width of the trunk wiring;

Invoke the impedance matching model, and output the impedance value range of the continuous trace corresponding to the actual impedance value and equal to the total length of each trace segment in the DDR string; the lower limit of the impedance value range greater than the actual impedance value;

receiving an input second impedance value whose value is within the impedance value range;

Using the second line width of the continuous trace calculated based on the second impedance value and the stacking parameter as the line width of the trace segment;

Wherein, the impedance matching model is pre-trained and generated based on the impact on the impedance reduction of the continuous wiring after the DDR particles are connected in series.

Optionally, the determining the first impedance value of the trunk line includes:

Receive the input model information and signal type information of the main control chip;

The chip database is queried to obtain the first impedance value corresponding to the model information and the signal type information.

Optionally, after receiving the input second impedance value whose value is within the impedance value range, the method further includes:

According to the inputted second impedance value, a signal simulation eye diagram is generated, so that the user can adjust the second impedance value according to the effect of the signal simulation eye diagram.

Optionally, the training process of the impedance matching model includes:

According to the preset DDR string impedance calculation formula, calculate the overall impedance value of the sample DDR string after the DDR particles reduce the trace impedance;

According to the formula for calculating the impedance of the continuous trace, calculate the associated impedance value of the continuous trace that is equal to the total length of each trace segment in the sample DDR string;

Taking the overall impedance value as an input, and taking the corresponding value range of the associated impedance value as an output, the DDR string impedance matching model is generated by training.

In a third aspect, the present application also discloses an electronic device, comprising:

memory for storing computer programs;

The processor is configured to execute the computer program to implement the steps of any of the above-mentioned impedance matching methods for PCB traces of the solid-state hard disk.

In a fourth aspect, the present application also discloses a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, it is used to implement any of the above solid-state The steps of the impedance matching method of the hard disk PCB trace.

The present application provides an impedance matching device for PCB wiring of a solid-state hard disk. The solid-state hard disk includes a main control chip and a DDR string connected by a backbone wiring, and the DDR string includes a plurality of DDR particles connected in series by wiring segments. ; The impedance matching device includes: a line width calculation module for calculating the line width of the corresponding continuous line according to the input impedance value and the stacking parameters; a first line width determination module for determining the main line The first impedance value is used as the actual impedance value of the DDR string; the line width calculation module is called, and the first line width calculated based on the first impedance value is used as the line width of the trunk line; impedance The matching model is used to output the impedance value range of the continuous traces corresponding to the actual impedance value and having the same length as the total length of each trace segment in the DDR string; the lower limit of the impedance value range is greater than the actual impedance value; a training module is used for pre-training to generate the impedance matching model according to the impact on the impedance reduction of the continuous wiring after the DDR particles are connected in series; the second line width determination module is used for receiving the input value of The second impedance value within the impedance value range; the line width calculation module is invoked, and the second line width calculated based on the second impedance value is used as the line width of the trace segment.

The beneficial effects of the impedance matching device, method, electronic device, and computer-readable storage medium for solid-state drive PCB wiring provided by the present application are: the present application considers the impact on the impedance reduction of the continuous wiring after the DDR particles are connected in series, By reasonably adjusting the line width of the trace segments, the impedance value of each trace segment plus each DDR particle, that is, the actual impedance value of the DDR string, is equal to the first impedance value of the backbone trace, thus effectively realizing the entire link. The impedance matching of the DDR signal ensures the integrity and transmission rate of the DDR signal, and improves the signal quality; in addition, the application does not need to add components such as resistors and capacitors, which effectively saves cost and layout space, and is efficient and convenient.

Description of drawings

In order to more clearly illustrate the prior art and the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings to be used in the description of the prior art and the embodiments of the present application. Of course, the following drawings related to the embodiments of the present application describe only a part of the embodiments of the present application. For those of ordinary skill in the art, without any creative effort, they can also obtain other embodiments according to the provided drawings. The accompanying drawings and other drawings obtained also belong to the protection scope of the present application.

FIG. 1 is a structural block diagram of an impedance matching device for a PCB wiring of a solid-state hard disk disclosed in an embodiment of the application;

FIG. 2 is a schematic circuit diagram of a solid-state hard disk disclosed in an embodiment of the present application;

3 is a flowchart of a method for impedance matching of a solid-state drive PCB wiring disclosed in an embodiment of the present application;

4 is a flowchart of a training method for an impedance matching module disclosed in an embodiment of the present application;

FIG. 5 is a structural block diagram of an electronic device disclosed in an embodiment of the present application.

detailed description

The core of the present application is to provide an impedance matching device, method, electronic device and computer-readable storage medium for PCB traces of solid-state drives, so as to simply and efficiently solve the problem of trace impedance mismatch caused by adding DDR particles, thereby improving DDR signal transmission performance.

In order to describe the technical solutions in the embodiments of the present application more clearly and completely, the technical solutions in the embodiments of the present application will be introduced below with reference to the drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

At present, in the field of electronic storage, SSD (Solid State Drive, solid state drive) is extremely widely used. With the increasing transmission rate of DDR (Double Data Rate, double-rate synchronous dynamic random access memory) and the market's increasing demand for SSD capacity, in the current SSD products in the market, the main control chip CPU usually It is required to hang many DDR chips to improve its storage performance and read and write speed. The addition of DDR particles will introduce a certain load capacitance to the circuit traces, causing the unit capacitance of the circuit traces to increase and the impedance to decrease, which in turn causes the impedance mismatch of the entire trace before and after the DDR particles are mounted, causing signal reflections. Seriously affect the integrity of the DDR signal, resulting in the performance of the DDR rate and other performance cannot meet the expected requirements. In view of this, the present application provides an impedance matching solution for PCB wiring of a solid-state hard disk, which can effectively solve the above problems.

Referring to FIG. 1 , an embodiment of the present application discloses an impedance matching device for PCB wiring of a solid-state hard disk.

The solid-state hard disk includes a main control chip and a DDR string connected by backbone wires, as shown in FIG. 2 for details. Wherein, the DDR string includes a plurality of DDR particles connected in series by wiring segments. Specifically, in FIG. 2 , A represents the backbone wiring; A1, A2, ..., An represent n wiring segments respectively; DDR0, DDR1, ..., DDRn represent n+1 DDR particles, respectively.

The impedance matching device provided by this application, as shown in Figure 1, mainly includes:

The line width calculation module 101 is used to calculate the line width of the corresponding continuous wiring according to the input impedance value and the stacking parameters;

The first line width determination module 102 is used to determine the first impedance value of the trunk line and use it as the actual impedance value of the DDR string; the line width calculation module 101 is called, and the first line width calculated based on the first impedance value is used as The line width of the trunk line;

The impedance matching model 103 is used to output the impedance value range of the continuous trace corresponding to the actual impedance value and having the same length as the total length of each trace segment in the DDR string; the lower limit of the impedance value range is greater than the actual impedance value ;

The training module 104 is used for pre-training and generating the impedance matching model 103 according to the impact on the impedance reduction of the continuous wiring after the DDR particles are connected in series;

The second line width determination module 105 is used to receive the input second impedance value whose value is within the impedance value range; the line width calculation module 101 is called, and the second line width calculated based on the second impedance value is used as the line segment line width.

Specifically, the impedance matching device for the PCB traces of the solid-state hard disk provided by the present application takes into account the impact of the DDR particle load on the impedance of the entire DDR trace, so the line width of the trace segment is adjusted to make it different from the main trace. The line width is used to balance the influence of the DDR load on the trace impedance.

It should be noted that, for a continuous trace on the PCB, the main factors affecting its equivalent impedance are the line width and stacking parameters. The so-called continuous traces are PCB traces that do not include other components (such as DDR particles) and are continuously routed. Therefore, when the impedance value and stacking parameters are known, the line width of the corresponding continuous trace can also be determined. The line width calculation module 101 in the present application can calculate the line width of the corresponding continuous trace according to the input impedance value and stacking parameters.

Wherein, as a specific example, the stacking parameters may specifically include the thickness of the copper foil of the PCB board, the dielectric constant of the board, and the thickness of the board.

The first line width determination module 102 is mainly used to determine the line width of the trunk line, that is, the first line width. Specifically, the first impedance value of the trunk line can be determined according to actual application requirements, and further, by calling the line width calculation module 101, the line width of the trunk line can be calculated. In addition, in order to achieve impedance matching, the actual impedance value of the entire DDR should be equal to the first impedance value of the trunk line.

The second line width determination module 105 is mainly used to determine the line width of the trace segment, that is, the second line width. It should be emphasized that since the introduction of DDR particles will reduce the impedance of the traces, compared with the continuous traces of equal length, the total impedance value of each trace segment in the DDR string with each DDR particle attached, that is, its The actual impedance value should be small. And because the line width calculation module 101 is only suitable for calculating the line width of the continuous line according to the impedance value, the application needs to imagine that the ends of each line in the DDR string are spliced together to form a line without DDR particles. For an imaginary continuous line, by giving the impedance value of the imaginary continuous line, that is, the second impedance value, the line width of the imaginary continuous line can be calculated by calling the line width calculation module 101, that is, the line width of the imaginary continuous line. The line width of the line segment. Providing a reasonable value range of the second impedance value is the key to solving the mismatch in impedance reduction caused by the introduction of DDR particles, and is also the key to the technical problem solved by the present application.

The impedance matching model 103 in the present application is just used to provide the impedance value range of the second impedance value. As before, the first impedance value, that is, the actual impedance value is smaller than the second impedance value. Therefore, the lower limit of the impedance value range of the second impedance value is larger than the actual impedance value. In this application, a large amount of sample data can be obtained in advance, and these sample data can be used to reflect and analyze the impact of the impedance reduction on the continuous traces after the DDR chips are connected in series, and then the impedance matching model 103 can be trained and generated based on the large amount of sample data, so as to According to the actual impedance value of the DDR string, the corresponding imaginary continuous line impedance value range can be given.

It should also be noted that, generally, the lengths of each routing segment are the same. For example, if there are n trace segments, and the length of each trace segment is X, the length of the imaginary continuous trace corresponding to the DDR string is n·X. In addition, when parameters such as the number of DDR particles, the equivalent load capacitance of the DDR particles, and the length X of each trace segment are different, the magnitude of the impact of the resulting impedance reduction is different. Therefore, the impedance matching model 103 can perform matching output according to these specific conditions.

The user can determine the size of the second impedance value within the given impedance value range, and then the second line width determination module 105 can call the line width calculation module 101 to calculate the second line width as the line width of the trace segment.

In the impedance matching device for the PCB wiring of the solid-state hard disk disclosed in this application, the solid-state hard disk includes a main control chip and a DDR string connected by a backbone wiring, and the DDR string includes a plurality of DDR particles connected in series by wiring segments; the impedance matching The device includes: a line width calculation module 101 for calculating the line width of a corresponding continuous line according to the input impedance value and stacking parameters; a first line width determination module 102 for determining the first impedance value of the trunk line, and use it as the actual impedance value of the DDR string; call the line width calculation module 101, and use the first line width calculated based on the first impedance value as the line width of the trunk line; the impedance matching model 103 is used for outputting corresponding to the actual impedance value The impedance value range of the continuous trace that is equal to the total length of each trace segment in the DDR string; the lower limit of the impedance value range is greater than the actual impedance value; the training module 104 The impedance matching model 103 is generated by pre-training on the impact of the impedance reduction of the continuous trace; the second line width determination module 105 is used to receive the input second impedance value whose value is within the impedance value range; call the line width calculation module 101 , and the second line width calculated based on the second impedance value is used as the line width of the trace segment.

It can be seen that the impedance matching device for the PCB wiring of the solid-state hard disk provided by this application, considering the impact on the impedance reduction of the continuous wiring after the DDR particles are connected in series, the line width of the wiring segment is reasonably adjusted, so that each wiring segment adds The impedance value after each DDR particle, that is, the actual impedance value of the DDR string, is equal to the first impedance value of the trunk line, thus effectively realizing the impedance matching of the entire link, ensuring the integrity and transmission rate of the DDR signal, and improving the Signal quality; in addition, the application does not need to add components such as resistors, capacitors, etc., which effectively saves cost and layout space, and is efficient and convenient.

As a specific embodiment, on the basis of the above-mentioned content, the first line width determination module 102 is specifically used for:

Receive the input model information and signal type information of the main control chip; query the chip database to obtain the first impedance value corresponding to the model information and the signal type information.

Specifically, the first line width determination module 102 may have a built-in chip database, so as to determine the first impedance value of the main line by querying the chip database according to the actual application situation. Different chips and different signal types have different impedance requirements. The relevant data is stored in the chip database, and can be updated and maintained by R&D personnel with relevant authority to prevent other personnel from mistakenly deleting or modifying.

The signal types can be specifically classified into data signals, control signals, and clock signals.

As a specific embodiment, on the basis of the above content, the impedance matching device for the PCB wiring of the solid-state disk disclosed in the embodiment of the present application further includes: a calibration module, configured to generate a signal artificial eye according to the input second impedance value diagram, so that the user can adjust the second impedance value according to the effect of the signal simulation eye diagram.

Specifically, since signal impedance matching is a process that is difficult to calculate accurately and may require continuous debugging, in this embodiment, a calibration module is also provided, so that the user can adjust the value of the second impedance value for multiple times, so as to improve the impedance Matching accuracy. Specifically, the calibration module is also used to provide a corresponding signal simulation eye diagram, so as to measure the effect of impedance matching through the signal quality.

As a specific embodiment, on the basis of the above-mentioned content, the training module 104 is specifically used for:

According to the preset DDR string impedance calculation formula, calculate the overall impedance value of the sample DDR string after the DDR particles reduce the trace impedance; The associated impedance value of the continuous trace; the overall impedance value is used as input, and the range of the corresponding associated impedance value is used as the output to train and generate the DDR string impedance matching model 103 .

Further, the preset DDR string impedance calculation formula is specifically:

Among them, L and C are the parasitic inductance and parasitic capacitance of the continuous traces of the same length as the total length of each trace segment in the DDR string, respectively; m is the total number of DDR particles; C _L is the equivalent capacitance of DDR particles; X is each The length of a trace segment.

It should be noted that, generally, the relationship between the number n of wiring segments and the total number m of DDR particles is: m=n+1.

As for the formula for calculating the impedance of the continuous trace, a conventional formula in the technical field can be used, which is not limited in this application.

Referring to FIG. 3 , an embodiment of the present application further discloses an impedance matching method for PCB wiring of a solid-state hard disk.

The solid-state hard disk includes a main control chip and a DDR string connected by backbone wires, and the DDR string includes a plurality of DDR particles connected in series by wire segments. The impedance matching method provided by this application includes:

S201: Determine the first impedance value of the trunk line and use it as the actual impedance value of the DDR string.

S202: Use the first line width of the continuous wiring calculated based on the first impedance value and the stacking parameter as the line width of the trunk wiring.

S203: Invoke the impedance matching model, and output the impedance value range of the continuous trace corresponding to the actual impedance value and equal to the total length of each trace segment in the DDR string; the lower limit of the impedance value range is greater than the actual impedance value .

Among them, the impedance matching model is pre-trained and generated based on the impact on the impedance reduction of the continuous wiring after the DDR particles are connected in series.

S204: Receive an input second impedance value whose value is within an impedance value range.

S205: Use the second line width of the continuous line calculated based on the second impedance value and the stacking parameter as the line width of the line segment.

It can be seen that the impedance matching method for the PCB traces of the solid-state hard disk provided by the present application takes into account the impact on the impedance reduction of the continuous traces after the DDR particles are connected in series. The impedance value after each DDR particle, that is, the actual impedance value of the DDR string, is equal to the first impedance value of the trunk line, thus effectively realizing the impedance matching of the entire link, ensuring the integrity and transmission rate of the DDR signal, and improving the Signal quality; in addition, the application does not need to add components such as resistors, capacitors, etc., which effectively saves cost and layout space, and is efficient and convenient.

As a specific embodiment, the impedance matching method for the PCB wiring of the solid-state hard disk provided by the embodiment of the present application determines the first impedance value of the main wiring on the basis of the above content, including:

Receive the model information and signal type information of the input main control chip;

As a specific embodiment, the impedance matching method for the PCB wiring of the solid-state hard disk provided by the embodiment of the present application is based on the above content, and after receiving the input second impedance value whose value is within the impedance value range, Also includes:

According to the input second impedance value, a signal simulation eye diagram is generated, so that the user can adjust the second impedance value according to the effect of the signal simulation eye diagram.

As a specific embodiment, the impedance matching method for the PCB routing of the solid-state hard disk provided by the embodiment of the present application is based on the above content, and the training process of the impedance matching model can be specifically referred to FIG. 4, which mainly includes the following steps:

S301 : According to a preset DDR string impedance calculation formula, calculate the overall impedance value of the sample DDR string after the DDR chip reduces the trace impedance.

S302 : Calculate, according to the formula for calculating the impedance of the continuous wiring, the associated impedance value of the continuous wiring that is equal to the total length of each wiring segment in the sample DDR string.

S303: Taking the overall impedance value as input, and taking the value range of the corresponding associated impedance value as output, train to generate a DDR string impedance matching model.

Wherein, further, the preset DDR string impedance calculation formula is specifically:

As a specific embodiment, the impedance matching method of the solid-state drive PCB trace provided by the embodiment of the present application is based on the above content, and the stacking parameters include the copper foil thickness of the PCB board, the dielectric constant of the board, and the board thickness.

For the specific content of the impedance matching method for the above-mentioned solid-state drive PCB wiring, reference may be made to the foregoing detailed introduction on the impedance matching device for the solid-state hard drive PCB wiring, which will not be repeated here.

Referring to FIG. 5 , an embodiment of the present application discloses an electronic device, including:

memory 401 for storing computer programs;

The processor 402 is configured to execute the computer program to implement the steps of any of the above-mentioned impedance matching methods for PCB traces of the solid-state hard disk.

Further, an embodiment of the present application also discloses a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and the computer program is used to implement any of the above when executed by a processor. The steps of the impedance matching method of the PCB trace of the solid state drive.

For the specific content of the electronic device and the computer-readable storage medium, reference may be made to the foregoing detailed introduction on the impedance matching device for the PCB wiring of the solid-state drive, which will not be repeated here.

The various embodiments in this application are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments may be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant part can be referred to the description of the method.

It should also be noted that, in this application document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require Or imply that there is any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising", "comprising" or any other variation thereof are intended to encompass non-exclusive inclusion such that a process, method, article or device comprising a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

The technical solutions provided by the present application have been introduced in detail above. Specific examples are used herein to illustrate the principles and implementations of the present application, and the descriptions of the above embodiments are only used to help understand the methods and core ideas of the present application. It should be pointed out that for those skilled in the art, without departing from the principles of the present application, several improvements and modifications can also be made to the present application, and these improvements and modifications also fall within the protection scope of the present application.

Claims

An impedance matching device for PCB wiring of a solid-state hard disk, characterized in that the solid-state hard disk comprises a main control chip and a DDR string connected by a backbone wiring, and the DDR string comprises a plurality of DDR particles connected in series by wiring segments ; The impedance matching device includes:

The line width calculation module is used to calculate the line width of the corresponding continuous trace according to the input impedance value and stacking parameters;

The first line width determination module is used to determine the first impedance value of the trunk line, and use it as the actual impedance value of the DDR string; call the line width calculation module, which will be calculated based on the first impedance value. The first line width of is used as the line width of the trunk line;

The impedance matching model is used to output the impedance value range of the continuous trace corresponding to the actual impedance value and having the same length as the total length of each trace segment in the DDR string; the lower limit of the impedance value range value is greater than the actual impedance value;

a training module, configured to pre-train and generate the impedance matching model according to the impact on the impedance reduction of the continuous wiring after the DDR particles are connected in series;

The second line width determination module is used to receive the input second impedance value whose value is within the impedance value range; call the line width calculation module, and use the second line width calculated based on the second impedance value as the line width of the trace segment.
The impedance matching device according to claim 1, wherein the first line width determination module is specifically used for:

Receive the input model information and signal type information of the main control chip; query a chip database to obtain the first impedance value corresponding to the model information and the signal type information.
The impedance matching device according to claim 1, further comprising:

The calibration module is configured to generate a signal simulation eye diagram according to the input second impedance value, so that the user can adjust the second impedance value according to the effect of the signal simulation eye diagram.
The impedance matching device according to claim 1, wherein the training module is specifically used for:

According to the preset DDR string impedance calculation formula, calculate the overall impedance value of the sample DDR string after the DDR particles reduce the trace impedance; according to the continuous trace impedance calculation formula, calculate the total length of each trace segment in the sample DDR string, etc. The associated impedance value of the long continuous trace; taking the overall impedance value as an input, and taking the corresponding value range of the associated impedance value as an output, training to generate the DDR string impedance matching model.
The impedance matching device according to claim 4, wherein the preset DDR string impedance calculation formula is specifically:

Wherein, L and C are the parasitic inductance and parasitic capacitance of the continuous traces of the same length as the total length of each trace segment in the DDR string, respectively; m is the total number of DDR particles; C L is the equivalent capacitance of the DDR particles; X is the length of each trace segment.
The impedance matching device according to any one of claims 1 to 5, wherein the stacking parameters include copper foil thickness, sheet dielectric constant and sheet thickness of the PCB board.
An impedance matching method for PCB wiring of a solid-state hard disk, characterized in that the solid-state hard disk comprises a main control chip and a DDR string connected by a backbone wiring, and the DDR string comprises a plurality of DDR particles connected in series by wiring segments; The impedance matching method includes:

determining the first impedance value of the trunk line as the actual impedance value of the DDR string;

Taking the first line width of the continuous wiring calculated based on the first impedance value and the stacking parameters as the line width of the trunk wiring;

Invoke the impedance matching model, and output the impedance value range of the continuous trace corresponding to the actual impedance value and equal to the total length of each trace segment in the DDR string; the lower limit of the impedance value range greater than the actual impedance value;

receiving an input second impedance value whose value is within the impedance value range;

Using the second line width of the continuous trace calculated based on the second impedance value and the stacking parameter as the line width of the trace segment;

Wherein, the impedance matching model is pre-trained and generated based on the impact on the impedance reduction of the continuous wiring after the DDR particles are connected in series.
The impedance matching method according to claim 7, wherein the training process of the impedance matching model comprises:

According to the preset DDR string impedance calculation formula, calculate the overall impedance value of the sample DDR string after the DDR particles reduce the trace impedance;

According to the formula for calculating the impedance of the continuous trace, calculate the associated impedance value of the continuous trace that is equal to the total length of each trace segment in the sample DDR string;

Taking the overall impedance value as an input, and taking the corresponding range of the associated impedance value as an output, the DDR string impedance matching model is generated by training.
An electronic device, comprising:

memory for storing computer programs;

The processor is configured to execute the computer program to implement the steps of the impedance matching method for the PCB wiring of the solid-state hard disk according to claim 7 or 8.
A computer-readable storage medium, characterized in that, a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, it is used to realize the solid-state hard disk PCB operation according to claim 7 or 8. The steps of the line impedance matching method.