CN112906342A - Method and device for setting clock tree wiring rule - Google Patents
Method and device for setting clock tree wiring rule Download PDFInfo
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Abstract
The application provides a method and a device for setting a clock tree wiring rule, wherein the method comprises the following steps: obtaining a total value of the dynamic power consumption and the holding time violation of the clock tree according to the wiring width and the wiring interval; calculating to obtain a wiring factor according to the dynamic power consumption of the clock tree and the total value of the holding time violation; cooperatively optimizing the wiring width and the wiring interval to minimize the wiring factor; since the routing factors are positively correlated to the absolute values of the total values of the clock tree dynamic power consumption and hold time violations, respectively; when the wiring factor is minimum, the requirement that the dynamic power consumption of the clock tree is low and the requirement that the hold time of the clock tree is less than a certain violation are met.
Description
Technical Field
The present disclosure relates to the field of integrated circuit design, and in particular, to a method and an apparatus for setting clock tree routing rules.
Background
The clock tree is a mesh structure built by balancing a plurality of buffer cells (buffer cells), and can manage clock signals in a clock domain, so that the clock edge of a register in the clock domain is ensured to be minimum, and good timing sequence characteristics are ensured. In a traditional clock tree comprehensive design flow, a low-power-consumption design aiming at a clock tree wiring rule is not provided, and the dynamic power consumption of the clock tree set according to the traditional wiring rule is probably higher. Therefore, how to reduce the dynamic power consumption of the clock tree is an urgent technical problem to be solved in the field.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a method and an apparatus for setting a clock tree wiring rule, which can reduce dynamic power consumption of a clock tree and satisfy that there are few violations of a retention time of the clock tree.
In a first aspect, the present application provides a method for setting clock tree routing rules, including:
obtaining a total value of the dynamic power consumption and the holding time violation of the clock tree according to the wiring width and the wiring interval;
calculating to obtain a wiring factor according to the dynamic power consumption of the clock tree and the total value of the holding time violation; the routing factors are positively correlated to absolute values of the clock tree dynamic power consumption and the total hold time violation values, respectively;
the routing width and the routing pitch are co-optimized to minimize the routing factor.
Optionally, the calculating a wiring factor according to the clock tree dynamic power consumption and the total value of the hold time violation includes:
taking a product of a square of the clock tree dynamic power consumption and an absolute value of the total hold time violation value as the routing factor.
Optionally, the cooperatively optimizing the wiring width and the wiring pitch to minimize the wiring factor includes:
setting the wiring space as an initial wiring space, and adjusting the initial wiring width by a first step length to minimize the wiring factor to obtain an optimal wiring width;
and setting the wiring width as the optimal wiring width, and adjusting the initial wiring interval by a second step length to minimize the wiring factor to obtain the optimal wiring interval.
Optionally, the dynamic power consumption of the clock tree includes: clock tree short circuit power consumption and clock tree switching power consumption.
Optionally, the total value of the hold time violation is obtained according to a pre-established model; and the pre-established model is used for analyzing the input wiring width and wiring interval to obtain the total holding time violation value.
In a second aspect, the present application provides an apparatus for setting clock tree routing rules, including:
the first calculation unit is used for obtaining the total value of the dynamic power consumption and the holding time violation of the clock tree according to the wiring width and the wiring distance;
the second calculation unit is used for calculating and obtaining a wiring factor according to the dynamic power consumption of the clock tree and the total value of the holding time violation; the routing factors are positively correlated to absolute values of the clock tree dynamic power consumption and the total hold time violation values, respectively;
an optimization unit for co-optimizing the wiring width and the wiring pitch to minimize the wiring factor.
Optionally, the second computing unit includes:
a second calculation unit subunit configured to use, as the wiring factor, a product of a square of the clock tree dynamic power consumption and an absolute value of the total hold time violation value.
Optionally, the optimization unit includes:
a first adjusting unit, configured to set the wiring pitch as an initial wiring pitch, and adjust an initial wiring width by a first step length to minimize the wiring factor, so as to obtain an optimal wiring width;
and the second adjusting unit is used for enabling the wiring width to be the optimal wiring width, and adjusting the initial wiring distance by a second step length to minimize the wiring factor to obtain the optimal wiring distance.
Optionally, the dynamic power consumption of the clock tree includes: clock tree short circuit power consumption and clock tree switching power consumption.
Optionally, the apparatus further comprises:
and the analysis unit is used for analyzing the wiring width and the wiring interval input into the model according to a pre-established model to obtain the total value of the holding time violation.
The embodiment of the application provides a method and a device for setting a clock tree wiring rule, which can obtain a clock tree dynamic power consumption and a holding time violation total value according to wiring width and wiring distance, and calculate to obtain a wiring factor according to the clock tree dynamic power consumption and the holding time violation total value; cooperatively optimizing the wiring width and the wiring interval to minimize the wiring factor; the wiring factors are positively correlated with the absolute values of the dynamic power consumption of the clock tree and the total value of the holding time violation respectively; when the wiring factor is minimum, the requirement that the dynamic power consumption of the clock tree is low and the requirement that the hold time of the clock tree is less than a certain violation are met.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a flow chart illustrating a conventional clock tree synthesis design provided by an embodiment of the present application;
FIG. 2 is a schematic diagram of a metal wiring provided in an embodiment of the present application;
FIG. 3 is an analysis diagram illustrating setup and hold times provided by embodiments of the present application;
FIG. 4 is a flowchart illustrating a method for setting clock tree routing rules according to an embodiment of the present application;
fig. 5 is a schematic diagram illustrating a setting apparatus for clock tree routing rules according to an embodiment of the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited by the specific embodiments disclosed below.
As described in the background, referring to fig. 1, the clock tree design flow in the conventional digital integrated circuit back-end physical design is as follows:
the first step is as follows: check before clock tree synthesis (check _ physical _ design). Checking whether the design is completely laid out and the clock constraint is set;
the second step is that: removal of the ideal clock (remove _ ideal _ network). Removing the ideal attribute of the clock;
the third step: setting of clock tree constraints (set _ clock _ tree _ options). Constraint settings including maximum clock skew, maximum fan-out, maximum capacitance, etc.;
the fourth step: set _ clock _ tree _ references of the clock tree driver. Setting the type of a clock tree driver and selecting the driving capability;
the fifth step: setting of clock tree routing rule (define _ routing _ rule). The method comprises the steps of selecting a wiring metal layer, wiring width, wiring distance and arranging through holes;
and a sixth step: clock tree synthesis (clock tree synthesis) is performed.
Namely, in the traditional clock tree comprehensive design flow in the digital integrated circuit back-end physical design, although the step of setting the wiring rule exists, the low-power consumption design of the clock tree is not available. Therefore, a specific design method is needed to guide the setting of the routing rule, so as to implement the low power consumption design of the clock tree.
The calculation formula of the dynamic power consumption of the clock tree is shown as formula (1):
wherein，PdynamicDynamic power consumption for clock trees; pshortShort circuit power consumption for the clock tree; pswitchThe switching power consumption of the clock tree; alpha is a clock conversion factor; k is a transistor constant; τ is the transition time of the clock signal, i.e., the rise time or fall time of the clock signal; f. ofclkIs the clock frequency; vDDIs the supply voltage; vthIs the transistor threshold voltage; coutputIs a load capacitance; in the present application, it is assumed that the rise time and the fall time of the clock signal are equal.
From (1), it can be seen that, under the premise of not changing circuit performance, working frequency, voltage and manufacturing process, the clock signal conversion time tau and the clock network load capacitance C are reducedoutputCan reduce the dynamic power consumption P of the clock treedynamicAnd the arrangement of the width and spacing of the metal layers in the clock tree wiring rules can affect the transition time of the clock signal and the load capacitance of the clock network.
According to the signal and system knowledge, the conversion time tau of the clock signal is r0c0(r0、c0Respectively, a resistance and a capacitance driven by a signal). For a clock network, a signal driven resistor r0Output impedance R of logic cell including signal drive0And parasitic resistance r of interconnection line, then
r0＝R0+r (2)
Signal driven capacitor c0By the input capacitance C of the standard cell0And a parasitic capacitance c of the interconnection line, having
c0＝C0+c (3)
After the integrated circuit enters deep submicron, along with the expansion of the chip scale, the length, the width and the spacing of the interconnection line are increased, and simultaneously, the capacitance and the resistance of the interconnection line become main components of interconnection delay, and the resistance and the capacitance of an active device can be ignored. Therefore, there are:
modeling the wiring structure of the clock network, referring to fig. 2, which is a schematic diagram of metal wiring, the parasitic resistance r and the parasitic capacitance c of the interconnection line can be expressed as:
wherein, cAdjacent layer、cSame layer、cSame direction layer、cTo the groundThe capacitance between the clock signal line and the adjacent layer metal, the capacitance between the parallel adjacent layer metal and the parasitic capacitance to the ground are respectively. srρ is the resistivity of the clock signal line, h is the thickness of the metal line, and w is the width of the metal line, which is the cross-sectional area of the clock signal line. Epsilon1、ε2、ε3And ε4Is the dielectric constant of the capacitor, d1、d2、d3And d4The distance between the clock signal line and the adjacent metal layer, the distance between the metal layers on the same layer, the vertical distance between the metal layers on the adjacent layers in parallel and the distance between the clock signal line and the ground are respectively. l is the length of the clock signal line itself, l1x(x＝1,2,3...)、l2y(y＝1,2,3...)、l3z(z 1,2, 3.) is the length of the area of each segment of the clock signal line opposite to the adjacent layer metal, the length of each segment of the clock signal line opposite to the same layer metal, the length of each segment of the clock signal line opposite to the parallel adjacent metal, and l4Lambda is the coefficient of the relative area of capacitance between the parallel adjacent metal layers, and the larger the width is, the larger the relative area is.
Substituting the calculation formula combining the formulas (4) and (5) into the formula (1) to obtain:
for short-circuit power consumption and switching power consumption in dynamic power consumption, there are:
where k is the transistor constant and c is the interconnect parasitic capacitance.
Assuming that copper is adopted as an interconnection line in a chip process, the resistivity at normal temperature is 0.0185 omega mm2And m is 0.0185 omega. um, the width w and the thickness h of the interconnection line are both less than 1 micron, and the length of the clock tree interconnection line is in the millimeter order. Let w be 0.2um, h 0.2um, and l 2 mm. The constant k of a typical MOS transistor is about several hundred uA/V and the power supply voltage V is setDDTaking 1.2V, expression (7) can be transformed into:
as can be seen from (8), among the dynamic power consumptions, the switching power consumption is dominant. The length l of the clock signal line is determined by the position of each clock input point such as a register, so the size of the clock signal line is basically kept unchanged, d1、d3Also a fixed value. Thus the metal line width w for the clock network and the metal line wiring spacing d for the clock network2These two variables, the switch power consumption P according to equation (6)switchThe dynamic power consumption of the clock tree can be reduced by reducing the width of the metal wire of the clock network; increasing the spacing between clock network metal lines may also reduce clock tree dynamic power consumption. As can be seen from the formula (6), the reduction of the width w of the clock network metal lines has little effect on the area, and the increase of the spacing d of the clock network metal lines2The wiring layout rate is affected and the chip area may be increased. Therefore, in reducing dynamic power consumption, the width w of the clock network metal lines can be optimized first, and then the distance d of the clock network metal lines can be optimized2。
From the formula (6), it can be known that the timing of the clock tree is influenced to some extent while the width of the metal lines of the clock network is reduced and the metal line pitch of the clock network is increased. That is, formula (3) PshortSecond item in parentheses
The clock tree is a part of the conversion time, reducing the width of the metal wires of the clock network increases the conversion time of the clock signal, increasing the distance between the metal wires of the clock network decreases the conversion time of the clock signal, and further affects the timing sequence of the clock tree.
On the premise of satisfying the constraint condition of the same maximum clock signal transition time max _ transition, compared with the clock tree design before the wiring rule is not changed, after reducing the metal wire width of the clock network and increasing the metal wire spacing of the clock network in order to reduce the dynamic power consumption of the clock tree, the comprehensive effect is that the clock tree driving capability is relatively low and the transition time of the clock tree is relatively long. The effect on the setup time and hold time checks at this point is shown in figure 3. CLK is the clock signal, T2setup and T2hold are the setup and hold times, respectively, for the data signal after reducing the width of the clock network metal lines and increasing the spacing of the metal lines of the clock network, and T1setup and T1hold are the setup and hold times, respectively, for the data signal before modifying the wiring rules. For the setup time: as shown in fig. 3, it is apparent that T2setup > T1setup, and thus the time for which the data signal remains stable until the clock active edge arrives becomes large after the wiring rule is modified, and thus it is advantageous for the check of the setup time; for the retention time: t2hold < T1hold, i.e., after the wiring rule is modified, the holding time of the data signal becomes smaller than that before the rule is modified, and therefore, the check of the holding time is disadvantageous. The hold time timing is adversely affected while reducing dynamic power consumption by reducing the width of the metal lines of the clock network and increasing the spacing between the metal lines of the clock network.
Therefore, the present application provides a method for setting a clock tree wiring rule, which can reduce dynamic power consumption of a clock tree and ensure that a total value of a hold time violation is small.
Exemplary method
Referring to fig. 4, a flowchart of a method for setting a clock tree routing rule provided in an embodiment of the present application includes:
s101: and obtaining the total value of the dynamic power consumption and the holding time violation of the clock tree according to the wiring width and the wiring distance.
In the embodiment of the present application, as can be seen from the formula (6), it is possible to obtain the wiring width w and the wiring pitch d2And calculating other parameters to obtain dynamic power consumption P of the clock treedynamicAnd can be determined according to the wiring width w and the wiring pitch d2And inputting a pre-established model to obtain a total holding time violation value TNS with the unit of ns.
S102: calculating to obtain a wiring factor according to the dynamic power consumption of the clock tree and the total value of the holding time violation; the routing factors are positively correlated to absolute values of the clock tree dynamic power consumption and the total hold time violation values, respectively;
in the embodiment of the application, in order to reduce the dynamic power consumption of the clock tree and ensure that the total value of the hold time violation is less, a parameter of a wiring factor is provided, so that two variables of the hold time sequence and the dynamic power consumption of the clock tree can be optimized together, the dynamic power consumption of the clock tree is low, and the hold time violation of the whole system is less.
The wiring factors are respectively positively correlated with the clock tree dynamic power consumption and the absolute value of the total value of the holding time violation, so that when the wiring factor is minimum, the requirements that the clock tree dynamic power consumption is low and the absolute value of the total value of the holding time violation is low are met.
In particular, the routing factor may be equal to the product of the square of the clock tree dynamic power consumption and the absolute value of the total hold time violation, i.e., Q ═ Pdynamic 2xxTNS, where Q is the routing factor, PdynamicFor clock tree dynamic power consumption, TNS is the total hold time violation.
S103: the routing width and the routing pitch are co-optimized to minimize the routing factor.
In the embodiment of the present application, since the wiring factors are positively correlated to the absolute values of the total values of the dynamic power consumption and the hold time violations of the clock tree, respectively, and changing the wiring width and the wiring pitch of the clock tree can change the absolute values of the total values of the dynamic power consumption and the hold time violations of the clock tree, the wiring width and the wiring pitch can be cooperatively optimized to minimize the wiring factors.
The wiring width and the wiring pitch are cooperatively optimized to minimize the wiring factor, which may be:
setting the wiring interval as an initial wiring interval, and adjusting the initial wiring width by the first step length to minimize a wiring factor to obtain an optimal wiring width; and then, the wiring width is set as the optimal wiring width, and the initial wiring distance is adjusted by the second step length to minimize the wiring factor, so that the optimal wiring distance is obtained.
Specifically, after the initial wiring rule is set, the wiring metal layer is selected, and the wiring width, the wiring pitch, and the through hole are set, the wiring pitch is set to the initial wiring pitch s0, the initial wiring width is set to w0, and from s0 and w0, i and j are set to 0, and the initial wiring factor Q (i, j) is calculated to be Q (0,0), and Q is the wiring factor.
The wiring pitch is kept unchanged at the initial wiring pitch s (j) ═ s0, the wiring width is reduced by the first step length β, that is, w (i +1) ═ w (i) — β, then the existing clock tree is removed, the clock tree synthesis is performed again, and the Q value Q (i +1, j) is calculated.
A Q value Q (i +1, j) obtained by judging whether the width w (i +1) is smaller than the Q value Q (i, j) obtained before the width is reduced is obtained, and the width w (i +1) after the width is reduced is larger than the minimum wiring width. If so, let i equal i +1, continue to reduce the wiring width by the first step length, otherwise, obtain the width value w (i) before reducing the width as the optimum wiring width wopt。
When the optimal wiring width w is obtained by calculationoptAnd then, adjusting the initial wiring distance by the second step length to minimize the wiring factor to obtain the optimal wiring distance.
Specifically, the wiring width can be made to be the optimum wiring width woptThe wiring pitch is increased by a second step γ, that is, s (j +1) ═ s (j) + γ, the existing clocks are removed, clock tree integration is performed again, and a Q value Q (i, j +1) is calculated.
Judging whether the increased spacing is s (j +1) or notThe obtained Q value Q (i, j +1) is smaller than the Q value Q (i, j) obtained before increasing the pitch. If so, let j equal to j +1, continue to increase the wiring pitch by the second step length, otherwise, obtain the width value s (j) before increasing the pitch as the optimal wiring pitch sopt。
At the moment, the optimal wiring width and the optimal wiring interval corresponding to the optimal wiring factor are used as the comprehensive wiring parameters of the low-power-consumption clock tree, so that the dynamic low power consumption of the clock tree is met, and the condition that the retention time violation is less is met.
The embodiment of the application provides a method for setting a clock tree wiring rule, which can obtain a total value of clock tree dynamic power consumption and holding time violation according to wiring width and wiring distance, and calculate a wiring factor according to the total value of clock tree dynamic power consumption and holding time violation; cooperatively optimizing the wiring width and the wiring interval to minimize the wiring factor; the wiring factors are positively correlated with the absolute values of the dynamic power consumption of the clock tree and the total value of the holding time violation respectively; when the wiring factor is minimum, the requirement that the dynamic power consumption of the clock tree is low and the requirement that the hold time of the clock tree is less than a certain violation are met.
Exemplary devices
Referring to fig. 5, a schematic diagram of a setting apparatus for clock tree routing rules according to an embodiment of the present application is provided. The method can comprise the following steps:
a first calculating unit 201, configured to obtain a total value of dynamic power consumption and retention time violation of the clock tree according to the wiring width and the wiring distance;
a second calculating unit 202, configured to calculate a wiring factor according to the clock tree dynamic power consumption and the total value of the hold time violation; the routing factors are positively correlated to absolute values of the clock tree dynamic power consumption and the total hold time violation values, respectively;
an optimizing unit 203 for cooperatively optimizing the wiring width and the wiring pitch to minimize the wiring factor.
In some embodiments, the second computing unit 202 includes:
a second calculation unit subunit configured to use, as the wiring factor, a product of a square of the clock tree dynamic power consumption and an absolute value of the total hold time violation value.
In some embodiments, the optimizing unit 203 includes:
a first adjusting unit, configured to set the wiring pitch as an initial wiring pitch, and adjust an initial wiring width by a first step length to minimize the wiring factor, so as to obtain an optimal wiring width;
and the second adjusting unit is used for enabling the wiring width to be the optimal wiring width, and adjusting the initial wiring distance by a second step length to minimize the wiring factor to obtain the optimal wiring distance.
In some embodiments, the clock tree dynamically consumes power, including: clock tree short circuit power consumption and clock tree switching power consumption.
In some embodiments, the apparatus further comprises:
and the analysis unit is used for analyzing the wiring width and the wiring interval input into the model according to a pre-established model to obtain the total value of the holding time violation.
The embodiment of the application provides a device for setting a clock tree wiring rule, which can obtain a total value of clock tree dynamic power consumption and holding time violation according to wiring width and wiring distance, and calculate a wiring factor according to the total value of clock tree dynamic power consumption and holding time violation; cooperatively optimizing the wiring width and the wiring interval to minimize the wiring factor; the wiring factors are positively correlated with the absolute values of the dynamic power consumption of the clock tree and the total value of the holding time violation respectively; when the wiring factor is minimum, the requirement that the dynamic power consumption of the clock tree is low and the requirement that the hold time of the clock tree is less than a certain violation are met.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, it is relatively simple to describe, and reference may be made to some descriptions of the method embodiment for relevant points.
The foregoing is merely a preferred embodiment of the present application and, although the present application discloses the foregoing preferred embodiments, the present application is not limited thereto. Those skilled in the art can now make numerous possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the claimed embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still fall within the protection scope of the technical solution of the present application without departing from the content of the technical solution of the present application.
Claims (10)
1. A method for setting clock tree wiring rules is characterized by comprising the following steps:
obtaining a total value of the dynamic power consumption and the holding time violation of the clock tree according to the wiring width and the wiring interval;
calculating to obtain a wiring factor according to the dynamic power consumption of the clock tree and the total value of the holding time violation; the routing factors are positively correlated to absolute values of the clock tree dynamic power consumption and the total hold time violation values, respectively;
the routing width and the routing pitch are co-optimized to minimize the routing factor.
2. The method of claim 1, wherein calculating a routing factor from the clock tree dynamic power consumption and the total hold time violation value comprises:
taking a product of a square of the clock tree dynamic power consumption and an absolute value of the total hold time violation value as the routing factor.
3. The method of claim 1, wherein the co-optimizing the routing width and the routing pitch to minimize the routing factor comprises:
setting the wiring space as an initial wiring space, and adjusting the initial wiring width by a first step length to minimize the wiring factor to obtain an optimal wiring width;
and setting the wiring width as the optimal wiring width, and adjusting the initial wiring interval by a second step length to minimize the wiring factor to obtain the optimal wiring interval.
4. The method of claim 1, wherein the clock tree dynamically consumes power, comprising: clock tree short circuit power consumption and clock tree switching power consumption.
5. The method of claim 1, wherein the total hold time violation value is derived from a pre-established model; and the pre-established model is used for analyzing the input wiring width and wiring interval to obtain the total holding time violation value.
6. An apparatus for setting a clock tree wiring rule, comprising:
the first calculation unit is used for calculating and obtaining the total value of the dynamic power consumption and the holding time violation of the clock tree according to the wiring width and the wiring distance;
the second calculation unit is used for obtaining a wiring factor according to the dynamic power consumption of the clock tree and the total value of the holding time violation; the routing factors are positively correlated to absolute values of the clock tree dynamic power consumption and the total hold time violation values, respectively;
an optimization unit for co-optimizing the wiring width and the wiring pitch to minimize the wiring factor.
7. The apparatus of claim 6, wherein the second computing unit comprises:
a second calculation unit subunit configured to use, as the wiring factor, a product of a square of the clock tree dynamic power consumption and an absolute value of the total hold time violation value.
8. The apparatus of claim 6, wherein the optimization unit comprises:
a first adjusting unit, configured to set the wiring pitch as an initial wiring pitch, and adjust an initial wiring width by a first step length to minimize the wiring factor, so as to obtain an optimal wiring width;
and the second adjusting unit is used for enabling the wiring width to be the optimal wiring width, and adjusting the initial wiring distance by a second step length to minimize the wiring factor to obtain the optimal wiring distance.
9. The apparatus of claim 6, wherein the clock tree dynamically consumes power, comprising: clock tree short circuit power consumption and clock tree switching power consumption.
10. The apparatus of claim 6, further comprising:
and the analysis unit is used for analyzing the wiring width and the wiring interval input into the model according to a pre-established model to obtain the total value of the holding time violation.
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| CN202110290928.8A CN112906342A (en) | 2021-03-18 | 2021-03-18 | Method and device for setting clock tree wiring rule |
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| CN202110290928.8A CN112906342A (en) | 2021-03-18 | 2021-03-18 | Method and device for setting clock tree wiring rule |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN114662446B (en) * | 2022-03-29 | 2024-05-03 | 东科半导体(安徽)股份有限公司 | Wiring optimization method for reducing dynamic power consumption |
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