CN107423491A - A kind of compensation calculation method of the line length matching of differential pair across pcb board - Google Patents
A kind of compensation calculation method of the line length matching of differential pair across pcb board Download PDFInfo
- Publication number
- CN107423491A CN107423491A CN201710509754.3A CN201710509754A CN107423491A CN 107423491 A CN107423491 A CN 107423491A CN 201710509754 A CN201710509754 A CN 201710509754A CN 107423491 A CN107423491 A CN 107423491A
- Authority
- CN
- China
- Prior art keywords
- pcb board
- differential pair
- line
- differential
- pair
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
Abstract
The present invention relates to electronic circuit technology field, the compensation calculation method of the line length matching of specially a kind of differential pair across pcb board, a kind of formula of the present invention
Description
Technical field
The present invention relates to electronic circuit technology field, more particularly to a kind of benefit of the line length matching of differential pair across pcb board
Repay computational methods.
Background technology
At present, high-speed-differential occupies critical role to being routed in PCB design, designs successful key and seeks to ensure system
System has the sequential allowance of abundance, and the purpose to the control of sequential allowance is to ensure that data have settling time and the guarantor of abundance in receiving terminal
Hold the time.Ensure the sequential allowance of system, line length matching is an important link, is exactly by sequential for differential pair
Allowance is converted into length difference of that in differential pair to differential lines.
For needing for A plates are transferred to the differential pair of B plates, total length includes the length on A plates, plus on B plates
Length, along with the length of the pin of connection stand.Length wherein on A plates and B plates is adjustable in PCB design, and is connected
The length of the pin of joint chair is then fixed.Because in stand is connected, the pin of a pair of differential lines is usually designed to one and entered
One goes out, and causes two pins length difference to be present.Make differential pair isometric, then will be in pcb board on the pin of connection stand
Length difference compensates.
For simplicity, it is assumed that differential lines are isometric in B plates, then the length difference on pin compensates in A plates.
The isometric design method of traditional differential lines be directly using interface stand manufacturer provide 2 pins length difference data (assuming that
It is 50mil), then directly compensate 50mil on single line shorter in a differential pair in PCB design, so that a pair of difference
Line is isometric.According to formula T (time)=S (distance)/V (speed), if offset is always maintained at 50mil, with the biography of signal
Defeated speed is more and more faster, and when transmission rate reaches some critical point, i.e., T values can not ensure that system has the sequential allowance of abundance
When, signal transmission will be made the unmatched situation of sequential occur.
To sum up, it is ensured that system has the sequential allowance of abundance, and when transmission rate is lifted, length offset also needs to change therewith
Become, to ensure that sequential allowance is maintained at a stable value.It is not the thing according to the pin of connection stand to compensate how much length
Length difference is managed to calculate, but is calculated according to the transmission rate of signal., under the increasingly faster background of signal transmission rate
Designer is asked to need further minute design when designing isometric, to accord with the demands of the market.
The content of the invention
The present invention is converted on PCB exactly in view of the above-mentioned problems, providing a kind of pin length difference by connection stand
The compensation calculation method of the line length matching of the differential pair across pcb board for the offset that differential pair needs.
To achieve the above object, the present invention uses following technical scheme：
A kind of compensation calculation method of the line length matching of differential pair across pcb board, the pcb board is multi-layer sheet, the PCB
Plate is provided with connection stand, and the connection stand is provided with a pair of pins for being used for setting differential pair, it is characterised in that including following
Step：
It is poor to calculate transmission duration：The transmission duration of a pair of pins for the differential pair for connecting stand is subtracted each other, when obtaining transmission
Length is poor；
Calculate line delay：Wherein line delay calculates according to equation below：Wherein D represents line
Delay, unit ps/inch, εrRepresent the relative dielectric constant of a certain layer in pcb board；
Calculate the offset of compensating length required for differential lines in differential pair：Wherein offset calculates according to equation below：
Offset=transmission duration difference/line time delay.
Further, in pcb board a certain layer relative dielectric constant εrSo calculate：By the dielectric of neighbouring layer
Constant phase adduction divided by two, obtain the relative dielectric constant ε of this layerr。
Compared with prior art, the beneficial effects of the invention are as follows：Signal is calculated in pcb board by the method for the present invention
Line delay, by line be delayed and connect stand pin length difference, the benefit required for differential lines is precisely calculated
The length repaid, differential pair is reached line length matching, make differential lines internally isometric, the sequential allowance of system is ensure that, so as to ensure
The stable operation of system.
Embodiment
In order to more fully understand the technology contents of the present invention, with reference to specific embodiment to technical scheme
It is described further and illustrates.
Embodiment
Reference picture 1, with a pair of differential lines of PCIE3.0 (PCIE belongs to the point-to-point binary channels high bandwidth transmission of high speed serialization)
Exemplified by carry out across pcb board differential pair line length matching compensation calculation.A pair of differential lines are respectively DP1 and DN1, and two pieces are matched
Plate is respectively A plates and B plates, and differential lines DP1 and DN1 need to be transferred to B plates from A plates.Specific transmission path is from A plate to interface
Stand is connected, then B plates are connected to by the connection stand of docking.In PCB design, the isometric concept of differential pair refers to length difference
Within the specific limits, by taking PCIE3.0 as an example, the control of differential pair length difference is just isometric at last within +/- 2mil for control.
To simplify the compensation method of the explanation present invention, it is assumed that differential lines are isometric in B plates, then the length difference on pin
Then compensated in A plates.
(the manufacturer one in the pin transmission duration for the differential pair that the manufacturer of connection stand provides and the form of transmission duration difference
As can be furnished with the pin transmission duration parameters of connection stand), choose a pair of differential pairs, duration of the signal Jing Guo a pair of pins is distinguished
For：Pin 1 is 207.3ps, and pin 2 is 218.3ps, and it is 11ps that both differences, which transmit duration difference,.To ensure differential lines etc.
Long, the 11ps transmission duration differences of pin need to compensate in A plates.The cabling of pin 1 is lengthened, makes its transmission
Time and pin 2 are equal.
In order to calculate transmission range of the signal in 11ps, it is necessary to calculate line time delay, and line time delay (Delay, referred to as
D), in PCB design it is a very important linear module, unit ps/inch, representing the line time delay of per inch length needs
Psec (ps) number wanted.It is the inverse of speed：1/V.The long-term design taken charge of by me, emulation, measurement practice, when drawing line
The formula prolonged：
Wherein εrRepresent the relative dielectric constant of the material for carrying differential lines.
It is then possible to calculate the length offset of differential lines according to the lamination of pcb board, each layer relative dielectric constant takes
The average of the dielectric constant of lower adjacent layer, it is respectively L03, L05, L10 with pcb board internal layer routing layer, exemplified by L12, above and below L03
The dielectric constant of adjacent layer is 4.1 and 3.49, i.e. the ε of L03 layersr=3.795；The dielectric constant of the neighbouring layers of L05 is 4.1 Hes
3.51, the i.e. ε of L05 layersr=3.805；The dielectric constant of the neighbouring layers of L10 is 4.1 and 3.51, i.e. the ε of L10 layersr=3.805；
The dielectric constant of the neighbouring layers of L12 is 4.1 and 3.49, i.e. the ε of L12 layersr=3.795.
By the formula of line time delayFollowing result can be drawn：
Line time delay D=165.489ps/inch of L03 layers
Line time delay D=165.706ps/inch of L05 layers
Line time delay D=165.706ps/inch of L10 layers
Line time delay D=165.489ps/inch of SL12 layers
Due to pin 1, the transmission duration difference of pin 2 is 11ps, then passes through formula：Offset=transmission duration difference/line
Time delay, you can calculate in L03, L05, L10, the offset that L12 needs is respectively 66.47mil, 66.38mil, 66.38mil,
66.47mil。
From the foregoing, it will be observed that because the dielectric constant of each layer is different, cloth is in the offset that different layer interconnection differential lines need
Different.Relative dielectric constant difference it is bigger, it is necessary to offset difference it is also bigger.Also 2 pins of indirect proof simultaneously
Length difference (this is a fixed value) directly compensate, high-speed-differential line transmission in and it is not rigorous.
The PCB completed according to the design of the result of calculation of the present embodiment, makes differential lines reach length matching, and the system of ensure that has
Sufficient sequential allowance.The present embodiment is having simplicity, ease for use and the advantages of accuracy, pass through in terms of calculating compensating length
Simple mathematical formulae can draw the length that needs compensate.This method is applicable not only to the internally isometric containing differential lines of more flaggies
Pcb board design, be also applied for one group of isometric situation of single line.
The technology contents described above that the present invention is only further illustrated with embodiment, in order to which reader is easier to understand,
But embodiments of the present invention are not represented and are only limitted to this, any technology done according to the present invention extends or recreation, is sent out by this
Bright protection.
Claims (2)
1. a kind of compensation calculation method of the line length matching of differential pair across pcb board, the pcb board is multi-layer sheet, the pcb board
Connection stand is provided with, the connection stand is provided with a pair of pins for being used for setting differential pair, it is characterised in that including following step
Suddenly：
It is poor to calculate transmission duration：The transmission duration of a pair of pins for the differential pair for connecting stand is subtracted each other, it is poor to obtain transmission duration；
Calculate line delay：Wherein line delay calculates according to equation below：Wherein D represents line delay,
Unit is ps/inch, εrRepresent the relative dielectric constant of a certain layer in pcb board；
Calculate the offset of compensating length required for differential lines in differential pair：Wherein offset calculates according to equation below：Compensation
Value=transmission duration difference/line time delay.
2. the compensation calculation method of the line length matching of the differential pair according to claim 1 across pcb board, it is characterised in that：
The relative dielectric constant ε of a certain layer in pcb boardrSo calculate：By the dielectric constant phase adduction of neighbouring layer divided by two,
Obtain the relative dielectric constant ε of this layerr。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710509754.3A CN107423491A (en) | 2017-06-28 | 2017-06-28 | A kind of compensation calculation method of the line length matching of differential pair across pcb board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710509754.3A CN107423491A (en) | 2017-06-28 | 2017-06-28 | A kind of compensation calculation method of the line length matching of differential pair across pcb board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107423491A true CN107423491A (en) | 2017-12-01 |
Family
ID=60426219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710509754.3A Pending CN107423491A (en) | 2017-06-28 | 2017-06-28 | A kind of compensation calculation method of the line length matching of differential pair across pcb board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107423491A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109583094A (en) * | 2018-12-03 | 2019-04-05 | 郑州云海信息技术有限公司 | The long method of benefit and relevant apparatus of high-speed line on a kind of pcb board |
| CN109740272A (en) * | 2019-01-09 | 2019-05-10 | 郑州云海信息技术有限公司 | The inspection method and relevant apparatus of inductive compensation in a kind of PCB |
| CN112507650A (en) * | 2020-11-19 | 2021-03-16 | 浪潮电子信息产业股份有限公司 | Equal-length design method of DDR wiring and related assembly |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5777526A (en) * | 1994-09-01 | 1998-07-07 | Hitachi, Ltd. | Method of manufacturing a microstrip transmission device |
| CN101576936A (en) * | 2008-05-06 | 2009-11-11 | 英业达股份有限公司 | Length monitoring method of signal transmission path |
| CN101841969A (en) * | 2009-03-17 | 2010-09-22 | 鸿富锦精密工业（深圳）有限公司 | Differential signal wire and compensation method for differential signal wire offset |
-
2017
- 2017-06-28 CN CN201710509754.3A patent/CN107423491A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5777526A (en) * | 1994-09-01 | 1998-07-07 | Hitachi, Ltd. | Method of manufacturing a microstrip transmission device |
| CN101576936A (en) * | 2008-05-06 | 2009-11-11 | 英业达股份有限公司 | Length monitoring method of signal transmission path |
| CN101841969A (en) * | 2009-03-17 | 2010-09-22 | 鸿富锦精密工业（深圳）有限公司 | Differential signal wire and compensation method for differential signal wire offset |
Non-Patent Citations (2)
| Title |
|---|
| 刘欢 等: "高速信号时延及过孔对信号完整性影响的研究", 《工业控制计算机》 * |
| 徐鲁杰 等: "差分原理及其在连接其中的应用", 《机电元件》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109583094A (en) * | 2018-12-03 | 2019-04-05 | 郑州云海信息技术有限公司 | The long method of benefit and relevant apparatus of high-speed line on a kind of pcb board |
| CN109583094B (en) * | 2018-12-03 | 2022-03-08 | 郑州云海信息技术有限公司 | Method for compensating length of high-speed line on PCB and related device |
| CN109740272A (en) * | 2019-01-09 | 2019-05-10 | 郑州云海信息技术有限公司 | The inspection method and relevant apparatus of inductive compensation in a kind of PCB |
| CN109740272B (en) * | 2019-01-09 | 2022-03-08 | 郑州云海信息技术有限公司 | PCB (printed circuit board) inductivity compensation checking method and related device |
| CN112507650A (en) * | 2020-11-19 | 2021-03-16 | 浪潮电子信息产业股份有限公司 | Equal-length design method of DDR wiring and related assembly |
| CN112507650B (en) * | 2020-11-19 | 2023-02-28 | 浪潮电子信息产业股份有限公司 | Equal-length design method of DDR wiring and related assembly |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107423491A (en) | A kind of compensation calculation method of the line length matching of differential pair across pcb board | |
| CN101923530B (en) | Adapter card from PCI (Peripheral Component Interconnect) Express X1 to CPCI (Compact Peripheral Component Interconnect) Express X1 | |
| US20060237322A1 (en) | Printed circuit board for improving impedance of signal transmission lines | |
| DE112007000112T5 (en) | Passive impedance equalization of high-speed serial links | |
| CN103718658A (en) | Backboard, insert frame and network equipment | |
| CN103650347B (en) | Equipment and method for deskewing differential signal | |
| DE112019007073T5 (en) | PHASE SYNCHRONIZATION CIRCUIT | |
| US7983374B2 (en) | Methods and systems for providing variable clock rates and data rates for a SERDES | |
| US20190208633A1 (en) | Signal trace fan-out method for double-sided mounting on printed circuit board and printed circuit board | |
| KR20080099147A (en) | Termination compensation for differential signals on glass | |
| KR20090114629A (en) | Crosstalk canceller for semiconductor device | |
| US20090278633A1 (en) | Equalizer and connector including the same | |
| CN103441818B (en) | The detection method of a kind of data transmission fault and device | |
| US10420219B1 (en) | Printed circuit board adaptable for multiple interconnection slots | |
| KR20100037387A (en) | Memory moduel and topology of circuit board | |
| CN219978854U (en) | Multi-port industrial network card | |
| CN107959543A (en) | Based on RACK management board transmission signal jamproof systems and design method | |
| CN116627872B (en) | Method for realizing MIPI interface in FPGA chip and electronic equipment | |
| CN104063349B (en) | System middle back plate and method for realizing data transmission | |
| CN210725503U (en) | PCB assembly of high-speed signal and electronic equipment comprising same | |
| CN220368850U (en) | Main impedance capacitive compensation structure of DDRX interconnection equal-arm branch topology | |
| CN205828800U (en) | Communicator | |
| WO2016197682A1 (en) | Single board | |
| CN208112609U (en) | It is a kind of applied to the Medium Dependent Interface circuit connected in plate | |
| DE102020129017A1 (en) | USB module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20171201 |