CN112486305A - External equipment time sequence control method, computer, mainboard and host thereof - Google Patents
External equipment time sequence control method, computer, mainboard and host thereof Download PDFInfo
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- CN112486305A CN112486305A CN202110153340.8A CN202110153340A CN112486305A CN 112486305 A CN112486305 A CN 112486305A CN 202110153340 A CN202110153340 A CN 202110153340A CN 112486305 A CN112486305 A CN 112486305A
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- external equipment
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
Abstract
The invention discloses a time sequence control method of external equipment, a computer, a mainboard and a host thereof, wherein the computer mainboard comprises a pluggable equipment interface, an external equipment detection circuit and a processor; when detecting that the external equipment is in place, the external equipment detection circuit detects whether the external equipment is powered on or not, and outputs an external equipment state OK signal to the processor when detecting that the external equipment is powered on, and when receiving the external equipment state OK signal, the processor outputs a reset-off signal, outputs the reset-off signal to the external equipment through the pluggable equipment interface and controls the external equipment to reset; the invention realizes the time sequence control between the reset and power-on of the external equipment and avoids the external equipment from being incapable of working because of abnormal reset and power-on time sequences.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a time sequence control method of external equipment, a computer, a mainboard and a host thereof.
Background
With the continuous development of computer technology, the performance of a simple server is increasingly unable to meet the requirements of various data processing services, so that enhancing the data processing capability of the server by externally connecting various devices to the server becomes a feasible scheme and is used in various data processing services.
In practical applications, when the external device is connected to the server, the computer motherboard delays the reset release signal by a delay time to send out the signal, so as to power on the external device for a sufficient time, and then performs reset release on the external device.
Disclosure of Invention
The invention mainly aims to provide a time sequence control method of an external device, a computer, a mainboard and a host thereof, aiming at solving the problem that the time sequence of power-on and reset of the external device connected with the mainboard of the computer is inaccurate.
In order to achieve the above object, the present invention provides a computer motherboard, including:
a circuit board;
the pluggable equipment interface is arranged on the circuit board and is electrically connected with the external equipment in a pluggable way;
the external equipment detection circuit is arranged on the circuit board and is electrically connected with the pluggable equipment interface, and a first detection end and a second detection end of the external equipment detection circuit are respectively and electrically connected with the pluggable equipment interface; when the external equipment is detected to be in place, the external equipment detection circuit detects whether the external equipment is powered on and finished, and outputs an external equipment state OK signal when the external equipment is detected to be powered on and finished;
the input end of the processor is connected with the external equipment detection circuit, and the output end of the processor is connected with the pluggable equipment interface; and the processor is used for outputting a reset signal to the external equipment through the pluggable equipment interface when receiving the state OK signal of the external equipment so as to control the external equipment to reset.
Optionally, the external device detection circuit outputs the external device state OK signal when detecting that the external device is not in place.
Optionally, the external device detection circuit includes:
the first input end of the OR gate logic circuit is the first detection end of the external equipment detection circuit, the second input end of the OR gate logic circuit is the second detection end of the external equipment detection circuit, and the output end of the OR gate logic circuit is connected with the processor.
Optionally, the external device detection circuit further includes:
the first input end of the AND gate logic circuit is connected with the output end of the OR gate logic circuit, and the second input end of the AND gate logic circuit is connected with the power-on completion detection end of the computer mainboard; and the output end of the AND gate logic circuit is connected with the processor.
Optionally, the pluggable device interface is a slot; and/or the pluggable equipment interface is a backboard custom connector.
The invention also provides a time sequence control method of the external equipment, which is applied to the computer mainboard, wherein the computer mainboard comprises a circuit board and the pluggable equipment interface arranged on the circuit board; the external equipment time sequence control method comprises the following steps:
when the pluggable equipment interface detects that the external equipment is in place and the external equipment is detected to be powered on, outputting an external equipment state OK signal;
and when the state OK signal of the external equipment is received, outputting a reset signal to the external equipment through the pluggable equipment interface so as to control the external equipment to reset.
The invention also provides a computer host which comprises the computer mainboard.
The invention also provides a computer, which comprises the external equipment and the computer mainboard or the computer host.
Optionally, the external device has a plug-in card, and the external device is pluggable to the computer motherboard through the plug-in card;
or the external equipment is provided with a connecting terminal, and the connecting terminal can be plugged on the computer mainboard in a pluggable manner through the conductive piece.
The computer mainboard detects whether the external equipment is in place or not and whether the external equipment is powered on or not by arranging the external equipment detection circuit, when the external equipment is detected to be in place, the external equipment detection circuit detects whether the external equipment is powered on or not, and when the external equipment is detected to be powered on, the external equipment state OK signal is output to the processor, and when the external equipment state OK signal is received by the processor, the processor outputs a reset-release signal to the external equipment so as to reset the external equipment; therefore, the problem that the external equipment is incorrect in power-on and reset timing sequence due to the fact that the processor sends out reset signals to the external equipment in advance is solved. And the computer mainboard can not influence the normal work of the computer mainboard because the external equipment is not in place, and can also send out the reset signal to reset other circuit modules of the computer mainboard.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a block diagram of an embodiment of a motherboard of a computer;
FIG. 2 is a circuit diagram of another embodiment of a computer motherboard according to the present invention;
FIG. 3 is a circuit diagram of a motherboard according to another embodiment of the present invention;
fig. 4 is a flowchart of an external device sequential logic control method according to an embodiment of the present invention.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) |
| 10 | |
50 | |
| 20 | Processor with a memory having a plurality of |
60 | Power-on completion detection terminal of |
| 30 | External |
31 | AND |
| 40 | Said canPlug-in |
32 | OR gate logic circuit |
The objects, features and advantages of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the meaning of "and/or" appearing throughout includes three juxtapositions, exemplified by "A and/or B" including either A or B or both A and B. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The invention provides a computer mainboard which can be used for various computers, such as servers, to control the power-on and reset time sequence of an external device 50 connected with the computer, so that the power-on and reset time sequence of the external device 50 is correct, and meanwhile, the computer mainboard can work normally when the external device 50 is not in place.
Referring to fig. 1, in an embodiment, the computer motherboard includes:
a circuit board 10;
the pluggable equipment interface 40 is arranged on the circuit board 10 and is electrically connected with the external equipment 50 in a pluggable way;
the external device detection circuit 30 is arranged on the circuit board 10 and is electrically connected with the pluggable device interface 40, and a first detection end and a second detection end of the external device detection circuit 30 are respectively and electrically connected with the pluggable device interface 40; when the external device 50 is detected to be in place, the external device detection circuit 30 detects whether the external device 50 is powered on and outputs an external device state OK signal when the external device 50 is detected to be powered on and finished;
the input end of the processor 20 is connected with the output end of the external equipment detection circuit, and the output end of the processor 20 is connected with the pluggable equipment interface 40; the processor 20 is configured to output a reset signal to the external device 50 through the pluggable device interface 40 when receiving the external device status OK signal, so as to control the external device 50 to reset.
It should be noted that, the external device state OK signal described herein indicates that the external device is ready to perform a reset operation, and the reset operation indicates that the device outputs a signal to enable the device to release the reset state and enter a normal operating mode.
Wherein the circuit board 10 may be a PCB circuit board; the external device 50 may be a PCIE (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, high speed serial computer expansion bus standard) device or other external device 50; the pluggable device interface 40 may be a connection interface such as a slot or a custom backplane connector.
The external device detection circuit 30 may be implemented by a digital logic circuit or an analog logic circuit. The logic of the logic circuit may be to output an external device status OK signal when the external device 50 is on bit and power-up is complete. The specific logic selection of the logic circuit may be determined according to the corresponding levels of the on-position indication signal and the power-on completion indication signal of the external device, for example, when the on-position indication signal is a low level, the external device 50 is indicated to be on position, and when the power-on completion indication signal is a high level, the external device 50 is indicated to be powered on completely, and the external device detection circuit 30 may be implemented by an or gate logic circuit. When the levels of the bit indication signal and the power-on completion indication signal are in other situations, the external device detection circuit 30 may also be other logic circuits.
It is understood that each external device 50 has its own requirement of timing relationship between power-on and power-off, for example, for a PCIE device, the power-off signal is generally required to arrive after 100ms after the power-on of the PCIE device is completed. The timing relationship between power-up and power-down may not satisfy the timing relationship, which may cause the external device 50 to be initialized abnormally and not work normally.
However, because the time required for completing the power-on of different external devices 50 is different, the processor 20 cannot determine whether the external device 50 is completely powered on, and thus cannot determine when to send out the reset signal, and the traditional method delays (software or hardware delays) the reset signal to send out, for example, the processor 20 takes the time required for completing the power-on of the functional module with the longest time required for completing the power-on among all functional modules on the computer motherboard and the external devices 50 as the delay time, and after the delay time is reached, the processor 20 defaults that all devices on the computer motherboard and the external devices 50 are completely powered on, so as to output the reset signal to all devices on the computer motherboard and the external devices 50; however, after the external device 50 is replaced, the delay time needs to be readjusted, and if the delay time is not adjusted, the delay time is less than the power-on completion time required by the external device 50, which results in the reset signal being output to the external device 50 in advance, and the power-on and reset timing of the external device 50 does not meet the requirements of the external device 50, thereby causing the external device 50 to be initialized abnormally. Therefore, in order to make the power-on and power-off timing sequence of the external device 50 normal and work normally, the delay time needs to be estimated again according to the external device when the external device 50 is replaced each time, it can be understood that the external device 50 is different from a fixed device on a computer motherboard, and in many application occasions, various external devices 50 need to be frequently replaced and plugged, and the external device 50 needs to be plugged and unplugged for many times.
Therefore, when the external device 50 is replaced each time, the processor 20 needs to estimate the delay time again according to the external device 50, firstly, the external device 50 is various, the power-on completion time is different, the difficulty in estimating the delay time again is large, a large amount of workload can be brought to software and hardware design, secondly, the estimated delay time is smaller than the power-on completion time required by the external device 50, the reset signal is output to the external device 50 in advance, and the power-on and reset timing sequence of the external device 50 is abnormal, so that the external device 50 cannot work. Or in order to ensure that the power-on and power-off timing sequence of the external device 50 is normal, the delay time estimated by the processor 20 is much longer than the time required for completing the power-on of the device on the computer motherboard and the external device 50, which may cause the start speed of the system to be slow after the external device 50 is replaced, and greatly affect the working efficiency.
Meanwhile, it should be understood that, in practical applications, a connection detection circuit is arranged between the external device 50 and the pluggable device interface 40, specifically, a pull-up resistor may be arranged on the pluggable device interface 40, a first end of the pull-up resistor is connected with a power supply, a second end of the pull-up resistor is an in-place indication signal output end and can output an in-place indication signal, and a pull-down resistor having a resistance value far smaller than that of the pull-up resistor is arranged on the external device 50 or is directly grounded; therefore, before the external device 50 is connected to the pluggable device interface 40, the power source raises the level of the second end of the pull-up resistor, so that the second end of the pull-up resistor outputs a high level to indicate that the external device 50 is not in place, after the external device 50 is connected to the pluggable device interface 40, the pull-up resistor and the pull-down resistor form a voltage dividing circuit, the resistance value of the pull-down resistor is far smaller than that of the pull-up resistor, and therefore the second end of the pull-up resistor outputs a low level to indicate that the external device 50 is in place. Meanwhile, the external device 50 may have a plurality of power sources, and after the voltage of each power source reaches a stable state, the external device 50 may output a power-on completion indication signal indicating that the power source voltage reaches the stable state, and meanwhile, the plurality of power sources of the external device 50 are powered on in a certain order and reach the stable state, and when the last power source voltage of the external device 50 reaches the stable state, all the power sources of the external device 50 reach the stable state, so that the power-on completion indication signal output end of the last powered power source of the external device 50 may be used as the power-on completion indication signal output end of the external device 50.
In order to solve the above problems, the present invention provides an external device detection circuit 30 disposed between the processor 20 and the pluggable device interface 40, wherein a first detection end of the external device detection circuit 30 is connected to the pluggable device interface 40 and connected to the in-place indication signal output end through the pluggable device interface 40 to detect whether the external device 50 is in place, a second detection end of the external device detection circuit 30 is electrically connected to the pluggable device interface 40 and connected to the power-on completion indication signal output end of the external device 50 through the pluggable device interface 40 to detect whether the power-on of the external device 50 is completed, when detecting that the external device 50 is in place, the external device detection circuit 30 detects whether the power-on of the external device 50 is completed, and at this time, if detecting that the power-on of the external device 50 is completed, the external device detection circuit 30 outputs an external device status OK signal to the processor 20, therefore, the processor 20 can know the state OK of the external device 50, and when the power-on of other devices on the motherboard of the computer is completed, outputs the reset signal to the device on the motherboard of the computer, and outputs the reset signal to the external device 50 through the pluggable device interface 40 to control the external device 50 to reset.
In this embodiment, the external device detection circuit 30 outputs an external device status OK signal after detecting that the external device 50 is in place and the power-on is completed, so that the processor 20 can know that the external device 50 is in OK status, and when the power-on of other devices on the motherboard of the computer is completed, the processor outputs a reset signal and outputs the reset signal to the external device 50 through the pluggable device interface 40; therefore, there is a sequential logical relationship between the power-on completion and the reset of the external device 50, so that the problem of incorrect power-on and reset timing sequence of the external device 50 is solved, and the problem that the external device 50 cannot work normally due to incorrect power-on and reset timing sequence is avoided.
In addition, after the external device 50 is replaced each time, the external device detection circuit 30 detects the in-place situation of the external device 50 again, detects whether the external device 50 is powered on completely, and outputs an external device status OK signal when the external device 50 is detected to be in-place and the power on is completed, so that the processor 20 can know that the external device 50 is in-place and the power on is completed. The detection process of the in-place and power-on conditions of the external device 50 is completed by hardware, the processor 20 does not need to estimate the time required by the power-on completion of the external device 50, and the problem of delay time estimation does not exist, so that the problem that the delay time of the output reset signal needs to be estimated again after the external device 50 is replaced every time is solved, the software and hardware design time consumed by estimating the delay time is greatly reduced, and the method has great significance for occasions needing to replace the external device 50 frequently. Meanwhile, the processor 20 is not required to estimate the time required by the power-on completion of the external device 50, and the delay time estimation time is also avoided to be far longer than the actually required delay time, so that the system starting speed is reduced, the starting speed of the system after the external device 50 is replaced can be greatly improved, the waiting time is reduced, and the working efficiency is improved.
Further, when the external device detection circuit 30 detects that the external device 50 is in the on position and detects that the power-on of the external device 50 is not completed, it does not output an external device status OK signal,
the processor 20 needs to receive the external device status OK signal and output a reset signal when the device on the motherboard of the computer is powered on, so that the motherboard device and the external device are reset.
When the external device 50 is in place and the power-on is not completed, the external device detection circuit 30 does not output the external device state OK signal, and at this time, the processor 20 cannot output the reset signal because the external device state OK signal is not received, so that the main working different board system of the computer is always in the reset state, and the processor 20 can timely judge that the external device 50 is normal, so as to perform the next operation, for example, stop working and feed back a fault to the user for maintenance or replacement of the external device 50. The embodiment overcomes the defect that the fault of the external equipment cannot be found when the external equipment is used as a necessary component. The external device 50 is prevented from being in a reset state all the time and possibly damaged, and meanwhile, the normal work of other devices on the computer mainboard can be influenced.
Further, when the external device detection circuit 30 detects that the external device 50 is not in place, the external device state OK signal is output, and it can be understood that the external device is not expanded and added to the computer system at this time, but the computer motherboard itself still needs to be able to operate independently, so that the external device detection circuit 30 also outputs the external device state OK signal when the external device is not in place, so that the computer can operate normally without the external device.
In this embodiment, when the external device 50 is not in place (it may not be connected before the computer motherboard works, or it may be unplugged during the computer motherboard work), the external device 50 is not a necessary component of the computer motherboard, and therefore, when the external device is not in place, the external device detection circuit 30 may determine that the external device is not in place, which is the external device state OK, in order to enable the motherboard to work normally. Specifically, the external device detection circuit 30 detects that the external device 50 is not connected to the pluggable device interface 40, and the external device detection circuit 30 outputs an external device status OK signal no matter whether the external device 50 is powered on or not; therefore, after receiving the external device status OK signal, the processor 20 may determine whether to output the reset signal according to the situation when the power-on of the device on the motherboard of the computer is completed, and output the reset signal when the power-on of the device on the motherboard of the computer is completed, so that the motherboard of the computer does not affect the normal operation of the motherboard of the computer because the external device is not in place.
That is, in this embodiment, when the external device 50 is not in place, the computer motherboard can normally power on and power off without being affected by the external device 50; this embodiment has realized not inserting external device 50 or plug external device 50 at computer motherboard during operation, also when external device 50 is not in place, computer motherboard also can normal work to when having solved external device 50 and not being in place, treater 20 can not receive external device state OK signal, leads to unable output reset signal, leads to the unable problem of normal work of computer motherboard.
Referring to fig. 2, in an embodiment, the external device detection circuit 30 includes an or gate logic circuit 32, a first input terminal of the or gate logic circuit 32 is a first detection terminal of the external device detection circuit 30, a second input terminal of the or gate logic circuit 32 is a second detection terminal of the external device detection circuit 30, and an output terminal of the or gate logic circuit 32 is connected to the processor 20.
Specifically, a first input and a second input of the or gate logic circuit 32 are connected to the pluggable device interface 40, and an output of the or gate logic circuit 32 is connected to the processor 20; the output of the processor 20 is connected to the pluggable device interface 40.
The pluggable device interface 40 has at least three terminals: a first input of or gate logic circuit 32, a second input, and an output of processor 20. The first input terminal and the second input terminal of the or gate logic circuit 32 and the output terminal of the processor 20 are respectively connected to the on-site indication signal output terminal of the external device, the power-on completion indication output terminal of the external device and the reset signal receiving terminal of the external device 50 through the pluggable device interface 40 in a one-to-one correspondence manner. The or gate logic circuit 32 may be implemented by an or gate chip or an analog circuit, and this embodiment may be implemented by using a two-terminal or gate integrated chip.
In practical application, the computer motherboard further includes a power-on completion detection terminal 60 of the computer motherboard, and the power-on completion detection terminal 60 of the computer motherboard is connected to another input terminal of the processor 20, so that the processor 20 detects whether the power-on of the device on the computer motherboard is completed.
Specifically, the power-on completion detecting terminal 60 of the computer motherboard may output a power-on completion indication signal of the computer motherboard when the power-on of the device on the computer motherboard is completed, so as to indicate that the power-on of the device on the computer motherboard is completed; outputting a power-on abnormity indication signal of the computer mainboard when equipment on the computer mainboard is abnormal in power-on so as to represent that the equipment on the computer mainboard is abnormal in power-on; in this embodiment, the power-on completion indication signal of the computer motherboard is a high level signal, and the power-on abnormal indication signal of the computer motherboard is a low level signal for interpretation, but in practical application, adjustment may be performed according to actual conditions, for example, if the power-on completion indication signal of the computer motherboard is a low level signal and the power-on abnormal indication signal of the computer motherboard is a high level signal, an inverter may be added to invert the power-on completion indication signal, or adjust logic of a logic circuit.
The in-place indication signal output end of the external device can output a low level signal when the external device 50 is in place, and output a high level signal when the external device 50 is not in place; the external device power-on completion indication signal output end may output a high level signal when the external device 50 is powered on, and output a low level signal when the external device 50 is not powered on. The high level signal output by the external device detection circuit 30 is an external device state OK signal; when receiving the high level signal output by the external device detection circuit 30, the processor 20 may output the reset signal when the power-on completion detection terminal 60 of the computer motherboard also outputs the high level signal, and when not receiving the state OK signal of the external device 50, the processor 20 does not output the reset signal.
The external device detection circuit 30 in this embodiment can achieve the following functions:
first, when the external device 50 is not in place, the first input terminal of the or gate logic circuit 32 detects a high level signal, and at this time, no matter what level signal is input to the second input terminal of the or gate logic circuit 32, the or gate logic circuit 32 outputs the high level signal to the processor 20, and at this time, the processor 20 may output an un-reset signal to other devices on the computer motherboard when receiving the high level signal output by the power-on completion detection terminal 60 of the computer motherboard, so that the computer motherboard normally operates. Therefore, when the external device 50 is not in place, the computer mainboard can work normally, and therefore the situation that the computer mainboard is powered off due to plugging and unplugging of the external device 50 cannot be caused in the working process of the computer mainboard on the premise of time-space control is guaranteed.
Secondly, when the external device 50 is on site and the power-on is completed, the first input end of the or gate logic circuit 32 detects a low level signal, the second input end of the or gate logic circuit 32 detects a high level signal, the or gate logic circuit 32 outputs a high level signal to the processor 20, at this time, the processor 20 can output a reset signal to the device on the computer motherboard when receiving the high level signal output by the power-on completion detection end 60 of the computer motherboard, and output the reset signal to the external device 50 through the pluggable device interface 40, so that the device on the computer motherboard and the external device 50 both work normally. The sequential logic relationship between the completion of power-on and the reception of the reset signal of the equipment on the computer mainboard and the external equipment 50 is realized, so that the power-on and reset time sequences of the equipment on the computer mainboard and the external equipment 50 are correct and work normally.
Thirdly, when the external device 50 is on-position and the power-on is not completed, the first input end and the second input end of the or gate logic circuit 32 both detect a low level signal, so that the or gate logic circuit 32 does not output a high level signal (does not output an external device state OK signal), so that the processor 20 does not receive the external device state OK signal at this time and does not output a reset signal, and then the device on the computer motherboard and the external device 50 are always in a reset state, and at this time, the processor 20 can judge that the external device 50 works abnormally by this, and can find that the external device 50 works abnormally in time. Thus, the processor 20 can detect the malfunction of the external device 50 in time to perform the next operation, such as stopping the operation and feeding back the malfunction to the user for repairing or replacing the external device 50.
In the technical scheme of the embodiment, the simple or gate logic circuit 32 is used to realize the sequential control of power-on and power-off reset of the external device 50; the power-on completion and the reset of the external equipment 50 have a logical relationship on a circuit, and the power-on and reset time sequence of the external equipment 50 is ensured to be correct, so that the system works more stably, and meanwhile, the external equipment detection circuit 30 has few devices, so that the circuit structure is simple, the circuit layout is simple, the debugging workload is less, and the circuit works stably. In addition, the or gate logic circuit 32 is implemented by a hardware circuit or a chip, and when the external device 50 is abnormal or the power-on is completed, the or gate logic circuit 32 can quickly feed back a signal to the processor 20, so that the processor 20 does not need to estimate the power-on completion time of the external device 50, and the problems of workload caused by estimating the power-on completion time of the external device 50, abnormal power-on and reset timing sequence caused by delay time estimation errors, slow system start and the like are greatly reduced. Meanwhile, the or gate logic circuit 32 of the embodiment also reports an error when the external device 50 is in place and power-on is abnormal, and outputs an external device state OK signal when the external device 50 is not in place, so that the computer motherboard can normally work.
Referring to fig. 3, further, the external device detection circuit 30 further includes an and logic circuit 31; a first input end of the and logic circuit 31 is connected with an output end of the or logic circuit 32, and a second input end of the and logic circuit 31 is connected with a power-on completion detection end 60 of the computer motherboard; the output end of the and logic circuit 31 is the output end of the external device detection circuit 30, and is connected to the processor 20.
In this embodiment, the external device detection circuit 30 includes an and gate logic circuit 31 and an or gate logic circuit 32, and the computer motherboard further includes a power-on completion detection terminal 60 of the computer motherboard.
In this embodiment, the first input end and the second input end of the or gate logic circuit 32 are connected to the pluggable device interface 40, the output end of the or gate logic circuit 32 is connected to the first input end of the and gate logic circuit 31, the second input end of the and gate logic circuit 31 is connected to the power-on completion detection end 60 of the computer motherboard, and the output end of the and gate logic circuit 31 is connected to the processor 20; the output end of the processor 20 is connected with the pluggable device interface 40; the pluggable device interface 40 has at least three ends: a first input of or gate logic circuit 32, a second input, and an output of processor 20. The first input terminal and the second input terminal of the or gate logic circuit 32 and the output terminal of the processor 20 are respectively connected to the on-site indication signal output terminal of the external device, the power-on completion indication output terminal of the external device and the reset signal receiving terminal of the external device 50 through the pluggable device interface 40 in a one-to-one correspondence manner.
In this embodiment, the in-place indication signal output end of the external device may output a low level signal when the external device 50 is in place, and output a high level signal when the external device 50 is not in place; the external device power-on completion indication signal output end may output a high level signal when the external device 50 is powered on, and output a low level signal when the external device 50 is not powered on. The power-on completion detection terminal 60 of the computer motherboard can output a high level signal when the power-on of the device on the computer motherboard is completed, and the power-on completion detection terminal 60 of the computer motherboard can output a low level signal when the power-on of the device on the computer motherboard is abnormal.
It should be noted that the high level signal output by the or gate logic circuit 32 is an external device status OK signal; the high level signal output by the power-on completion detection terminal 60 of the computer motherboard indicates that the power-on of the device on the computer motherboard is completed. When the state of the external device 50 is OK and the power-on of the device on the motherboard of the computer is completed, the high level signal output by the and logic circuit 31 represents that the power-on of the motherboard of the computer is normal and the state of the external device 50 is OK, that is, the high level signal output by the and logic circuit 31 is the system state OK signal.
When the processor 20 receives the high level output by the external device detection circuit 30, it can know that the power-on of the device on the motherboard of the computer is completed and the state of the external device 50 is OK, and the processor 20 outputs a reset signal to the device on the motherboard of the computer and outputs the reset signal to the external device 50 through the pluggable device interface 40; when the processor 20 does not receive the high level signal, it does not output the reset signal.
The external device detection circuit 30 in this embodiment can achieve the following functions:
firstly, when the devices on the computer motherboard are powered on abnormally, the power-on completion detection end 60 of the computer motherboard outputs a low level signal to the second input end of the and logic circuit 31, at this time, no matter what level signal is output by the or logic circuit 32, the and logic circuit 31 does not output a high level signal, so that the computer motherboard cannot output a reset signal, and each device on the computer motherboard is always in a reset state, and the processor 20 timely judges the power-on abnormality of the computer motherboard according to the above, so as to perform the next operation, for example, stop working and feed back a fault to a user for maintenance or restart.
Secondly, when the device on the computer motherboard is powered on, the power-on completion detection end 60 of the computer motherboard outputs a high level signal to the second input end of the and logic circuit 31, at this time, the output level of the output end of the and logic circuit 31 depends on the output level of the or logic circuit 32, when the or logic circuit 32 outputs a high level, the state OK of the external device 50 is represented, and then the and logic circuit 31 outputs a high level, which represents the state OK of the system; when the or gate logic circuit 32 outputs a low level, it indicates that the state of the external device 50 is not OK, and the and gate logic circuit 31 outputs a low level, that is, does not output a system state OK signal.
When the equipment on the computer mainboard is powered on, the following effects are achieved:
firstly, when the external device 50 is not in place, the first input terminal of the or gate logic circuit 32 detects a high level signal, and at this time, no matter what level signal is input to the second input terminal of the or gate logic circuit 32, the or gate logic circuit 32 outputs the high level signal to the first input terminal of the and gate logic circuit; and when the computer motherboard device is powered on, the and gate logic circuit outputs a high level signal to the processor 20, and the processor 20 outputs a reset signal to other devices on the computer motherboard, so that the computer motherboard normally works. Therefore, when the external device 50 is not in place, the computer mainboard can also work normally, and on the premise of ensuring space-time control, the computer mainboard does not power down when the external device 50 is plugged or not connected to the external device during working.
Secondly, when the external device 50 is on-position and the power-on is completed, the first input end of the or gate logic circuit 32 detects a low level signal, the second input end of the or gate logic circuit 32 detects a high level signal, and the or gate logic circuit 32 outputs the high level signal to the first input end of the and gate logic circuit; and at this time, the computer motherboard device is powered on, so that the and gate logic circuit 31 outputs a high level signal to the processor 20, at this time, the processor 20 outputs a reset signal to other devices on the computer motherboard, and outputs the reset signal to the external device 50 through the pluggable device interface 40, so that the computer motherboard and the external device 50 both work normally. The sequential relationship between the completion of power-on and the reception of the reset signal of the equipment on the computer mainboard and the external equipment 50 is realized, so that the power-on and reset time sequences of the equipment on the computer mainboard and the external equipment 50 are correct and work normally.
Thirdly, when the external device 50 is on-bit and the power-on is not completed, both the first input end and the second input end of the or gate logic circuit 32 detect a low level signal, so that the or gate logic circuit 32 outputs the low level signal to the first input end of the and gate logic circuit, and at this time, the and gate logic circuit 31 outputs the low level signal; therefore, the computer motherboard cannot output a reset signal, so that each device on the computer motherboard is always in a reset state, and the processor 20 determines that the computer motherboard is powered on abnormally, so as to perform the next operation, such as stopping working and feeding back a fault to a user for maintenance or restarting.
In the technical scheme of this embodiment, a simple and gate logic circuit 31 is combined with an or gate logic circuit 32, so that when a device on a computer motherboard is powered on abnormally, or when an external device 50 is in place and powered on abnormally, the processor 20 does not output a reset signal, so that the computer motherboard system is in a reset state, and the processor 20 timely determines that the computer motherboard is powered on or the external device is abnormal, so as to perform the next operation.
When the external equipment is not in place and the equipment on the computer mainboard is powered on normally, the processor can normally output an unset signal to the equipment on the computer mainboard, so that the computer mainboard can work normally when the external equipment is not available.
When the device on the motherboard of the computer is powered on normally, and the external device is in place and powered on completely, the processor 20 outputs a reset signal, so that there is a logical relationship between the power-on completion and the reset of the external device 50 and the device on the motherboard of the computer, and the power-on and reset timing sequence of the external device 50 and the device on the motherboard of the computer is ensured to be correct, thereby the system works more stably. The power-on completion time of the external device 50 does not need to be estimated, so that the workload brought by the time required by estimating the power-on completion of the external device 50 is greatly reduced, and the problems of abnormal power-on and reset time sequences, slow system starting and the like caused by delay time estimation errors are solved.
In one embodiment, the pluggable device interface 40 is a slot; and/or the pluggable device interface 40 is a backplane custom connector.
When the pluggable device interface 40 is a slot, the external device 50 has a plug-in card, and the external device 50 is plugged into the computer motherboard by the plug-in card, wherein the external device 50 may have a PIN for outputting a power-on completion signal PIN.
The custom connector may be a PCIE connector or other custom connector. The external device 50 may be a carrier board, the carrier board has an interface matching with the custom connector and a power-on completion detection circuit, and the interface on the carrier board may be directly plugged into the backplane custom connector or may be connected to the backplane custom connector in a pluggable manner through a communication transmission cable.
Referring to fig. 4, the present invention further provides a timing control method for an external device 50, which is applied to the computer motherboard, where the computer motherboard includes a circuit board 10 and the pluggable device interface 40 disposed on the circuit board 10; the external device 50 timing control method comprises the following steps:
step S100, when the pluggable device interface 40 detects that the external device 50 is in place and when the external device 50 is detected to be powered on completely, outputting an external device state OK signal;
step S200, when receiving the external device status OK signal, outputting a release signal to the external device 50 through the pluggable device interface 40, so as to control the external device 50 to enter a normal operating state.
In this embodiment, the computer motherboard may be provided with an external device detection circuit 30, a processor 20, a pluggable device interface 40, and a power-on completion detection end 60 of the computer motherboard; the external device detection circuit 30 may include an and gate logic circuit 31 and an or gate logic circuit 32; the output end of the and logic circuit 31 is connected with the processor 20; a second input end of the and logic circuit 31 is connected with a power-on completion detection end 60 of the computer mainboard; the first input end of the AND gate logic circuit is connected with the output end of the OR gate logic circuit, the first input end of the OR gate logic circuit is connected with the in-place indication signal output end of the external device through the pluggable device interface 40, and the second input end of the OR gate logic circuit is connected with the power-on completion indication signal output end of the external device through the pluggable device interface 40.
The pluggable device interface 40 may be provided with a connection detection circuit, an output end of the connection detection circuit is an in-place indication signal output end of the external device, and an indication signal output end of the external device 50 that is powered on is an indication signal output end of the external device 50 that is powered on.
The external device detection circuit 30 detects that the external device 50 is in place and the external device 50 is powered on and completed through the pluggable device interface 40, and simultaneously outputs a system state OK signal to the processor 20 when detecting that the device on the computer motherboard is powered on and completed, and the processor 20 outputs a reset-off signal to the device on the computer motherboard when receiving the system state OK signal, and outputs the reset-off signal to the external device 50 through the pluggable device interface 40 so as to control the device on the computer motherboard and the external device 50 to enter a normal working state.
When the external device detection circuit 30 detects that the external device 50 is in place through the pluggable device interface 40 and the power on of the external device 50 is not completed, the system state OK signal is not output to the processor 20, and when the processor 20 cannot receive the external device state OK signal, the reset signal is not output to the device on the computer motherboard and the external device 50, so that the device on the computer motherboard and the external device are always in the reset state, and the processor 20 can judge that the state of the external device 50 is abnormal.
When the external device detection circuit 30 detects that the external device 50 is not in place through the pluggable device interface 40 and detects that the power-on of the device on the computer motherboard is completed, it outputs a system status OK signal to the processor 20, and when the processor 20 receives the system status OK signal, it outputs a reset signal to the device on the computer motherboard, so that the computer motherboard can normally operate without the external device 50.
The invention also provides a computer host which comprises the computer mainboard. The specific structure of the computer motherboard refers to the above embodiments, and since the host computer adopts all the technical solutions of all the above embodiments, at least all the beneficial effects brought by the technical solutions of the above embodiments are achieved, and no further description is given here.
The invention further provides a computer, which comprises an external device 50, the computer motherboard or the computer host. The specific structure of the computer motherboard or the computer host refers to the above embodiments, and since the computer adopts all the technical solutions of all the embodiments, at least all the beneficial effects brought by the technical solutions of the embodiments are achieved, and no further description is given here.
In one embodiment, the external device 50 has a plug-in card, such as a gold finger, and the external device 50 is pluggable to the computer motherboard via the plug-in card;
or, external device 50 has connecting terminal, connecting terminal through electrically conductive pluggable grafting extremely on the computer motherboard, specifically, external device 50 can include support plate, functional module (for example PCIE equipment) and go up the electricity and accomplish detection circuitry, and wherein functional module can be fixed connection on the support plate, or has the slot on the support plate, and functional module is the integrated circuit board design, pluggable and be connected with the support plate to compatible board card formula external device 50. The external device 50 is connected to the computer motherboard through the connection terminal and the conductive member, and the power-on completion detection circuit is connected to the computer motherboard in a pluggable manner.
The above description is only an alternative embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (9)
1. A computer motherboard, comprising:
a circuit board;
the pluggable equipment interface is arranged on the circuit board and is electrically connected with the external equipment in a pluggable way;
the external equipment detection circuit is arranged on the circuit board and is electrically connected with the pluggable equipment interface, and a first detection end and a second detection end of the external equipment detection circuit are respectively and electrically connected with the pluggable equipment interface; when the external equipment is detected to be in place, the external equipment detection circuit detects whether the external equipment is powered on and finished, and outputs an external equipment state OK signal when the external equipment is detected to be powered on and finished;
the input end of the processor is connected with the external equipment detection circuit, and the output end of the processor is connected with the pluggable equipment interface; and the processor is used for outputting a reset signal to the external equipment through the pluggable equipment interface when receiving the state OK signal of the external equipment so as to control the external equipment to reset.
2. The computer motherboard of claim 1 wherein the external device detection circuit outputs the external device status OK signal when detecting that the external device is not in place.
3. The computer motherboard of claim 1 wherein said peripheral device detection circuitry comprises:
the first input end of the OR gate logic circuit is the first detection end of the external equipment detection circuit, the second input end of the OR gate logic circuit is the second detection end of the external equipment detection circuit, and the output end of the OR gate logic circuit is connected with the processor.
4. The computer motherboard of claim 3 wherein said peripheral device detection circuitry further comprises:
the first input end of the AND gate logic circuit is connected with the output end of the OR gate logic circuit, and the second input end of the AND gate logic circuit is connected with the power-on completion detection end of the computer mainboard; and the output end of the AND gate logic circuit is connected with the processor.
5. The computer motherboard according to any of claims 1 to 4 wherein said pluggable device interface is a slot; and/or the pluggable equipment interface is a backboard custom connector.
6. An external device timing control method, applied to the computer motherboard of any one of claims 1 to 5, wherein the computer motherboard comprises a circuit board and the pluggable device interface arranged on the circuit board; the external equipment time sequence control method is characterized by comprising the following steps:
when the pluggable equipment interface detects that the external equipment is in place and the external equipment is detected to be powered on, outputting an external equipment state OK signal;
and when the state OK signal of the external equipment is received, outputting a reset signal to the external equipment through the pluggable equipment interface so as to control the external equipment to reset.
7. A computer host, characterized in that the computer host comprises a computer motherboard according to any one of claims 1 to 5.
8. A computer, comprising an external device and a computer motherboard according to any one of claims 1 to 5, or a computer host according to claim 7.
9. The computer of claim 8, wherein the external device has a plug-in card, and the external device is pluggable to the computer motherboard by the plug-in card;
or the external equipment is provided with a connecting terminal, and the connecting terminal can be plugged on the computer mainboard in a pluggable manner through the conductive piece.
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