CN112466943A - GaN HEMT based on p-type diamond-doped heat dissipation layer and preparation method - Google Patents

GaN HEMT based on p-type diamond-doped heat dissipation layer and preparation method Download PDF

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CN112466943A
CN112466943A CN202011384359.5A CN202011384359A CN112466943A CN 112466943 A CN112466943 A CN 112466943A CN 202011384359 A CN202011384359 A CN 202011384359A CN 112466943 A CN112466943 A CN 112466943A
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layer
drain electrode
heat dissipation
gan hemt
electrode
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马晓华
程可
武玫
朱青
张濛
侯斌
杨凌
郝跃
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Xidian University
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Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Abstract

The invention discloses a GaN HEMT based on a p-type diamond-doped heat dissipation layer and a preparation method thereof; this GaN HEMT includes the substrate that sets up from bottom to top, the buffer layer, the barrier layer, the dielectric layer and the top heat dissipation layer of GaN material, still includes: a source electrode, a drain electrode, and a gate electrode; wherein, in the horizontal direction, the gate electrode is positioned between the source electrode and the drain electrode, and the top heat dissipation layer is positioned between the gate electrode and the drain electrode and is in contact with the gate electrode; the source electrode, the drain electrode and the gate electrode respectively penetrate through the dielectric layer to be in contact with the barrier layer; the upper end of the gate electrode extends towards the drain electrode so as to cover part of the surface of the top heat dissipation layer; the top heat dissipation layer is a p-type doped diamond layer. The invention can improve the heat dissipation capability of the GaN HEMT in a microwave high-power scene.

Description

GaN HEMT based on p-type diamond-doped heat dissipation layer and preparation method
Technical Field
The invention belongs to the field of semiconductor devices, and particularly relates to a High Electron Mobility Transistor (HEMT) based on a p-type diamond-doped heat dissipation layer and a preparation method thereof.
Background
Gallium nitride is used as a representative material of third-generation semiconductors, and has a very wide application prospect. Due to the characteristics of large forbidden band width, high electron saturation velocity and the like of gallium nitride, the gallium nitride has unique advantages in high-frequency and high-power fields such as military affairs, aerospace, communication and the like. With the increasing integration of semiconductor devices, the accompanying phenomenon of high heat generation is unavoidable, and the self-heating effect accumulation of the devices can not only reduce the basic performances of saturation current, transconductance and the like of the devices, but also can cause the failure of the devices in more serious cases.
The thermal conductivity of GaN itself is only 130W/(m · K) (watt/meter · kelvin), and in the current GaN HEMT, commonly used substrates mainly include a SiC (silicon carbide) substrate, a Si (silicon) substrate, and a sapphire substrate, and the like. Even if a SiC substrate with high thermal conductivity is adopted, the requirement of the GaN effect tube on heat dissipation in a future microwave high-power scene cannot be met.
Disclosure of Invention
In order to further improve the heat dissipation capability of the GaN HEMT in a microwave high-power scene, the invention provides a GaN HEMT based on a p-type diamond-doped heat dissipation layer and a preparation method thereof.
The technical problem to be solved by the invention is realized by the following technical scheme:
in a first aspect, the invention provides a p-type diamond-doped heat dissipation layer-based GaN HEMT, comprising a substrate, a GaN buffer layer, a barrier layer, a dielectric layer and a top heat dissipation layer arranged from bottom to top, and further comprising: a source electrode, a drain electrode, and a gate electrode; wherein the content of the first and second substances,
in the horizontal direction, the gate electrode is positioned between the source electrode and the drain electrode, and the top heat dissipation layer is positioned between the gate electrode and the drain electrode and is in contact with the gate electrode;
the source electrode, the drain electrode and the gate electrode respectively penetrate through the dielectric layer to be in contact with the barrier layer;
the upper end of the gate electrode extends towards the drain electrode so as to cover part of the surface of the top heat dissipation layer; the top heat dissipation layer is a p-type doped diamond layer.
Preferably, the p-type doped diamond layer is a boron doped diamond layer.
Preferably, the thickness of the p-type doped diamond layer is 0.5 to 1 μm.
Preferably, the length of the p-type doped diamond layer is greater than or equal to 50% of the horizontal spacing between the gate electrode and the drain electrode, and the p-type doped diamond layer is not in contact with the drain electrode.
Preferably, the dielectric layer is a SiN layer; the thickness of the SiN layer is 10 nm-60 nm.
Preferably, the barrier layer is made of AlGaN (aluminum gallium nitride).
Preferably, the source electrode and the drain electrode are both of a four-layer metal stack structure composed of titanium, aluminum, nickel and gold from bottom to top.
Preferably, the gate electrode is a double-layer metal stack structure composed of nickel and gold from bottom to top.
In a second aspect, the invention provides a method for preparing a GaN HEMT based on a p-type diamond-doped heat dissipation layer, comprising the following steps:
step S1: obtaining an epitaxial substrate; the epitaxial substrate comprises a substrate, a buffer layer and a barrier layer which are arranged from bottom to top; the buffer layer is made of GaN;
step S2: growing a dielectric layer on the barrier layer by utilizing a PECVD (Plasma Enhanced Chemical Vapor Deposition) process;
step S3: growing a top heat dissipation layer on the dielectric layer by an MPCVD (Microwave Plasma Chemical Vapor Deposition) process; the top heat dissipation layer is a p-type doped diamond layer;
step S4: carrying out graphical etching on the p-type doped diamond layer based on a metal hard mask to expose the dielectric layer in a partial area;
step S5: preparing a device electric isolation region of the GaN HEMT;
step S6: etching the dielectric layer of the partial area to enable the barrier layer to expose a gate groove area required for preparing a gate electrode, a source electrode area required for preparing a source electrode and a drain electrode area required for preparing a drain electrode; in the horizontal direction, the gate groove region is positioned between the source electrode region and the drain electrode region, and the p-type doped diamond layer after the patterned etching is positioned between the gate groove region and the drain electrode region and is adjacent to the gate groove region;
step S7: preparing a source electrode and a drain electrode on the source electrode area and the drain electrode area by sequentially utilizing a photoetching process and a metal evaporation deposition process;
step S8: and sequentially utilizing a photoetching process and a metal evaporation and deposition process to prepare a gate electrode based on the gate groove region.
Preferably, the p-type doped diamond layer is a boron doped diamond layer of 0.5 μm to 1 μm thickness.
In the GaN HEMT based on the p-type doped diamond heat dissipation layer, on one hand, the p-type doped diamond layer is arranged on the top of the GaN HEMT, and the effective heat dissipation is realized by utilizing the high heat conductivity of the diamond; on the other hand, the p-type doped diamond interacts with the conductive channel 2DEG (two-dimensional electron gas) of the GaN HEMT, so that the electric field peak value at the pin of the gate electrode can be reduced, the electric field distribution in the channel is more uniform, and the heat generation of the GaN HEMT is modulated. Based on the mutual synergistic effect of the two aspects, the GaN HEMT based on the p-type doped diamond heat dissipation layer can effectively improve the heat dissipation capability of the GaN HEMT in a microwave high-power scene.
The present invention will be described in further detail with reference to the accompanying drawings.
Drawings
FIG. 1 is a schematic structural diagram of a GaN HEMT based on a p-type doped diamond heat dissipation layer according to an embodiment of the invention;
FIG. 2 is a top view of FIG. 1;
FIG. 3 is a schematic structural diagram of another GaN HEMT based on a p-type doped diamond heat dissipation layer according to an embodiment of the invention;
FIG. 4 is a flowchart of a method for fabricating a GaN HEMT based on a p-type doped diamond heat dissipation layer according to an embodiment of the invention;
fig. 5 and 6 together form a schematic diagram of a complete process for fabricating a GaN HEMT in an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
In order to improve the heat dissipation capability of the GaN HEMT in a microwave high-power scene, the embodiment of the invention provides the GaN HEMT based on the p-type doped diamond heat dissipation layer. Fig. 1 exemplarily shows a front view of the GaN HEMT, and fig. 2 exemplarily shows a top view of the GaN HEMT; referring to fig. 1 and 2, the GaN HEMT includes a substrate, a buffer layer, a barrier layer, a dielectric layer, and a top heat dissipation layer arranged from bottom to top, the top heat dissipation layer is a p-type doped diamond layer, and the buffer layer is made of GaN; the GaN HEMT further includes: the source electrode, the drain electrode, and the gate electrode are denoted by symbols S, D and G, respectively.
In the horizontal direction, the gate electrode is positioned between the source electrode and the drain electrode, and the top heat dissipation layer is positioned between the gate electrode and the drain electrode and is in contact with the gate electrode; the source electrode, the drain electrode and the gate electrode respectively penetrate through the dielectric layer to be in contact with the barrier layer; the upper end of the gate electrode extends towards the drain electrode to cover part of the surface of the top heat dissipation layer; the top heat dissipation layer is a p-type doped diamond layer.
When the GaN HEMT operates under high voltage, the GaN HEMT needs to bear extremely high drain voltage, and the positive center of the depletion region generates electric field lines pointing from the positive center to the gate electrode with low potential, so that an electric field line concentration effect is generated on the gate electrode; therefore, the electric field lines at the pin channel of the gate electrode close to one side of the drain electrode are distributed more densely, the electric field peak value is formed at the edge of the gate electrode, and the heat generation of current is more concentrated at the electric field peak value; that is, the amount of heat generated at the pin of the gate electrode of the GaN HEMT, which is biased toward the drain electrode side, is large, here closer to the upper surface of the GaN HEMT.
In view of this, the GaN HEMT based on the p-type doped diamond heat dissipation layer provided in the embodiment of the present invention has a p-type doped diamond layer on the top thereof, so that effective heat dissipation is achieved by using the high thermal conductivity of diamond; on the other hand, the embodiment of the invention can reduce the electric field peak value at the pin of the gate electrode through the interaction of the p-type doped diamond and the conductive channel 2DEG of the GaN HEMT, so that the electric field distribution in the channel is more uniform, namely the modulation of the heat generation of the GaN HEMT is realized. Based on the mutual synergistic effect of the two aspects, the GaN HEMT based on the p-type doped diamond heat dissipation layer provided by the embodiment of the invention can effectively improve the heat dissipation capability of the GaN HEMT in a microwave high-power scene.
Preferably, in an embodiment of the present invention, the p-type doped diamond layer may be a boron doped diamond layer.
Preferably, the thickness of the p-type doped diamond layer may be 0.5 μm to 1 μm. For example, in a preferred embodiment, the thickness of the p-type doped diamond layer is preferably 1 μm. It should be noted that the p-type doped diamond layer with a thickness of 1 μm is a preferred thickness combining the heat dissipation effect and the manufacturing process.
Preferably, the first and second electrodes are formed of a metal,
the length of the p-type doped diamond layer is greater than or equal to 50% of the horizontal spacing between the gate electrode and the drain electrode, and the p-type doped diamond layer is not in contact with the drain electrode.
Preferably, the dielectric layer may be a SiN (silicon nitride) layer having a thickness of 10nm to 60 nm. Alternatively, the dielectric layer may be Al2O3(alumina) layer, the thickness can be referred to the thickness of the SiN layer.
It can be understood that if the dielectric layer is too thick, the heat dissipation effect of the top heat dissipation layer may be affected, so that the thickness of the dielectric layer is determined to be preferably 10nm to 60nm through practical verification.
Preferably, in the GaN HEMT based on the top heat dissipation layer provided in the embodiment of the present invention, the buffer layer is made of AlGaN, but the present invention is not limited thereto.
Preferably, the source electrode and the drain electrode may each have a four-layer metal stack structure composed of ti, al, ni, and au from bottom to top, but are not limited thereto.
Preferably, the gate electrode may be a double-layered metal stack structure composed of nickel and gold from bottom to top. Alternatively, the gate electrode may have a three-layer metal stack structure composed of nickel, gold, and nickel from the bottom to the top.
In addition, in an alternative embodiment, as shown in fig. 3, the GaN HEMT provided in the embodiment of the present invention may further have a device electrical isolation region; the device electrical isolation region is used for electrically isolating devices. Particularly, in practice, when a plurality of GaN HEMTs are prepared simultaneously, the device electric isolation region can effectively avoid the mutual influence of the active regions of the adjacent GaN HEMTs. In this embodiment, the preparation of the device electrical isolation region may be achieved by etching the dielectric layer, the barrier layer, and a portion of the buffer layer, and a detailed preparation process of the device electrical isolation region belongs to the prior art, and is not described in detail in the embodiments of the present invention.
The above completes the description of the GaN HEMT based on the p-type doped diamond heat dissipation layer.
The embodiment of the invention also provides a preparation method of the GaN HEMT, which corresponds to the GaN HEMT based on the p-type doped diamond heat dissipation layer provided by the embodiment of the invention. As shown in fig. 4, the method may include the steps of:
step S1: obtaining an epitaxial substrate; the epitaxial substrate comprises a substrate, a buffer layer and a barrier layer which are arranged from bottom to top; the buffer layer is made of GaN.
The substrate may be a silicon substrate, a sapphire substrate, or a SiC substrate, among others. The material of the barrier layer is preferably AlGaN, but it is not limited thereto.
Step S2: and growing a dielectric layer on the barrier layer by utilizing a PECVD process.
Specifically, the step S2 may include the following sub-steps:
step 2-a: and carrying out ultrasonic cleaning on the epitaxial substrate.
For example, the epitaxial substrate may be subjected to ultrasonic cleaning for 3 minutes, and the ultrasonic intensity may be 3.0W/cm2(watts/square centimeter).
Step 2-b: and (4) putting the cleaned epitaxial substrate into stripping liquid for water bath heating.
Illustratively, the cleaned epitaxial substrate may be placed in a water bath heated at a temperature of about 60 ℃ for 5 minutes in a stripping solution.
Step 2-c: and sequentially putting the further cleaned epitaxial substrate into an acetone solution and an ethanol solution for ultrasonic cleaning.
For example, the ultrasonic cleaning time may be 3 minutes, and the ultrasonic intensity may be 3.0W/cm2。
Step 2-d: the epitaxial substrate cleaned in step S2c was rinsed with ultrapure water and blown dry with nitrogen.
Step 2-e: and growing a dielectric layer on the barrier layer of the epitaxial substrate by utilizing a PECVD process.
Wherein the dielectric layer can be SiN layer or Al2O3Layers, etc., without limitation. In addition, the thickness of the dielectric layer may be 10nm to 60 nm.
For example, when a SiN layer with a thickness of 20nm needs to be grown, a specific PECVD process may include: by NH3(Ammonia gas) and SiH4(silane) as a reaction gas, temperature of epitaxial substrateThe temperature is 250 deg.C, the pressure in the reaction chamber is 600mTorr (millitorr), and the RF power is 22W.
Step S3: growing a top heat dissipation layer on the dielectric layer by an MPCVD process; the top heat dissipation layer is a p-type doped diamond layer.
For example, when a 1 μm thick p-doped diamond heat sink layer is grown on a SiN dielectric layer using an MPCVD process, the gas uses 3% CH4(methane) as a carbon source and H2(hydrogen) dilution; by adding B (CH) to the gas3)3(trimethylborane) to control boron content to give a mixed gas, the B (CH)3)3Likewise using H2Diluting; the proportion of boron and carbon in the mixed gas is not less than 1000ppm (parts per million concentration), and the total flow rate of the gas is 400sccm (standard cubic center meter per minute) to 600 sccm; a pressure of 200mTorr (millitorr) and a deposition rate of 0.13 μm/h (micrometers per hour) to 0.2 μm/h; the temperature of the substrate is 800-1000 ℃; the substrate is an epitaxial substrate after a dielectric layer is grown; the microwave power is 1500W-3500W.
Step S4: and carrying out graphical etching on the p-type doped diamond layer based on the metal hard mask so as to expose partial area of the dielectric layer.
Specifically, the step S4 may further include the following sub-steps:
step 4-a: a hard mask pattern is lithographically patterned on the p-type doped diamond layer.
For example, a sample with a grown p-type doped diamond layer may be first baked at a temperature of 200 ℃ for 5 minutes; then, the sample is subjected to glue spreading and spin coating of stripping glue, and the thickness of the spin coating can be 0.35 mu m; the sample was further baked at a temperature of 200 ℃ for 5 minutes. Then, coating photoresist and spin coating the photoresist on the coated stripper, wherein the spin coating thickness can be 0.77 mu m; the samples were baked at 90 ℃ for 1 minute. And then, putting the sample subjected to gluing and spinning into a photoetching machine for exposure, thereby forming a hard mask pattern on the upper surface of the p-type doped diamond layer. And finally, putting the exposed sample into a developing solution to remove the photoresist and the stripping glue in the hard mask pattern, and carrying out ultra-pure water washing and nitrogen blow drying on the photoresist and the stripping glue.
Step 4-b: the metal hard mask is evaporated.
The metal hard mask referred to herein may be a metal hard mask composed of two metals of Ti (titanium) and Ni (nickel). Using the metal hardmask for example, a sample having a hardmask photoresist pattern may be placed in a plasma stripper for a base film treatment of about 5 minutes, where the base film treatment removes primarily residual photoresist and stripper. Then, the sample is put into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10-6After Torr, metal Ti and metal Ni can be sequentially evaporated on the photoresist of the hard mask lithographic pattern. Then, stripping the sample after metal evaporation is finished so as to remove the metal, the photoresist and the stripping glue outside the hard mask pattern; finally, the sample was rinsed with ultra pure water and blown dry with nitrogen.
Step 4-c: etching the p-type doped diamond layer outside the hard mask photoetching pattern by utilizing an ICP (inductively Coupled Plasma) process.
For example, when the thickness of the p-type doped diamond layer is 1 μm, the etching conditions may include: bias power is about 100W, ICP source power is about 500W, helium flow is about 40sccm, oxygen flow is about 30sccm, operating pressure is about 10mTorr (millitorr), etch rate is about 180nm/min, and etch depth is about 1 μm.
It is understood that after the step 4-c is completed, a portion of the dielectric layer is exposed. The exposed partial area is mainly used for preparing three electrodes subsequently.
And 4-d: the metal hard mask is etched away.
Here, the metal hard mask may be chemically etched away with an etchant; specifically, the etching solution is a solution containing an oxidizing agent, a speed-increasing agent, a mask stabilizer, an etching surface-smoothing accelerator, and the like.
Step S5: and preparing a device electric isolation region of the GaN HEMT.
Related preparation processes of the device electrical isolation region belong to the existing mature technology, and the embodiment of the invention is not described in detail.
Step S6: etching the exposed dielectric layer in the partial area to enable the barrier layer to expose a gate groove area required for preparing a gate electrode, a source electrode area required for preparing a source electrode and a drain electrode area required for preparing a drain electrode; in the horizontal direction, the grid groove area is located between the source electrode area and the drain electrode area, and the p-type doped diamond layer after the patterned etching is located between the grid groove area and the drain electrode area and is adjacent to the grid groove area.
Specifically, the step S6 may include the following sub-steps:
step S6-a: and photoetching a source electrode pattern, a gate groove pattern and a drain electrode pattern on the exposed partial area of the dielectric layer.
For example, the sample may be first baked at 200 ℃ for 5 minutes; then, the dielectric layer was coated with a release coating having a thickness of about 0.35 μm and the sample was baked at 200 ℃ for 5 minutes. Next, the resist was applied and spun onto the strip to a thickness of about 0.77 μm, and the sample was baked at 90 ℃ for a further minute. And then, putting the sample subjected to glue coating and spin coating into a photoetching machine for exposure, thereby forming a source electrode pattern, a gate groove pattern and a drain electrode pattern on the dielectric layer. And finally, putting the exposed sample into a developing solution to remove the photoresist and the stripping glue in the source electrode pattern, the grid groove pattern and the drain electrode pattern, and then carrying out ultrapure water washing and nitrogen blow-drying on the sample.
Step S6-b: and etching the dielectric layer in the source electrode pattern, the gate groove pattern and the drain electrode pattern by utilizing an ICP (inductively coupled plasma) process.
Specifically, the etching depth is based on reaching the surface of the barrier layer, that is, the etching is stopped when the surface of the barrier layer is etched. Thus, the barrier layer can be exposed to a gate groove region required for preparing a gate electrode, a source electrode region required for preparing a source electrode, and a drain electrode region required for preparing a drain electrode.
For example, when the thickness of the dielectric layer is 20nm, the ICP etching conditions may include: the reaction gas being CF4(carbon tetrafluoride) and O2(oxygen), the pressure of the reaction chamber is l0mTorr, the radio frequency power of an upper electrode and the radio frequency power of a lower electrode of the ICP etching machine are 100W and l0W respectively, and the etching depth is based on reaching the surface of the barrier layer, namely the etching is stopped when the surface of the barrier layer is etched.
Step S7: and preparing a source electrode and a drain electrode on the source electrode area and the drain electrode area by sequentially utilizing a photoetching process and a metal evaporation deposition process.
Specifically, the step S7 may include the following sub-steps:
step 7-a: and respectively photoetching a source electrode pattern and a drain electrode pattern on the source electrode area and the drain electrode area.
For example, the sample may be first baked at 200 ℃ for 5 minutes; then, the dielectric layer was coated with a release coating having a thickness of about 0.35 μm and the sample was baked at 200 ℃ for 5 minutes. Next, the resist was applied and spun onto the strip to a thickness of about 0.77 μm, and the sample was baked at 90 ℃ for a further minute. And then, putting the sample subjected to glue coating and spin coating into a photoetching machine to expose the photoresist in the source electrode pattern and the drain electrode pattern, so as to form the source electrode pattern and the drain electrode pattern on the dielectric layer. And finally, putting the exposed sample into a developing solution to remove the photoresist and the stripping glue in the source electrode pattern and the drain electrode pattern, and then carrying out ultrapure water washing and nitrogen blow drying on the sample.
Step 7-b: the ohmic metal is evaporated.
The ohmic metal may be a metal stack structure composed of four layers of metals, i.e., titanium, aluminum, nickel, and gold, from bottom to top, but is not limited thereto.
For example, the sample with the source electrode pattern and the drain electrode pattern may be first put into a plasma stripper for a base film treatment, wherein the treatment time is about 5 minutes. Then, the sample is put into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10-6After Torr, sequentially evaporating four metals of titanium, aluminum, nickel and gold in the source electrode pattern and the drain electrode pattern; photoresist outside the source electrode pattern and the drain electrode patternThe metal also evaporates. Therefore, the ohmic metal, the photoresist and the stripper outside the source electrode pattern and the drain electrode pattern can be removed by subsequently stripping the sample in which the evaporation of the ohmic metal is completed. Finally, the sample was rinsed with ultra pure water and blown dry with nitrogen.
Step 7-c: and carrying out annealing treatment on the stripped sample.
Specifically, the stripped sample is placed into a rapid thermal annealing furnace for annealing, so that ohmic metal of the source electrode and the drain electrode sinks to the barrier layer, and ohmic contact between the ohmic metal and the heterojunction channel is formed. For example, the process conditions for annealing may include: annealing atmosphere is N2(Nitrogen), annealing temperature 830 ℃ and annealing time 30 seconds.
Step S8: and sequentially utilizing a photoetching process and a metal evaporation and deposition process to prepare a gate electrode based on the gate groove area.
Specifically, the step S8 may include the following sub-steps:
step S8-a: respectively photoetching a gate groove area on the barrier layer and part of the surface of the p-type doped diamond layer to obtain a gate electrode graph required by preparing a gate electrode;
for example, the sample may be first baked at 200 ℃ for 5 minutes; then, the sample was subjected to glue application and spin coating of a release film having a thickness of 0.35 μm, and then baked at 200 ℃ for 5 minutes. Subsequently, the sample was subjected to photoresist coating and spin coating with a spin coating thickness of 0.77 μm, and then baked at 90 ℃ for 1 minute. Then, putting the sample subjected to glue coating and spin coating into a photoetching machine, and exposing the photoresist on the surface of the barrier layer exposed in the gate groove region and part of the surface of the p-type doped diamond layer to form a gate electrode graph; finally, the exposed sample is put into a developing solution to remove the photoresist and the stripping glue in the gate electrode pattern, and the gate electrode pattern is subjected to ultra-pure water washing and nitrogen blow drying.
Step S8-b: and preparing a gate electrode on the gate electrode pattern by using a metal evaporation deposition process.
Specifically, a gate metal is evaporated on the surface of the sample. The gate metal can be a bimetallic stack structure composed of nickel and gold from bottom to top; alternatively, the gate metal may be a three-layer metal stack structure composed of nickel, gold, and nickel from top to bottom, or the like.
For example, a sample with a gate electrode pattern may be first placed in a plasma stripper for about 5 minutes of bottom film treatment. Then, the sample is put into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10-6After Torr, the upper gate metal can be evaporated on the photoresist inside and outside the gate electrode pattern. And then, stripping the sample after the gate metal evaporation is finished so as to remove the gate metal, the photoresist and the stripping glue outside the gate electrode pattern. Finally, the sample was rinsed with ultra pure water and blown dry with nitrogen.
Thus, the preparation work of the GaN HEMT is completed.
For the sake of clarity, fig. 5 and 6 show schematic diagrams of the fabrication process of the GaN HEMT in a graphical manner. Wherein, the symbol (a) represents an epitaxial substrate; the mark (b) represents the GaN HEMT sample after the medium layer is grown; mark (c) represents a sample with a p-type doped diamond layer grown on the dielectric layer; mark (d) represents the sample after evaporation of the metal hard mask on the sample of p-type doped diamond layer; mark (e) represents the sample after patterned etching of the p-doped diamond layer based on a metal hard mask; mark (f) represents the sample with the metal hard mask etched away; label (g) represents the sample after preparation of the electrically isolated region of the device; mark (h) represents the sample after etching the gate, source and drain electrode regions; reference (i) represents the sample after the source and drain electrodes have been fabricated; the symbol (j) represents a sample of the GaN HEMT after the gate electrode is fabricated, and the sample at this time is a finished product.
In the preparation method of the GaN HEMT based on the p-type doped diamond heat dissipation layer provided by the embodiment of the invention, the p-type doped diamond layer is prepared on the top of the GaN HEMT, and the high heat conductivity of the diamond is utilized to realize effective heat dissipation; in addition, the GaN HEMT prepared by the embodiment of the invention utilizes the interaction of the p-type doped diamond and the conductive channel 2DEG (two-dimensional electron gas) of the GaN HEMT, so that the electric field peak value at the pin of the gate electrode can be reduced, the electric field distribution in the channel is more uniform, and the modulation of the heat generation of the GaN HEMT is realized. Therefore, the GaN HEMT prepared by the preparation method provided by the embodiment of the invention can effectively improve the heat dissipation capability of the GaN HEMT in a microwave high-power scene.
The above completes the description of the method for manufacturing the GaN HEMT based on the p-type diamond doped heat dissipation layer.
In the description of the specification, reference to the description of the term "one embodiment", "some embodiments", "an example", "a specific example", or "some examples", etc., means that a particular feature or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (10)

1. The utility model provides a GaN HEMT based on p type dopes diamond heat dissipation layer which characterized in that includes the substrate that sets up from bottom to top, buffer layer, barrier layer, dielectric layer and the top heat dissipation layer of GaN material, still includes: a source electrode, a drain electrode, and a gate electrode; wherein the content of the first and second substances,
in the horizontal direction, the gate electrode is positioned between the source electrode and the drain electrode, and the top heat dissipation layer is positioned between the gate electrode and the drain electrode and is in contact with the gate electrode;
the source electrode, the drain electrode and the gate electrode respectively penetrate through the dielectric layer to be in contact with the barrier layer;
the upper end of the gate electrode extends towards the drain electrode so as to cover part of the surface of the top heat dissipation layer; the top heat dissipation layer is a p-type doped diamond layer.
2. The GaN HEMT of claim 1, wherein said p-type doped diamond layer is a boron doped diamond layer.
3. The GaN HEMT of claim 1, wherein said p-type doped diamond layer has a thickness of 0.5 to 1 μm.
4. The GaN HEMT of claim 1, wherein the length of said p-type doped diamond layer is greater than or equal to 50% of the horizontal spacing between said gate electrode and said drain electrode, and said p-type doped diamond layer is not in contact with said drain electrode.
5. The GaN HEMT of claim 1, wherein said dielectric layer is a SiN layer; the thickness of the SiN layer is 10 nm-60 nm.
6. The GaN HEMT of claim 1, wherein the barrier layer is AlGaN.
7. The GaN HEMT of claim 1, wherein said source electrode and said drain electrode are each a four-layer metal stack structure consisting of titanium, aluminum, nickel, and gold from bottom to top.
8. The GaN HEMT of claim 1, wherein the gate electrode is a double-layer metal stack structure consisting of nickel and gold bottom-up.
9. A preparation method of a GaN HEMT based on a p-type diamond-doped heat dissipation layer is characterized by comprising the following steps:
step S1: obtaining an epitaxial substrate; the epitaxial substrate comprises a substrate, a buffer layer and a barrier layer which are arranged from bottom to top; the buffer layer is made of GaN;
step S2: growing a dielectric layer on the barrier layer by utilizing a PECVD process;
step S3: growing a top heat dissipation layer on the dielectric layer by an MPCVD process; the top heat dissipation layer is a p-type doped diamond layer;
step S4: carrying out graphical etching on the p-type doped diamond layer based on a metal hard mask to expose the dielectric layer in a partial area;
step S5: preparing a device electric isolation region of the GaN HEMT;
step S6: etching the dielectric layer of the partial area to enable the barrier layer to expose a gate groove area required for preparing a gate electrode, a source electrode area required for preparing a source electrode and a drain electrode area required for preparing a drain electrode; in the horizontal direction, the gate groove region is positioned between the source electrode region and the drain electrode region, and the p-type doped diamond layer after the patterned etching is positioned between the gate groove region and the drain electrode region and is adjacent to the gate groove region;
step S7: preparing a source electrode and a drain electrode on the source electrode area and the drain electrode area by sequentially utilizing a photoetching process and a metal evaporation deposition process;
step S8: and sequentially utilizing a photoetching process and a metal evaporation and deposition process to prepare a gate electrode based on the gate groove region.
10. The method of claim 9, wherein the p-type doped diamond layer is a boron doped diamond layer 0.5 μm to 1 μm thick.
CN202011384359.5A 2020-12-01 2020-12-01 GaN HEMT based on p-type diamond-doped heat dissipation layer and preparation method Pending CN112466943A (en)

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Application publication date: 20210309