CN112444733A - Chip aging state detection method and device - Google Patents
Chip aging state detection method and device Download PDFInfo
- Publication number
- CN112444733A CN112444733A CN202011251252.3A CN202011251252A CN112444733A CN 112444733 A CN112444733 A CN 112444733A CN 202011251252 A CN202011251252 A CN 202011251252A CN 112444733 A CN112444733 A CN 112444733A
- Authority
- CN
- China
- Prior art keywords
- chip
- aging state
- leakage current
- maximum leakage
- detection circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/52—Testing for short-circuits, leakage current or ground faults
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Environmental & Geological Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The embodiment of the invention discloses a chip aging state detection method and device, relates to the technical field of chip detection, and is convenient for detecting the chip aging state caused by TDDB effect. The method comprises the following steps: connecting the output end of at least one power switch device on a chip into a peak current detection circuit; supplying power to the control terminal of the power switching device to enable current to flow to the output terminal through the control terminal; periodically obtaining a maximum leakage current from the output terminal by using the peak current detection circuit; and determining the chip aging state based on the maximum leakage current. The invention is suitable for chip aging test and monitoring occasions.
Description
Technical Field
The invention relates to the technical field of chip detection, in particular to a chip aging state detection method and device.
Background
There are many factors that occur in chip aging, and the chip aging is considered to mainly include aging phenomena caused by carrier injection (HCI), Negative Bias Temperature Instability (NBTI), Positive Bias Temperature Instability (PBTI), etc., and the chip aging effects or factors directly affect the Threshold voltage (often abbreviated as Vth) of the device to affect the magnitude of the driving current generated by the device, and further affect the performance of the whole chip.
The inventor finds in engineering practice that: the chip aging phenomenon caused by Time Dependent Dielectric Breakdown (TDDB) is different from the above-mentioned chip aging phenomenon, and the TDDB effect aging causes the leakage current of the device gate to gradually increase, so that finally the power device on the chip completely loses the power switching characteristic.
The traditional chip aging monitoring scheme is not suitable for monitoring or detecting the chip aging state caused by the TDDB effect.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method and an apparatus for detecting a chip aging state, which are convenient for detecting the chip aging state caused by the TDDB effect.
In a first aspect, an embodiment of the present invention provides a method for detecting a chip aging state, where the method includes:
connecting the output end of at least one power switch device on a chip into a peak current detection circuit;
supplying power to the control terminal of the power switching device to enable current to flow to the output terminal through the control terminal;
periodically obtaining a maximum leakage current from the output terminal by using the peak current detection circuit;
and determining the chip aging state based on the maximum leakage current.
With reference to the first aspect, in a first implementation manner of the first aspect, the determining a chip aging state based on the maximum leakage current includes:
converting the obtained maximum leakage current from analog quantity to digital quantity;
and the aging state of the chip is represented by using the obtained digital quantity quantification.
With reference to the first aspect, the first or second implementation manner of the first aspect, in a third implementation manner of the first aspect, the determining a chip aging state based on the maximum leakage current includes:
converting the maximum leakage current into a pulse signal with a preset pulse width;
converting the pulse signal into a digital quantity;
and quantitatively representing the aging state of the chip by using the obtained digital quantity.
With reference to any one of the first to third implementation manners of the first aspect, in a fourth implementation manner of the first aspect, a supply voltage of the control terminal of the power switching device is consistent with an operating voltage of a chip.
In a second aspect, an embodiment of the present invention provides a device for detecting a chip aging state, including: the peak current detection circuit comprises a comparison circuit, a peak current detection circuit and a power supply;
the power supply is configured to be connected with a control end of the power switch device and used for supplying power to the power switch device;
the peak current detection circuit is configured to be connected to the output end of at least one power switch device on a chip and used for periodically acquiring the maximum leakage current flowing through the power switch device;
the comparison circuit is configured to be electrically connected with the peak current detection circuit, and is used for receiving the maximum leakage current periodically sent by the peak current detection circuit and determining the chip aging state based on the maximum leakage current.
With reference to the second aspect, in a first implementation manner of the second aspect, an analog-to-digital conversion module is disposed at an input end of the comparison circuit, and is configured to convert the acquired maximum leakage current from an analog quantity to a digital quantity, and output the digital quantity to the comparison circuit;
the comparison circuit is specifically used for representing the aging state of the chip by utilizing the obtained digital quantity quantization.
With reference to the first or second implementation manner of the second aspect, in a third implementation manner of the second aspect, the apparatus further includes a current timing conversion module, an input terminal of the current timing conversion module is connected to the output terminal of the peak current detection circuit, and an output terminal of the current timing conversion module is connected to the input terminal of the analog-to-digital conversion module;
the current timing conversion module is used for converting the maximum leakage current into a pulse signal with a preset pulse width and inputting the pulse signal to the analog-to-digital conversion module;
the analog-to-digital conversion module is used for converting the pulse signal into a digital quantity;
and the comparison circuit is used for representing the aging state of the chip by utilizing the obtained digital quantity quantization.
With reference to any one of the first to third embodiments of the second aspect, in a fourth embodiment of the second aspect, a supply voltage of the control terminal of the power switching device is consistent with an operating voltage of the chip.
According to the chip aging state detection method and device provided by the embodiment of the invention, the output end of at least one power switch device on the chip is connected into a peak current detection circuit; supplying power to the control terminal of the power switching device to enable current to flow to the output terminal through the control terminal; periodically obtaining a maximum leakage current from the output terminal by using the peak current detection circuit; and determining the chip aging state based on the maximum leakage current. The aging state of the chip can be reflected by the size of the leakage current of the power switch device, so that the aging state of the chip caused by the TDDB effect can be conveniently detected.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flowchart illustrating a method for detecting a chip aging state according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a method for detecting a chip aging state according to another embodiment of the present invention;
FIG. 3 is a flowchart illustrating a method for detecting the aging state of a chip according to another embodiment of the present invention
FIG. 4 is a circuit diagram of a chip aging status detection apparatus according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an application of the device for detecting the aging state of the chip in FIG. 4;
FIG. 6 is a schematic diagram illustrating an application of a chip aging status detecting apparatus according to another embodiment of the present invention;
FIG. 7 is a schematic diagram of another chip degradation state detection apparatus according to the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The chip aging state detection method and device provided by the embodiment of the invention are suitable for chip aging test and monitoring occasions; for example, chip testing before shipment, chip monitoring during use, etc. The method is particularly suitable for detecting the chip aging state caused by the TDDB effect.
Example one
Referring to fig. 1 and fig. 2, the method for detecting the aging state of the chip provided by the embodiment includes the steps of:
110. and connecting the output end of at least one power switch device on the chip into a peak current detection circuit.
In this embodiment, a plurality of power switches are integrated on the chip, the power switches are, for example, mos (metal oxide semiconductor) transistors, and the aging or the good-bad state of the power switches reflects or determines the performance and the state of the chip to a certain extent. Therefore, the age of the chip is generally determined by detecting the state of the power switching device. For convenience of description and to aid the reader, the power switch device is described as a MOS transistor.
The MOS transistor has a Gate (Gate, Source, S pole for short), and a drain (drain, D pole for short), where the Gate is generally a control terminal, the Source and the drain are output terminals, and a leakage current flowing through the MOS transistor flows from the Gate to the Source or the drain. When the device is connected, the grid is directly or indirectly connected with a power supply source and used for providing gate voltage for the conduction of the MOS tube, and the source and the drain are connected with the input end of the peak current detection circuit.
According to engineering practice, the TDDB effect of the PMOS tube is higher than that of the NMOS tube by at least one order of magnitude. That is, the state of the NMOS is comparatively more susceptible to TDDB. Therefore, the detection method of the present embodiment is more suitable for detecting or monitoring the state of the NMOS.
The Peak current detector circuit (PCD for short) may be directly replaced by a Peak current detector, i.e. a detector commonly referred to as a Peak current detector or a Peak current detector, which is used to periodically obtain useful information in a fluctuating signal and identify the presence or variation of waves, oscillations or signals.
120. And supplying power to the control end of the power switch device to enable current to flow to the output end through the control end.
As mentioned above, the gate voltage required for conduction is provided to the gate of the MOS transistor, so that a current flows through the MOS transistor. When the test, can set up switch drive control circuit between MOS pipe grid to power supply, like this, when needs detect at every turn, through switch drive control circuit drive MOS pipe switch-on can, save the operating procedure of connecting power supply at every turn, be convenient for simplify the detection process.
130. Periodically obtaining a maximum leakage current from the output terminal using the peak current detection circuit.
In this embodiment, after the power switch is connected to the device required for detection, the Test mode starts, where Test _ EN is 1 is the Test mode and Test _ EN is 0 is the compression mode (i.e., untested state). The peak current detection circuit is used for periodically capturing the maximum leakage current generated by the power switch device during the test period and outputting the maximum leakage current.
140. And determining the chip aging state based on the maximum leakage current.
In this embodiment, the Processing may be implemented by a logic control circuit, or may be implemented by a Processor (Central Processing Unit/Processor), a single chip microcomputer, or the like.
The specific implementation mode can be as follows: and presetting a standard current value, and comparing the captured maximum leakage current with the standard current value to determine the aging degree of the chip.
Specifically, the degree of aging can also be quantitatively expressed according to the comparison result.
According to the chip aging state detection method provided by the embodiment of the invention, the output end of at least one power switch device on a chip is connected into a peak current detection circuit; supplying power to the control terminal of the power switching device to enable current to flow to the output terminal through the control terminal; periodically obtaining a maximum leakage current from the output terminal by using the peak current detection circuit; the chip aging state can be determined based on the maximum leakage current.
The aging state of the chip can be reflected by the size of the leakage current of the power switch device, so that the aging state of the chip caused by the TDDB effect can be conveniently detected.
Referring to FIG. 2, in some embodiments, step 140, determining the chip aging status based on the maximum leakage current comprises the steps of:
141A, converting the acquired maximum leakage current from analog quantity to digital quantity.
In this embodiment, the implementation may be through an analog-to-digital converter.
142A, the aging state of the chip is represented by the obtained digital quantity quantization.
In this embodiment, the maximum leakage current is converted from an analog quantity to a digital quantity, and the obtained digital quantity can quantitatively represent the aging degree of the chip. Due to the fact that the quantitative characterization of the aging degree of the chip is achieved, an engineer can decide the further processing of the chip according to the aging degree. E.g., discarded or repaired, and continued use.
Referring to FIG. 3, in other embodiments, determining the chip aging state based on the maximum leakage current at step 140 includes: 141B converting the maximum leakage current into a pulse signal of a predetermined pulse width; the maximum leakage Current may be converted into a pulse signal having a certain pulse width by a Current to time converter (C2T).
142B, converting the pulse signal into a digital quantity; 143B, the aging state of the chip is represented by the obtained digital quantity quantization.
The conversion of the pulse signal into a digital quantity can be realized by an analog-to-digital converter, if the maximum leakage current is monitored to be almost 0, the pulse width of the pulse signal output by the conversion is almost 0, and 0 is output, so as to represent that no aging caused by TDDB effect occurs. If the maximum leakage current value exceeds the standard current value, the pulse signal with the output width larger than 0 is converted, and a figure larger than 0 is output to represent the aging degree caused by the TDDB effect. The larger the leakage current is, the larger the pulse signal width is, the larger the aging degree of the power switch device is, and the larger the influence on the performance of the corresponding chip is.
In order to ensure that the test result of the power switch device can relatively truly represent the aging state of the chip, the power supply voltage of the control end of the power switch device is consistent with the working voltage of the chip during testing.
In addition, the conventional aging monitoring circuits proposed are mostly based on frequency variations of some oscillators for aging phenomena caused by Hot-carrier injection (HCI), Negative Bias Temperature Instability (NBTI), Positive Bias Temperature Instability (PBTI), etc. described in the background art, but the influence of aging of the TDDB effect on the oscillator frequency is non-linear, and thus, the conventional method is not well suited to monitoring the TDDB aging phenomenon.
According to the above description, the chip aging state detection method provided by the present scheme can detect and quantify the aging state of the chip conveniently and accurately by measuring the maximum leakage current of the gate of the power switch device, and then comparing the maximum leakage current intensity with the standard current to judge the chip aging degree caused by the TDDB effect.
Example two
FIG. 4 is a circuit diagram of an embodiment of a chip aging status detection apparatus according to the present invention; FIG. 5 is a schematic diagram illustrating an application of the chip aging status detecting apparatus according to an embodiment of the present invention. Referring to fig. 1, 4 and 5, the chip aging state detection apparatus according to the embodiment of the present invention includes a comparison circuit, a peak current detection circuit and a power supply.
The power supply is configured to be connected to a control terminal of the power switching device and used for supplying power to the power switching device.
And the power supply voltage of the power supply is consistent with the working voltage of the chip.
The peak current detection circuit is configured to be connected to an output end of at least one power switch device on a chip and used for periodically obtaining the maximum leakage current flowing through the power switch device.
The comparison circuit is configured to be electrically connected with the peak current detection circuit, and is used for receiving the maximum leakage current periodically sent by the peak current detection circuit and determining the chip aging state based on the maximum leakage current.
The peak current detection circuit can directly adopt a peak detector. The comparator circuit may employ a comparator for comparing an input signal with a predetermined value, in this embodiment, for comparing the maximum leakage current with a standard current value.
Referring to fig. 2 and fig. 6, in some embodiments, the input end of the comparison circuit is provided with an analog-to-digital conversion module, and the analog-to-digital conversion module is configured to convert the acquired maximum leakage current from an analog quantity to a digital quantity, and output the digital quantity to the comparison circuit.
The comparison circuit is specifically used for representing the aging state of the chip by utilizing the obtained digital quantity quantization.
It will be appreciated that the analog to digital conversion block and the comparator are sometimes integrated in one device, forming a device with a comparator and an analog to digital conversion block, such as an analog to digital converter with comparator functionality; of course, a comparator having an analog-to-digital conversion function may be used.
Referring to fig. 3 and 7, in some embodiments, the apparatus further comprises a current timing conversion module, an input of the current timing conversion module is connected to the output of the peak current detection circuit, and an output of the current timing conversion module is connected to the input of the analog-to-digital conversion module;
the current timing conversion module is used for converting the maximum leakage current into a pulse signal with a preset pulse width and inputting the pulse signal to the analog-to-digital conversion module;
and the analog-to-digital conversion module is used for converting the pulse signal into a digital quantity and outputting the digital quantity to the comparison circuit.
And the comparison circuit is used for representing the aging state of the chip by utilizing the obtained digital quantity quantization.
The chip aging state detection apparatus provided in the embodiment of the present invention is connected to at least one power switching device on a chip, and can conveniently and quantitatively determine the chip aging state based on the maximum leakage current by detecting the maximum leakage current flowing through the power switching device.
Therefore, the detection device is convenient to detect the chip aging state caused by the TDDB effect.
It should be noted that the solution and the first embodiment of the present invention have corresponding specific technical features, and the specific technical solutions and technical effects are similar to those of the first embodiment, except that the detection method of the first embodiment may be implemented by hardware provided in the present embodiment.
For each embodiment provided by the invention, the technical scheme and the technical effect are basically the same, and relevant parts can be referred to each other.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term "comprising", without further limitation, means that the element so defined is not excluded from the group consisting of additional identical elements in the process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same or similar parts among the embodiments may be referred to each other, and each embodiment focuses on differences from other embodiments.
For convenience of description, the above chip degradation state detection apparatus is described separately in terms of functional division into various functional units/circuits/modules. Of course, the functionality of the units/modules may be implemented in one or more software and/or hardware implementations of the invention.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. A chip aging state detection method is characterized by comprising the following steps:
connecting the output end of at least one power switch device on a chip into a peak current detection circuit;
supplying power to the control terminal of the power switching device to enable current to flow to the output terminal through the control terminal;
periodically obtaining a maximum leakage current from the output terminal by using the peak current detection circuit;
and determining the chip aging state based on the maximum leakage current.
2. The method of claim 1, wherein determining a chip aging state based on the maximum leakage current comprises:
converting the obtained maximum leakage current from analog quantity to digital quantity;
and the aging state of the chip is represented by using the obtained digital quantity quantification.
3. The method of claim 1, wherein determining a chip aging state based on the maximum leakage current comprises:
converting the maximum leakage current into a pulse signal with a preset pulse width;
converting the pulse signal into a digital quantity;
and quantitatively representing the aging state of the chip by using the obtained digital quantity.
4. The method according to any one of claims 1 to 3, wherein the supply voltage of the control terminal of the power switch device is consistent with the operating voltage of the chip.
5. A chip aging state detection device is characterized by comprising: the peak current detection circuit comprises a comparison circuit, a peak current detection circuit and a power supply;
the power supply is configured to be connected with a control end of the power switch device and used for supplying power to the power switch device;
the peak current detection circuit is configured to be connected to the output end of at least one power switch device on a chip and used for periodically acquiring the maximum leakage current flowing through the power switch device;
the comparison circuit is configured to be electrically connected with the peak current detection circuit, and is used for receiving the maximum leakage current periodically sent by the peak current detection circuit and determining the chip aging state based on the maximum leakage current.
6. The chip aging state detection device according to claim 5, wherein an analog-to-digital conversion module is provided at an input end of the comparison circuit, and is configured to convert the obtained maximum leakage current from an analog quantity to a digital quantity, and output the digital quantity to the comparison circuit;
the comparison circuit is specifically used for representing the aging state of the chip by utilizing the obtained digital quantity quantization.
7. The apparatus according to claim 6, further comprising a current timing conversion module, wherein an input terminal of the current timing conversion module is connected to an output terminal of the peak current detection circuit, and an output terminal of the current timing conversion module is connected to an input terminal of the analog-to-digital conversion module;
the current timing conversion module is used for converting the maximum leakage current into a pulse signal with a preset pulse width and inputting the pulse signal to the analog-to-digital conversion module;
the analog-to-digital conversion module is used for converting the pulse signal into a digital quantity;
and the comparison circuit is used for representing the aging state of the chip by utilizing the obtained digital quantity quantization.
8. The apparatus for detecting the aging state of a chip according to any one of claims 5 to 7, wherein the power supply voltage of the control terminal of the power switch device is consistent with the operating voltage of the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011251252.3A CN112444733B (en) | 2020-11-10 | 2020-11-10 | Chip aging state detection method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011251252.3A CN112444733B (en) | 2020-11-10 | 2020-11-10 | Chip aging state detection method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112444733A true CN112444733A (en) | 2021-03-05 |
| CN112444733B CN112444733B (en) | 2023-07-21 |
Family
ID=74735767
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011251252.3A Active CN112444733B (en) | 2020-11-10 | 2020-11-10 | Chip aging state detection method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112444733B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113253088A (en) * | 2021-06-25 | 2021-08-13 | 上海瞻芯电子科技有限公司 | Transistor gate oxide testing device and system |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5471429A (en) * | 1993-11-26 | 1995-11-28 | Samsung Electronics Co., Ltd. | Burn-in circuit and method therefor of semiconductor memory device |
| CN101303390A (en) * | 2008-06-23 | 2008-11-12 | 上海集成电路研发中心有限公司 | Method for judging MOS device performance degeneration |
| CN101545945A (en) * | 2008-03-25 | 2009-09-30 | 中芯国际集成电路制造(上海)有限公司 | Method for testing leakage current of MOS device |
| WO2010097986A1 (en) * | 2009-02-25 | 2010-09-02 | シャープ株式会社 | Shift register and display device |
| CN102385029A (en) * | 2011-08-26 | 2012-03-21 | 上海宏力半导体制造有限公司 | Method for testing high-voltage MOS device |
| CN102736016A (en) * | 2011-03-31 | 2012-10-17 | 英特尔移动通信有限公司 | Circuit arrangement with a plurality of on-chip monitor circuits and a control circuit and corresponding methods |
| CN104198907A (en) * | 2014-09-10 | 2014-12-10 | 广东美的集团芜湖制冷设备有限公司 | Power device current leakage detecting device and intelligent power module detecting equipment |
| CN105158670A (en) * | 2015-10-13 | 2015-12-16 | 中国人民解放军海军工程大学 | IGBT health state monitoring method based on leakage current of collector electrode |
| CN204905865U (en) * | 2015-09-10 | 2015-12-23 | 山东亿玛信诺电气有限公司 | Three -phase equilibrium high pressure takes accuse device |
| CN106291331A (en) * | 2016-09-14 | 2017-01-04 | 电子科技大学 | Integrated circuit life detecting method based on TDDB effect and system |
| CN106771477A (en) * | 2016-11-28 | 2017-05-31 | 国网福建省电力有限公司 | The highly sensitive high voltage direct current cable leakage current detection sensor of New Large Caliber |
| CN108363012A (en) * | 2018-01-17 | 2018-08-03 | 广州市香港科大霍英东研究院 | A kind of vehicle lithium battery startup power supply Primary Component fault detection system and method |
| CN108562841A (en) * | 2018-06-14 | 2018-09-21 | 山东阅芯电子科技有限公司 | leakage current detection method and device in electronic component environmental aging test |
| JP2019050087A (en) * | 2017-09-08 | 2019-03-28 | カルソニックカンセイ株式会社 | Leakage current detection device and heating apparatus |
-
2020
- 2020-11-10 CN CN202011251252.3A patent/CN112444733B/en active Active
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5471429A (en) * | 1993-11-26 | 1995-11-28 | Samsung Electronics Co., Ltd. | Burn-in circuit and method therefor of semiconductor memory device |
| CN101545945A (en) * | 2008-03-25 | 2009-09-30 | 中芯国际集成电路制造(上海)有限公司 | Method for testing leakage current of MOS device |
| CN101303390A (en) * | 2008-06-23 | 2008-11-12 | 上海集成电路研发中心有限公司 | Method for judging MOS device performance degeneration |
| WO2010097986A1 (en) * | 2009-02-25 | 2010-09-02 | シャープ株式会社 | Shift register and display device |
| CN102736016A (en) * | 2011-03-31 | 2012-10-17 | 英特尔移动通信有限公司 | Circuit arrangement with a plurality of on-chip monitor circuits and a control circuit and corresponding methods |
| CN102385029A (en) * | 2011-08-26 | 2012-03-21 | 上海宏力半导体制造有限公司 | Method for testing high-voltage MOS device |
| CN104198907A (en) * | 2014-09-10 | 2014-12-10 | 广东美的集团芜湖制冷设备有限公司 | Power device current leakage detecting device and intelligent power module detecting equipment |
| CN204905865U (en) * | 2015-09-10 | 2015-12-23 | 山东亿玛信诺电气有限公司 | Three -phase equilibrium high pressure takes accuse device |
| CN105158670A (en) * | 2015-10-13 | 2015-12-16 | 中国人民解放军海军工程大学 | IGBT health state monitoring method based on leakage current of collector electrode |
| CN106291331A (en) * | 2016-09-14 | 2017-01-04 | 电子科技大学 | Integrated circuit life detecting method based on TDDB effect and system |
| CN106771477A (en) * | 2016-11-28 | 2017-05-31 | 国网福建省电力有限公司 | The highly sensitive high voltage direct current cable leakage current detection sensor of New Large Caliber |
| JP2019050087A (en) * | 2017-09-08 | 2019-03-28 | カルソニックカンセイ株式会社 | Leakage current detection device and heating apparatus |
| CN108363012A (en) * | 2018-01-17 | 2018-08-03 | 广州市香港科大霍英东研究院 | A kind of vehicle lithium battery startup power supply Primary Component fault detection system and method |
| CN108562841A (en) * | 2018-06-14 | 2018-09-21 | 山东阅芯电子科技有限公司 | leakage current detection method and device in electronic component environmental aging test |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113253088A (en) * | 2021-06-25 | 2021-08-13 | 上海瞻芯电子科技有限公司 | Transistor gate oxide testing device and system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112444733B (en) | 2023-07-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7710141B2 (en) | Method and apparatus for dynamic characterization of reliability wearout mechanisms | |
| US8519730B2 (en) | Circuit, system, and method for degradation detection | |
| US11774470B2 (en) | Load detection system and load detection method thereof | |
| US10763836B2 (en) | Measuring circuit for quantizing variations in circuit operating speed | |
| CN100531474C (en) | Heater power control circuit and burn-in apparatus using the same | |
| CN112444733A (en) | Chip aging state detection method and device | |
| CN111919129A (en) | Apparatus and method for monitoring power of multiple chips | |
| CN216646725U (en) | Chip pin test system | |
| US20190205196A1 (en) | On-chip tddb degradation monitoring and failure early warning circuit for soc | |
| US11287462B2 (en) | Status detection of alarm sounding parts | |
| Roy et al. | State of health (SOH) estimation of multiple switching devices using a single intelligent gate driver module | |
| CN107991543B (en) | Gate charge quantity measuring circuit and method of insulated gate bipolar transistor | |
| CN114355134B (en) | Online state monitoring circuit based on power device turn-on delay time | |
| JP2023148069A (en) | Semiconductor inspection device and semiconductor inspection method | |
| CN113176482B (en) | Test circuit, test system and test method thereof | |
| CN108955930A (en) | temperature measuring circuit | |
| CN113589126A (en) | Transient time measuring device, junction temperature measuring system and method of power electronic device | |
| CN115656758B (en) | Method for detecting semiconductor CV characteristic empty clamp | |
| JP4811986B2 (en) | Inspection method of semiconductor integrated circuit | |
| CN115184784B (en) | Digital circuit connection type intermittent fault test system and method based on power supply current | |
| US8767900B2 (en) | Signal transition detection circuit and method of the same | |
| CN113049921B (en) | TDDB test structure, TDDB test system and test method thereof | |
| CN117491842A (en) | Method for optimizing DC parameter accuracy and shortening test time | |
| Piraghaj et al. | A low-cost, minimally-invasive embedded monitoring method for early detection of transistor on-state resistance degradation in power electronics systems | |
| TWI451110B (en) | Dc-to-dc converter having test circuit and test method of the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |