CN216646725U - Chip pin test system - Google Patents
Chip pin test system Download PDFInfo
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- CN216646725U CN216646725U CN202122447900.9U CN202122447900U CN216646725U CN 216646725 U CN216646725 U CN 216646725U CN 202122447900 U CN202122447900 U CN 202122447900U CN 216646725 U CN216646725 U CN 216646725U
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Abstract
The application relates to a chip pin test system, through detecting the first electric current of the chip pin that awaits measuring and with the second electric current of the chip pin that awaits measuring under the same condition of chip, judge whether the chip pin work that awaits measuring is unusual according to the contrast result between first electric current and the second electric current, whether it is unusual to judge the chip pin only through the reverse conduction voltage that detects the chip pin, can accurately judge whether the chip pin is unusual according to the electric current condition that detects under the condition of even detecting reverse conduction voltage, thereby realize the operating condition of accurate definite chip pin.
Description
Technical Field
The application relates to the technical field of chip testing, in particular to a chip pin testing system.
Background
Currently, whether a certain pin of a chip is damaged or not is checked, a universal meter is dialed to a diode gear, the reverse conduction voltage of a PN junction of the pin of the chip is measured, and the reverse conduction voltage is usually measured, so that the pin of the chip is considered to be normally not damaged; and if the reverse conduction voltage is not measured, the chip pin is considered to be damaged. However, even if the reverse conduction voltage is measured by using a multimeter in practice, the operation of the chip pin cannot be explained to be normal, so that the phenomenon that the reverse conduction voltage is measured but the operation of the chip pin is still abnormal is often encountered.
SUMMERY OF THE UTILITY MODEL
The application provides a chip pin test system to solve the problem of how to accurately detect whether a chip pin is abnormal.
The application provides a chip pin test system, includes:
the voltage source circuit is used for respectively providing variable voltage for the reference chip and the chip to be tested, wherein the variable voltage is dynamically changed voltage;
the sampling circuit is connected with the voltage source circuit and is used for collecting a first current output by the reference chip under the excitation of the variable voltage and a second current output by the chip to be tested under the excitation of the variable voltage;
and the main control module is connected with the sampling circuit and used for determining the pin state of the chip to be tested according to the result of the ratio of the first current to the second current.
Optionally, the system further comprises:
the switching circuit is connected with the voltage source circuit, the reference chip and the chip to be detected and used for providing the variable voltage output by the voltage source circuit to the reference chip in a first switching state and providing the variable voltage to the chip to be detected in a second switching state, wherein the first switching state is used for enabling the voltage source circuit to be connected with the reference chip, and the second switching state is used for enabling the voltage source circuit to be connected with the chip to be detected.
Optionally, the system further includes a current limiting circuit, a first end of the current limiting circuit is connected to the voltage source circuit, and a second end of the current limiting circuit is connected to the switch circuit, and is configured to divide the variable voltage and provide the divided voltage to the reference chip and the chip to be tested.
Optionally, the switch circuit includes a first switch and a second switch, a first end of the first switch is connected to the current limiting circuit, a second end of the first switch is connected to the reference chip, a first end of the second switch is connected to the current limiting circuit, and a second end of the second switch is connected to the chip to be tested.
Optionally, the sampling circuit comprises;
the sampling circuit is connected with the reference chip and the chip to be tested;
and the analog-to-digital conversion circuit is connected with the sampling circuit and the voltage source circuit and is used for acquiring the first current or the second current flowing through the sampling circuit, converting the variable voltage into a voltage digital signal, converting the first current into a first digital signal and converting the second current into a second digital signal.
Optionally, the sampling circuit includes a sampling resistor, a first end of the sampling resistor is connected to the reference chip, the first end of the sampling resistor is further connected to the chip to be tested, the first end of the sampling resistor is further connected to the first end of the analog-to-digital conversion circuit, a second end of the sampling resistor is connected to the analog-to-digital conversion circuit, the second end of the sampling resistor is further connected to the voltage source circuit, and the second end of the sampling resistor is further grounded.
Optionally, the main control module includes:
the data processing module is used for receiving the voltage digital signal, the first current signal and the second current signal, and generating a first change curve and a second change curve according to the voltage digital signal, the first current signal and the second current signal in an integrated mode, wherein the first change curve is used for indicating a change relation between the voltage digital signal and the first current signal, and the second change curve is used for indicating a change relation between the voltage digital signal and the second current signal;
and the display module is connected with the data processing module and used for displaying the first change curve and the second change curve.
Optionally, the data processing module is further configured to determine that the pin state of the chip to be tested is abnormal when the first variation curve is not matched with the second variation curve.
Optionally, the data processing module is further configured to determine that the pin state of the chip to be tested is normal under the condition that the first variation curve is matched with the second variation curve.
Optionally, the voltage source circuit is a signal generator.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages:
the system that this application embodiment provided, through the first electric current that detects the chip pin that awaits measuring and with the second electric current that consults the chip pin under the chip identical condition that awaits measuring, judge whether the chip pin that awaits measuring works unusually according to the contrast result between first electric current and the second electric current, whether the chip pin is unusual is judged to reverse breakover voltage through detecting the chip pin alone, can accurately judge whether the chip pin is unusual according to the electric current condition that detects under the condition of even detecting reverse breakover voltage, thereby realize the operating condition of accurate definite chip pin.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the utility model and together with the description, serve to explain the principles of the utility model.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a chip pin testing system according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of a variation curve of a variation voltage according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a chip pin testing system according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram illustrating a test result of a chip pin according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a schematic structural diagram of a chip pin testing system according to an embodiment of the present disclosure, in which a chip pin testing system is provided, the system includes:
the voltage source circuit 110 is configured to provide a varying voltage for the reference chip 120 and the chip 130 to be tested, respectively, where the varying voltage is a dynamically varying voltage.
Specifically, the voltage source circuit 110 generally includes an oscillator, a master oscillator output adjust potentiometer, a voltage amplifier, an output attenuator, a power amplifier, an impedance transformer, and an indicating voltmeter. The oscillator generates a low-frequency sinusoidal oscillation signal, the low-frequency sinusoidal oscillation signal is amplified by the voltage amplifier to meet the requirement of voltage output amplitude, the voltage can be directly output through the output attenuator, and the magnitude of the output voltage is adjusted by the main-oscillation output adjustment potentiometer, so that the reference chip 120 and the chip 130 to be tested are provided with variable voltages. The reference chip 120 is a chip with the same type as the chip 130 to be tested and a normal pin, so that the reference chip 120 and the chip 130 to be tested are placed in the same test environment, and whether the pin of the chip 130 to be tested is abnormal is determined according to the comparison of the test results of the reference chip 120 and the chip 130 to be tested. The voltage source circuit 110 may be embodied as a signal generator.
Referring to fig. 2, the voltage output by the voltage source circuit 110 gradually increases with time, that is, the voltages applied to the reference chip 120 and the chip 130 to be tested are gradually increased, so as to detect the current variation condition of the chip 130 to be tested under different voltage excitations, and thus the chip pin operating state can be known more comprehensively through the current variation condition.
And the sampling circuit 150 is connected to the voltage source circuit 110, and is configured to collect a first current output by the reference chip 120 under the excitation of the varying voltage and a second current output by the chip 130 to be tested under the excitation of the varying voltage.
Specifically, the sampling circuit 150 samples the current condition of the pins of the reference chip 120 and the chip 130 under test under excitation of varying voltages, and the sampling circuit 150 is usually composed of one or more resistors connected in series or in parallel, or a resistor and a comparator.
Under the excitation of different variation voltages, the corresponding current of the reference chip 120 or the chip 130 to be tested also varies accordingly.
And a main control module 140 connected to the sampling circuit 150, and configured to determine a pin state of the chip 130 to be tested according to a result of a ratio between the first current and the second current.
Specifically, the main control module 140 is usually a chip, an integrated circuit, or a device with data processing capability, the main control module 140 performs comparison processing according to the received first current and second current, and if a current difference between the first current and the second current is smaller than a set threshold, it is determined that the pin status of the chip 130 to be tested is normal; if the current difference between the first current and the second current is greater than or equal to the set threshold, it is determined that the pin status of the chip 130 to be tested is abnormal. In this embodiment, the main control module 140 is a computer device with data processing capability.
In one embodiment, the system further comprises:
and a switch circuit, connected to the voltage source circuit 110, the reference chip 120 and the chip 130 to be tested, for providing the variable voltage output by the voltage source circuit 110 to the reference chip 120 in a first switch state, and providing the variable voltage to the chip 130 to be tested in a second switch state, where the first switch state is used to connect the voltage source circuit 110 to the reference chip 120, and the second switch state is used to connect the voltage source circuit 110 to the chip 130 to be tested.
Specifically, the switch circuit is used for realizing the function of power supply switching, that is, the test process of the reference chip 120 is isolated from the test process of the chip 130 to be tested by the switch circuit, that is, when the switch circuit is in a first switch state, the voltage source circuit 110 is connected with the reference chip 120, the voltage source circuit 110 and the chip 130 to be tested are in a disconnection state, at this time, the voltage source circuit 110 outputs a variation voltage to be provided to the reference chip 120, and at this time, the test reference chip 120 tests the current variation condition under the excitation of the variation voltage; when the switch circuit is in the second switch state, the voltage source circuit 110 is connected to the chip 130 to be tested, the voltage source circuit 110 and the reference chip 120 are disconnected, the voltage source circuit 110 outputs a variable voltage to the chip 130 to be tested, and the chip 130 to be tested is tested for current variation under the excitation of the variable voltage. In the testing process of the two chips, the output voltage variation trends of the voltage source circuit 110 are the same, and are both the voltage variation conditions shown in fig. 2, so as to ensure that the test environments of the reference chip 120 and the chip 130 to be tested are the same, so as to accurately determine the working state of the pin of the chip 130 to be tested.
In one embodiment, the system further includes a current limiting circuit, a first end of the current limiting circuit is connected to the voltage source circuit 110, and a second end of the current limiting circuit is connected to the switch circuit, and the current limiting circuit is configured to divide the variable voltage and then provide the divided voltage to the reference chip 120 and the chip 130 to be tested.
Specifically, because the change voltage is the growth trend, in order to avoid the damage of crescent voltage to the chip pin, then add the current-limiting circuit between voltage source circuit 110 and switch circuit to reach the effect of partial pressure, and then reduced the voltage of exerting on the chip pin, thereby reduced the output current of chip pin, avoided the chip pin to produce the phenomenon that overflows and burn out. The current limiting circuit is generally composed of one or more current limiting resistors and a transistor, and in order to reduce cost, in this embodiment, the current limiting circuit performs voltage division processing through one current limiting resistor.
In one embodiment, the switch circuit includes a first switch and a second switch, a first terminal of the first switch is connected to the current limiting circuit, a second terminal of the first switch is connected to the reference chip 120, a first terminal of the second switch is connected to the current limiting circuit, and a second terminal of the second switch is connected to the chip 130 under test.
Specifically, referring to fig. 3, S1 is used to indicate a first switch, S2 is used to indicate a second switch, the comparison reference a is used to indicate the reference chip 120, the object B to be tested is used to indicate the chip 130 to be tested, the first switch is disposed between the current limiting circuit and the reference chip 120, the first switch is in a closed state, so that the varying voltage output by the voltage source circuit 110 is provided to the reference chip 120, and the second switch is in an open state when the first switch is in the closed state; the second switch is in a closed state, so that the variable voltage output by the voltage source circuit 110 is provided to the chip 130 to be tested, and similarly, the first switch is in an open state when the second switch is in the closed state. The pin test modes of the reference chip 120 and the chip 130 to be tested are switched by the first switch and the second switch.
The switching rule of the first switch and the second switch may specifically be that after the reference chip 120 or the chip to be tested 130 completes all tests, the chip to be tested 130 or the reference chip 120 is tested by switching the switching states of the first switch and the second switch; in the case that the variation voltage is at the first value, after the reference chip 120 and the chip 130 to be tested are respectively tested by switching the first switch and the second switch, the variation voltage may be adjusted to the second value, and then the reference chip 120 and the chip 130 to be tested are respectively tested by switching the first switch and the second switch.
In one embodiment, the sampling circuit 150 includes;
a sampling circuit connected to the reference chip 120 and the chip 130 to be tested;
and an analog-to-digital conversion circuit connected to the sampling circuit and the voltage source circuit 110, and configured to collect the first current or the second current flowing through the sampling circuit, convert the variation voltage into a voltage digital signal, convert the first current into a first digital signal, and convert the second current into a second digital signal.
Specifically, the sampling circuit usually selects components and parts with low resistance and high precision, because the current of the chip pin cannot be directly obtained, the current flowing condition of the chip pin is reflected through the sampling circuit, the analog-to-digital conversion circuit collects the current flowing through the sampling circuit, so as to realize the current sampling of the chip pin, the analog-to-digital conversion circuit can be specifically an ADC analog-to-digital sampler, the analog-to-digital conversion circuit is further connected with the voltage source circuit 110, and is used for synchronously receiving the variation voltage, converting the variation voltage into a voltage digital signal, converting the first current collected on the pin of the reference chip 120 into a first digital signal, converting the second current on the pin of the chip 130 to be detected into a second digital signal, and converting the analog signal into a digital signal to be convenient for the main control module 140 to analyze. The ADC sampling block in fig. 3 is used to indicate the analog-to-digital conversion circuit.
In one embodiment, the sampling circuit includes a sampling resistor, a first end of the sampling resistor is connected to the reference chip 120, a first end of the sampling resistor is further connected to the chip 130 to be tested, a first end of the sampling resistor is further connected to a first end of the analog-to-digital conversion circuit, a second end of the sampling resistor is connected to the analog-to-digital conversion circuit, a second end of the sampling resistor is further connected to the voltage source circuit 110, and a second end of the sampling resistor is further connected to ground.
Specifically, in order to reduce the cost, the sampling resistor is used as the sampling circuit, that is, the sampling resistor in fig. 3 is the sampling resistor, the analog-to-digital conversion circuit collects the current flowing through the sampling resistor, and the analog-to-digital conversion circuit converts the collected current analog signal into a digital signal and transmits the digital signal to the main control module 140.
In one embodiment, the main control module 140 includes:
the data processing module is used for receiving the voltage digital signal, the first current signal and the second current signal, and generating a first change curve and a second change curve according to the voltage digital signal, the first current signal and the second current signal in an integrated mode, wherein the first change curve is used for indicating a change relation between the voltage digital signal and the first current signal, and the second change curve is used for indicating a change relation between the voltage digital signal and the second current signal;
and the display module is connected with the data processing module and used for displaying the first change curve and the second change curve.
Specifically, the data processing module may be any chip or integrated circuit capable of implementing a data processing function, the data processing module is configured to generate a UI variation curve according to the voltage digital signal, the first digital signal, and the second digital signal, and the display module is configured to display the UI variation curve, as shown in fig. 4, so that a tester can visually know the test results of the chip 130 to be tested and the reference chip 120, and can feed back the test progress through the display module in real time during the chip testing process. The integration of the data processing module and the display module is the computer in fig. 3.
In an embodiment, the data processing module is further configured to determine that the pin status of the chip 130 to be tested is abnormal when the first variation curve is not matched with the second variation curve.
Specifically, referring to fig. 4, comparing that reference a is used to indicate a first variation curve, and object B to be tested is used to indicate a second variation curve, the variation voltage is within 0-0.4V, and both the first current and the second current are 0, which indicates that the reverse conduction voltage of the PN junctions of the reference chip 120 and the chip 130 to be tested is about 0.4V, since the variation voltage gradually increases with time, the first current increases with the increase of the variation voltage, and until the variation voltage reaches 1.4V, the first current does not increase with the increase of the variation voltage, but stabilizes at 10 mA. After the second current is 0.4V, the second current does not increase obviously with the increase of the variation voltage, and the current difference between the second current and the first current is large under the excitation of the same variation voltage, that is, the first variation curve is not matched with the second variation curve, so that it can be known that the current output capability of the pin of the chip 130 to be detected is weak, which indicates that the pin of the chip 130 to be detected is damaged, which indicates that the pin of the chip cannot be accurately judged to work normally under the condition that the reverse conduction voltage of the PN junction is measured by using a multimeter.
After the abnormality of the chip pin is determined, corresponding prompt information is generated, the prompt information can be displayed through the display module, and the prompt information comprises a test result, namely the chip 130 pin to be tested works normally or abnormally, so that a tester can know the test result conveniently.
In an embodiment, the data processing module is further configured to determine that the pin status of the chip 130 to be tested is normal when the first variation curve matches the second variation curve.
Specifically, when the current difference between the first current and the second current is smaller than the set threshold under the excitation of the same variation voltage, the first variation curve is matched with the second variation curve, which indicates that the pin of the chip 130 to be tested is working normally.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, system, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, system, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, system, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the utility model. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A chip pin testing system, the system comprising:
the voltage source circuit is used for respectively providing variable voltage for the reference chip and the chip to be tested, wherein the variable voltage is dynamically changed voltage;
the sampling circuit is connected with the voltage source circuit and is used for collecting a first current output by the reference chip under the excitation of the variable voltage and a second current output by the chip to be tested under the excitation of the variable voltage;
and the main control module is connected with the sampling circuit and used for determining the pin state of the chip to be tested according to the result of the ratio of the first current to the second current.
2. The system of claim 1, further comprising:
the switching circuit is connected with the voltage source circuit, the reference chip and the chip to be detected and used for providing the variable voltage output by the voltage source circuit to the reference chip in a first switching state and providing the variable voltage to the chip to be detected in a second switching state, wherein the first switching state is used for enabling the voltage source circuit to be connected with the reference chip, and the second switching state is used for enabling the voltage source circuit to be connected with the chip to be detected.
3. The system of claim 2, further comprising a current limiting circuit, wherein a first end of the current limiting circuit is connected to the voltage source circuit, and a second end of the current limiting circuit is connected to the switch circuit, and is configured to divide the variable voltage and provide the divided voltage to the reference chip and the chip to be tested.
4. The system of claim 3, wherein the switching circuit comprises a first switch and a second switch, a first terminal of the first switch is connected to the current limiting circuit, a second terminal of the first switch is connected to the reference chip, a first terminal of the second switch is connected to the current limiting circuit, and a second terminal of the second switch is connected to the chip under test.
5. The system of claim 1, wherein the sampling circuit comprises;
the sampling circuit is connected with the reference chip and the chip to be tested;
and the analog-to-digital conversion circuit is connected with the sampling circuit and the voltage source circuit and is used for collecting the first current or the second current flowing through the sampling circuit, converting the variable voltage into a voltage digital signal, converting the first current into a first digital signal and converting the second current into a second digital signal.
6. The system according to claim 5, wherein the sampling circuit comprises a sampling resistor, a first end of the sampling resistor is connected to the reference chip, a first end of the sampling resistor is further connected to the chip to be tested, a first end of the sampling resistor is further connected to a first end of the analog-to-digital conversion circuit, a second end of the sampling resistor is connected to the analog-to-digital conversion circuit, a second end of the sampling resistor is further connected to the voltage source circuit, and a second end of the sampling resistor is further grounded.
7. The system of claim 5, wherein the master module comprises:
the data processing module is used for receiving the voltage digital signal, the first current signal and the second current signal, and generating a first change curve and a second change curve according to the voltage digital signal, the first current signal and the second current signal in an integrated mode, wherein the first change curve is used for indicating a change relation between the voltage digital signal and the first current signal, and the second change curve is used for indicating a change relation between the voltage digital signal and the second current signal;
and the display module is connected with the data processing module and is used for displaying the first change curve and the second change curve.
8. The system according to claim 7, wherein the data processing module is further configured to determine that the pin status of the chip under test is abnormal if the first variation curve does not match the second variation curve.
9. The system of claim 7, wherein the data processing module is further configured to determine that the pin status of the chip under test is normal if the first variation curve matches the second variation curve.
10. The system of claim 1, wherein the voltage source circuit is a signal generator.
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| CN202122447900.9U CN216646725U (en) | 2021-10-11 | 2021-10-11 | Chip pin test system |
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| CN202122447900.9U CN216646725U (en) | 2021-10-11 | 2021-10-11 | Chip pin test system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115980502A (en) * | 2023-03-20 | 2023-04-18 | 宁波群芯微电子股份有限公司 | Optocoupler driving capability test method and system |
| CN117054858A (en) * | 2023-10-11 | 2023-11-14 | 井芯微电子技术(天津)有限公司 | Three-state configuration pin implementation method and IO device in chip |
-
2021
- 2021-10-11 CN CN202122447900.9U patent/CN216646725U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115980502A (en) * | 2023-03-20 | 2023-04-18 | 宁波群芯微电子股份有限公司 | Optocoupler driving capability test method and system |
| CN117054858A (en) * | 2023-10-11 | 2023-11-14 | 井芯微电子技术(天津)有限公司 | Three-state configuration pin implementation method and IO device in chip |
| CN117054858B (en) * | 2023-10-11 | 2024-01-16 | 井芯微电子技术(天津)有限公司 | Three-state configuration pin implementation method and IO device in chip |
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