CN112444733B - Chip aging state detection method and device - Google Patents
Chip aging state detection method and device Download PDFInfo
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- CN112444733B CN112444733B CN202011251252.3A CN202011251252A CN112444733B CN 112444733 B CN112444733 B CN 112444733B CN 202011251252 A CN202011251252 A CN 202011251252A CN 112444733 B CN112444733 B CN 112444733B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/52—Testing for short-circuits, leakage current or ground faults
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The embodiment of the invention discloses a method and a device for detecting a chip aging state, which relate to the technical field of chip detection and are convenient for detecting the chip aging state caused by a TDDB effect. The method comprises the following steps: the output end of at least one power switch device on the chip is connected into a peak current detection circuit; supplying power to a control end of the power switch device, so that current flows to the output end through the control end; periodically acquiring a maximum leakage current from the output end by using the peak current detection circuit; and determining the chip aging state based on the maximum leakage current. The invention is suitable for chip aging test and monitoring occasions.
Description
Technical Field
The present invention relates to the field of chip detection technologies, and in particular, to a method and an apparatus for detecting an aging state of a chip.
Background
Many factors occur in chip burn-in, and it is generally considered that chip burn-in mainly includes burn-in phenomena caused by carrier injection (Hot-carrier injection, HCI), negative bias temperature instability (Negative bias temperature instability, NBTI), positive bias temperature instability (Positive bias temperature instability, PBTI), etc., and the chip burn-in effect or factor directly affects the threshold voltage (Threshold voltage, commonly referred to as Vth) of the device to affect the magnitude of the driving current generated by the device, thereby affecting the performance of the whole chip.
The inventors found in engineering practice that: also, a chip burn-in phenomenon caused by time lapse breakdown (Time dependent dielectric breakdown, abbreviated as TDDB in english) is different from the above-mentioned chip burn-in phenomenon, and the TDDB effect burn-in causes leakage current of the gate electrode of the device to become gradually large, so that the power switching characteristics of the last on-chip power device are completely lost.
Whereas conventional chip burn-in monitoring schemes are not suitable for monitoring or detecting the chip burn-in state caused by TDDB effects.
Disclosure of Invention
Therefore, the embodiment of the invention provides a method and a device for detecting the chip aging state, which are convenient for detecting the chip aging state caused by the TDDB effect.
In a first aspect, an embodiment of the present invention provides a method for detecting an aging state of a chip, where the method includes the steps of:
the output end of at least one power switch device on the chip is connected into a peak current detection circuit;
supplying power to a control end of the power switch device, so that current flows to the output end through the control end;
periodically acquiring a maximum leakage current from the output end by using the peak current detection circuit;
and determining the chip aging state based on the maximum leakage current.
With reference to the first aspect, in a first implementation manner of the first aspect, the determining a chip aging state based on the maximum leakage current includes:
converting the acquired maximum leakage current from analog quantity to digital quantity;
and quantitatively characterizing the aging state of the chip by using the obtained digital quantity.
With reference to the first aspect, the first or second implementation manner of the first aspect, in a third implementation manner of the first aspect, the determining the chip aging state based on the maximum leakage current includes:
converting the maximum leakage current into a pulse signal with a preset pulse width;
converting the pulse signal into a digital quantity;
and quantitatively representing the aging state of the chip by using the obtained digital quantity.
With reference to any one of the first to third implementation manners of the first aspect, in a fourth implementation manner of the first aspect, a supply voltage of the control terminal of the power switching device is consistent with an operating voltage of the chip.
In a second aspect, an embodiment of the present invention provides a device for detecting an aging state of a chip, including: the peak current detection circuit is connected with the peak current detection circuit;
the power supply is configured to be connected with a control end of the power switching device and is used for supplying power to the power switching device;
the peak current detection circuit is configured to be connected to an output end of at least one power switch device on a chip and is used for periodically acquiring the maximum leakage current flowing through the power switch device;
the comparison circuit is configured to be electrically connected with the peak current detection circuit, and is used for receiving the maximum leakage current periodically sent by the peak current detection circuit and determining the chip aging state based on the maximum leakage current.
With reference to the second aspect, in a first implementation manner of the second aspect, an analog-to-digital conversion module is disposed at an input end of the comparison circuit, and the analog-to-digital conversion module is configured to convert the obtained maximum leakage current from an analog quantity to a digital quantity, and output the digital quantity to the comparison circuit;
the comparison circuit is particularly used for quantitatively representing the aging state of the chip by using the obtained digital quantity.
With reference to the first or second implementation manner of the second aspect, in a third implementation manner of the second aspect, the device further includes a current timing conversion module, an input end of the current timing conversion module is connected to the output end of the peak current detection circuit, and an output end of the current timing conversion module is connected to the input end of the analog-to-digital conversion module;
the current timing conversion module is used for converting the maximum leakage current into a pulse signal with a preset pulse width and inputting the pulse signal into the analog-to-digital conversion module;
the analog-to-digital conversion module is used for converting the pulse signal into digital quantity;
and the comparison circuit is used for quantitatively representing the aging state of the chip by using the obtained digital quantity.
With reference to any one of the first to third embodiments of the second aspect, in a fourth embodiment of the second aspect, a supply voltage of the control terminal of the power switching device is consistent with an operating voltage of the chip.
The chip aging state detection method and device provided by the embodiment of the invention are characterized in that the output end of at least one power switch device on a chip is connected into a peak current detection circuit; supplying power to a control end of the power switch device, so that current flows to the output end through the control end; periodically acquiring a maximum leakage current from the output end by using the peak current detection circuit; and determining the chip aging state based on the maximum leakage current. The size of the leakage current of the power switch device can reflect the aging state of the chip, so that the chip aging state caused by the TDDB effect can be conveniently detected by the scheme.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a method for detecting an aging state of a chip according to an embodiment of the present invention;
FIG. 2 is a flowchart of a method for detecting an aging state of a chip according to another embodiment of the present invention;
FIG. 3 is a flowchart of a method for detecting a burn-in status of a chip according to another embodiment of the present invention
FIG. 4 is a circuit diagram of a device for detecting an aging state of a chip according to an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating an application of the device for detecting a burn-in status of a chip in FIG. 4;
FIG. 6 is a schematic diagram illustrating an apparatus for detecting a burn-in status of a chip according to another embodiment of the present invention;
fig. 7 is a schematic diagram illustrating an application of the device for detecting a burn-in status of a chip according to another embodiment of the invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The method and the device for detecting the chip aging state are suitable for chip aging test and monitoring occasions; for example, pre-factory chip testing, in-use chip monitoring, and the like. The method is particularly suitable for detecting the aging state of the chip caused by the TDDB effect.
Example 1
Referring to fig. 1 and 2, the method for detecting a chip aging state according to the present embodiment includes the steps of:
110. and the output end of at least one power switch device on the chip is connected into the peak current detection circuit.
In this embodiment, a plurality of power switching devices, such as MOS (Metal oxide semiconductor) tubes, are integrated on the chip, and the aging or good/bad status of the power switching devices reflects or determines the performance and status of the chip to a certain extent. Therefore, the burn-in of the chip is generally determined by detecting the state of the power switching device. For convenience of description and to help the reader, the following description will be made using the power switching device as a MOS transistor.
The MOS tube has a Gate (G pole for short), a Source (S pole for short) and a drain (D pole for short), wherein the Gate is generally a control terminal, the Source and the drain are output terminals, and leakage current flowing through the MOS tube flows from the Gate to the Source or the drain. When the device is connected, the grid electrode is directly or indirectly connected with a power supply, and is used for providing gate voltage for the conduction of the MOS tube and connecting the source electrode and the drain electrode with the input end of the peak current detection circuit.
According to engineering practice, the TDDB effect of the PMOS tube is at least one order of magnitude higher than the TDDB effect of the NMOS tube. That is, the state of the NMOS is more susceptible to TDDB than the state of the NMOS. Therefore, the detection method of the present embodiment is more suitable for detecting or monitoring the state of the NMOS.
The peak current detector circuit (Peak current detector, PCD for short) may be directly replaced by a peak current detector, commonly known as a detector or peak detector, which is used to periodically obtain useful information in the fluctuating signal and identify the presence or change of waves, oscillations or signals.
120. And supplying power to the control end of the power switch device to enable current to flow to the output end through the control end.
As described above, the gate voltage required for conduction is provided to the gate of the MOS transistor, so that current flows in the MOS transistor. During testing, a switch driving control circuit can be arranged between the grid electrode of the MOS tube and the power supply, so that the MOS tube is driven to be conducted through the switch driving control circuit every time detection is needed, the operation steps of connecting the power supply every time are omitted, and the detection procedure is convenient to simplify.
130. And periodically acquiring the maximum leakage current from the output end by using the peak current detection circuit.
In this embodiment, after the power switching device is connected to the apparatus required for detection, the Test mode is started, wherein test_en=1 is the Test mode, and test_en=0 is the compression mode (i.e. the non-Test state). The peak current detection circuit is used for periodically capturing and outputting the maximum leakage current generated by the power switch device during the test.
140. And determining the chip aging state based on the maximum leakage current.
In this embodiment, the implementation may be performed by a logic control circuit, or may be performed by a Processor (Central Processing Unit/Processor), a single chip microcomputer, or the like.
The specific implementation mode can be as follows: and presetting a standard current value, and comparing the captured maximum leakage current with the standard current value to determine the aging degree of the chip.
Specifically, the aging degree may also be quantitatively expressed according to the comparison result.
According to the chip aging state detection method provided by the embodiment of the invention, the output end of at least one power switch device on a chip is connected into a peak current detection circuit; supplying power to a control end of the power switch device, so that current flows to the output end through the control end; periodically acquiring a maximum leakage current from the output end by using the peak current detection circuit; and determining the chip aging state based on the maximum leakage current.
The size of the leakage current of the power switch device can reflect the aging state of the chip, so that the chip aging state caused by the TDDB effect can be conveniently detected by the scheme.
Referring to fig. 2, in some embodiments, step 140, determining the chip burn-in state based on the maximum leakage current includes the steps of:
141A, converting the obtained maximum leakage current from analog to digital.
In this embodiment, this may be implemented by an analog-to-digital converter.
142A, quantitatively characterizing the aging state of the chip by using the obtained digital quantity.
In this embodiment, the maximum leakage current is converted from an analog quantity to a digital quantity, so that the obtained digital quantity can quantitatively characterize the aging degree of the chip. Due to the fact that the chip aging degree is quantitatively represented, engineering technicians can determine further processing of the chip according to the aging degree. Such as discarding or repairing, and continuing use.
Referring to fig. 3, in other embodiments, step 140 of determining the chip burn-in state based on the maximum leakage current includes: 141B converting the maximum leakage current into a pulse signal of a predetermined pulse width; the maximum leakage current can be converted into a pulse signal with a certain pulse width by a current-to-time converter (Current to time converter, C2T).
142B, converting the pulse signal into a digital quantity; 143B, quantitatively characterizing the aging state of the chip by using the obtained digital quantity.
The conversion of the pulse signal into digital quantity can be realized by an analog-to-digital converter, if the maximum leakage current is monitored to be almost 0, the pulse width of the pulse signal output by conversion is almost 0, and 0 is output to represent that no aging caused by TDDB effect occurs. If the maximum leakage current value exceeds the standard current value, converting and outputting a pulse signal with the width larger than 0, and outputting a number larger than 0 to represent the aging degree caused by the TDDB effect. The larger the leakage current is, the larger the pulse signal width is, the larger the aging degree of the power switch device is, and the larger the performance of the corresponding chip is affected.
In order to ensure that the test result of the power switch device can truly represent the aging state of the chip, the power supply voltage of the control end of the power switch device is consistent with the working voltage of the chip during the test.
In addition, for the aging phenomenon caused by carrier injection (Hot-carrier injection, HCI), negative bias temperature instability (Negative bias temperature instability, NBTI), positive bias temperature instability (Positive bias temperature instability, PBTI), etc. described in the background art, the proposed conventional aging monitor circuit is mostly based on the frequency variation of some oscillators, but the influence of aging of the TDDB effect on the oscillator frequency is nonlinear, and thus, the conventional method is not well suited for monitoring the TDDB aging phenomenon.
According to the method for detecting the chip aging state, which is provided by the scheme, the degree of the chip aging caused by the TDDB effect is judged by measuring the maximum leakage current of the grid electrode of the power switch device and comparing the maximum leakage current intensity with the standard current, so that the aging state of the chip can be conveniently and accurately detected and quantitatively represented.
Example two
FIG. 4 is a circuit diagram of an embodiment of a device for detecting a burn-in status of a chip according to the present invention; fig. 5 is a schematic diagram of an embodiment of a chip burn-in status detection device according to the present invention. Referring to fig. 1, 4 and 5, the chip aging state detection device provided by the embodiment of the invention includes a comparison circuit, a peak current detection circuit and a power supply.
The power supply is configured to be connected with a control end of the power switching device and is used for supplying power to the power switching device.
The power supply voltage of the power supply is consistent with the working voltage of the chip.
The peak current detection circuit is configured to be connected to an output end of at least one power switching device on a chip and used for periodically acquiring the maximum leakage current flowing through the power switching device.
The comparison circuit is configured to be electrically connected with the peak current detection circuit, and is used for receiving the maximum leakage current periodically sent by the peak current detection circuit and determining the chip aging state based on the maximum leakage current.
The peak current detection circuit can directly adopt a peak detector. The comparator circuit may employ a comparator for comparing whether an input signal is higher than a given value, in this embodiment, comparing the maximum leakage current with a standard current value.
Referring to fig. 2 and 6, in some embodiments, the input end of the comparison circuit is provided with an analog-to-digital conversion module, and the analog-to-digital conversion module is used for converting the obtained maximum leakage current from an analog quantity to a digital quantity and outputting the digital quantity to the comparison circuit.
The comparison circuit is particularly used for quantitatively representing the aging state of the chip by using the obtained digital quantity.
It will be appreciated that the analog to digital conversion module and the comparator are sometimes integrated in a device, forming a device with a comparator and an analog to digital conversion module, such as an analog to digital converter with a comparator function; of course, a comparator with analog-to-digital conversion function is also possible.
Referring to fig. 3 and 7, in some embodiments, the apparatus further includes a current timing conversion module, an input end of the current timing conversion module is connected to the peak current detection circuit output end, and an output end of the current timing conversion module is connected to the analog-to-digital conversion module input end;
the current timing conversion module is used for converting the maximum leakage current into a pulse signal with a preset pulse width and inputting the pulse signal into the analog-to-digital conversion module;
the analog-to-digital conversion module is used for converting the pulse signal into digital quantity and outputting the digital quantity to the comparison circuit.
And the comparison circuit is used for quantitatively representing the aging state of the chip by using the obtained digital quantity.
The detection method of the first embodiment of the present invention may be, but is not limited to, implemented by the chip burn-in status detection device provided by the embodiment of the present invention, where the chip burn-in status detection device provided by the embodiment of the present invention is connected to at least one power switching device on a chip, and the chip burn-in status can be conveniently quantitatively determined based on the maximum leakage current by detecting the maximum leakage current flowing through the power switching device.
Therefore, the detection device is convenient for detecting the chip aging state caused by the TDDB effect.
It should be noted that, the scheme of the present embodiment and the first embodiment have corresponding specific technical features, and the specific technical scheme and technical effects are similar to those of the first embodiment, and the difference is that the detection method of the first embodiment may be implemented by hardware provided by the present embodiment, which includes but is not limited to.
For the embodiments provided by the invention, the technical scheme and the technical effect are basically the same, and the related parts can be seen from each other.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
In this specification, each embodiment is described in a related manner, and the same or similar parts of each embodiment are referred to each other, where each embodiment mainly describes differences from other embodiments.
For convenience of description, the above chip burn-in state detection apparatus is described as being functionally divided into various functional units/circuits/modules, respectively. Of course, the functions of the various elements/modules may be implemented in the same piece or pieces of software and/or hardware when implementing the present invention.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (6)
1. The method for detecting the aging state of the chip is characterized by being used for chip aging test and monitoring occasions, and comprises the following steps:
the output end of at least one power switch device on the chip is connected into a peak current detection circuit;
supplying power to a control end of the power switch device, so that current flows to the output end through the control end;
periodically acquiring a maximum leakage current from the output end by using the peak current detection circuit;
determining a chip aging state based on the maximum leakage current;
the determining the chip aging state based on the maximum leakage current includes: and comparing the captured maximum leakage current with a standard current value to determine the aging state of the chip.
2. The method of claim 1, wherein comparing the captured maximum leakage current to a standard current value, determining a chip burn-in state comprises: converting the maximum leakage current into a pulse signal with a preset pulse width;
converting the width of the pulse signal into a digital quantity according to the comparison result; and
and quantitatively representing the aging state of the chip by using the obtained digital quantity.
3. A method according to any one of claims 1 to 2, wherein the supply voltage at the control terminal of the power switching device corresponds to the operating voltage of the chip.
4. A chip burn-in status detection apparatus, comprising: the peak current detection circuit is connected with the peak current detection circuit;
the power supply is configured to be connected with a control end of the power switching device and is used for supplying power to the power switching device;
the peak current detection circuit is configured to be connected to an output end of at least one power switch device on a chip and is used for periodically acquiring the maximum leakage current flowing through the power switch device;
the comparison circuit is configured to be electrically connected with the peak current detection circuit, and is used for receiving the maximum leakage current periodically sent by the peak current detection circuit and determining the chip aging state based on the maximum leakage current;
the comparison circuit is specifically used for comparing the captured maximum leakage current with a standard current value to determine the chip aging state.
5. The device for detecting the aging state of the chip according to claim 4, further comprising a current timing conversion module, wherein an input end of the current timing conversion module is connected to an output end of the peak current detection circuit, and an output end of the current timing conversion module is connected to an input end of the analog-to-digital conversion module;
the current timing conversion module is used for converting the maximum leakage current into a pulse signal with a preset pulse width and inputting the pulse signal into the analog-to-digital conversion module;
the analog-to-digital conversion module is used for converting the width of the pulse signal into digital quantity;
the comparison circuit is used for outputting a digital quantity corresponding to the width of the pulse signal according to the comparison result;
and quantitatively representing the aging state of the chip by utilizing the output digital quantity.
6. The device for detecting a burn-in status of a chip according to any one of claims 4 to 5, wherein a supply voltage of the control terminal of the power switching device is identical to an operating voltage of the chip.
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