CN112420532B - 无引脚dfn封装器件的封装工艺 - Google Patents

无引脚dfn封装器件的封装工艺 Download PDF

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CN112420532B
CN112420532B CN202011403562.2A CN202011403562A CN112420532B CN 112420532 B CN112420532 B CN 112420532B CN 202011403562 A CN202011403562 A CN 202011403562A CN 112420532 B CN112420532 B CN 112420532B
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马磊
党鹏
杨光
彭小虎
王新刚
庞朋涛
任斌
王妙妙
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Xi'an Hangsi Semiconductor Co ltd
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Abstract

本发明公开了一种集成电路器件的封装工艺,所述器件包括位于环氧绝缘体中的散热焊盘、芯片和导电焊盘,所述芯片位于散热焊盘上;包括以下步骤:S1.先将硅微粉80份和阻燃剂10份与3‑氨基丙基三乙氧基硅烷2份混合均匀,进行表面处理;S2.再加入环氧树脂80份、线型酚醛树脂55份、液体丁腈橡胶16份、焦碳酸二乙酯8份、聚乙二醇单辛基苯基醚0.1份、醋酸丁酸纤维素5份、5‑氟‑2‑甲氧基苯胺2份、2,4,6‑三(二甲氨基甲基)苯酚5份和脱模剂3份,混合均匀。本发明方法制备得到的器件有效避免了气孔导致的导热性能降低进而引起电性方面的失效的问题,内部气孔的发生率低。

Description

无引脚DFN封装器件的封装工艺
技术领域
本发明属于半导体器件技术领域,尤其涉及一种无引脚DFN封装器件的封装工艺。
背景技术
随着电子产品向小型化方向发展,在手提电脑、CPU电路、微型移动通信电路(手机等)、数字音视频电路、通信整机、数码相机等消费类电子领域的大规模IC和VLSI(超大规模IC)应用电路中,要求半导体芯片的外形做得更小更薄; DFN是一种无引脚封装,呈正方形或矩形,封装底部中央位置有一个大面积裸露焊盘用来导热,围绕大焊盘的封装外围四周有实现电气连结的导电焊盘。由于DFN封装不像传统的SOIC与TSOP封装那样具有鸥翼状引线,内部引脚与焊盘之间的导电路径短,自感系数以及封装体内布线电阻很低,所以它能提供卓越的电性能,而得到广泛应用。
由于在封装过程中环氧树脂组成物流动性差或固化不均一,易导致内部的气体未被完全赶走而产生气孔,进而导致封装器件吸湿导致可靠性失效,且内部气孔的产生还可能会导致导热性能降低从而引起电性方面的失效或热量损耗。因此,如何提供一种导热性能好,内部气孔的发生率低的DFN封装器件,成为本领域技术人员努力的方向。
发明内容
本发明目的在于提供一种无引脚DFN封装器件的封装工艺,该封装工艺得到的集成电路芯片内部气孔的发生率低,有效避免了气孔导致的导热性能降低进而引起电性方面的失效的问题。
为达到上述目的,本发明采用的技术方案是:一种无引脚DFN封装器件的封装工艺,所述器件包括位于环氧绝缘体中的散热焊盘、芯片和导电焊盘,所述芯片位于散热焊盘上,位于散热焊盘周边设有若干个导电焊盘,所述导电焊盘和芯片通过一引线连接;
所述散热焊盘的中央区开有一供芯片嵌入的沉槽,从而在散热焊盘的边缘区形成一围堰部,所述沉槽的底部和围堰部与芯片的下表面和侧壁之间均设置有银浆层,所述沉槽的底部开有若干个延伸至散热焊盘内的换热盲孔,所述换热盲孔中具有银浆填充部;
所述环氧绝缘体的原料的制备方法包括以下步骤:
S1. 先将硅微粉80份和阻燃剂10份与3-氨基丙基三乙氧基硅烷2份混合均匀,进行表面处理;
S2. 再加入环氧树脂80份、线型酚醛树脂55份、液体丁腈橡胶16份、焦碳酸二乙酯8份、聚乙二醇单辛基苯基醚0.1份、醋酸丁酸纤维素5份、5-氟-2-甲氧基苯胺2份、2,4,6-三(二甲氨基甲基)苯酚5份和脱模剂3份,混合均匀;
S3. 将混合物于90~110℃混炼3~5分钟,产物冷却后粉碎过筛,以上份数均为重量份。
上述技术方案中进一步改进的技术方案如下:
1. 上述方案中,所述换热盲孔为锥形盲孔,所述换热盲孔靠近芯片一端端口的孔径大于换热盲孔远离芯片一端端口的孔径。
2. 上述方案中,所述脱模剂选自硬脂酸、硬脂酸盐或者氧化聚乙烯蜡中的至少一种。
3. 上述方案中,所述阻燃剂为硼酸盐和/或钼酸盐。
4. 上述方案中,步骤S3中,混炼温度为100℃。
由于上述技术方案的运用,本发明与现有技术相比具有下列优点:
1、本发明无引脚DFN封装器件的封装工艺,其在散热焊盘的中部开设与芯片匹配的沉槽,从而使得在贴装芯片时,工作人员将银浆置于沉槽中,并将对应的芯片安装进沉槽即可;此时,芯片下部嵌于沉槽中,不仅其底部能够通过形成的银浆层与沉槽底部粘结,芯片下部的侧壁也能与沉槽外部的围堰部的内壁通过银浆层相互粘结,不仅芯片与银浆层的接触面积有所增加,而且银浆层与散热焊盘的接触面积也有所增加,从而使得单位时间内,更多的热量在芯片与银浆层之间、银浆层与散热焊盘之间传导,进而改善DFN封装半导体器件的散热效果。
2、本发明无引脚DFN封装器件的封装工艺,在散热焊盘的中央区设置有沉槽,能方便工作人员校准芯片的安装位置,实现芯片的精确安装,提高芯片封装质量;同时,将芯片嵌装于沉槽中,能够定位芯片位置,配合银浆的设置保护芯片和与芯片连接的引线,提高封装质量;此外,沉槽底部开设换热盲孔,换热盲孔的设置能够容纳部分银浆,避免多余的银浆溢出沉槽,待换热盲孔中具有银浆填充部后,银浆与散热焊盘的接触面积进一步增加,封装散热效果得到进一步的提升。
3、本发明无引脚DFN封装器件的封装工艺,其环氧绝缘体配方在环氧树脂体系中加入了液体丁腈橡胶,采用2,4,6-三(二甲氨基甲基)苯酚作为固化促进剂,并额外添加了焦碳酸二乙酯和5-氟-2-甲氧基苯胺,提高了固化物的交联密度,从而增强了环氧绝缘体的整体力学性能,有效保证了制得DFN封装器件结构稳定性。
4、本发明无引脚DFN封装器件的封装工艺,其环氧绝缘体配方采用环氧树脂80~100份和线型酚醛树脂,并添加聚乙二醇单辛基苯基醚和醋酸丁酸纤维素,降低了树脂体系与无机填料间的相互作用力,显著改善了组合物的流动性,能够有效降低封装后内部气孔的发生率,避免了气孔导致的导热性能降低进而引起电性方面的失效的问题,提高了封装成品率。
附图说明
附图1为本发明集成电路器件的结构示意图;
附图2为附图1的局部结构示意图。
以上附图中:1、散热焊盘;11、沉槽;12、围堰部;121、阶梯部;13、换热盲孔;2、银浆层;21、银浆填充部;3、芯片;4、导电焊盘;5、引线;6、环氧绝缘体。
具体实施方式
下面结合实施例对本发明作进一步描述:
实施例:一种无引脚DFN封装器件的封装工艺,所述高导热DFN封装器件包括位于环氧绝缘体6中的散热焊盘1、芯片3和导电焊盘4,所述芯片3位于散热焊盘1上,位于散热焊盘1周边设有若干个导电焊盘4,所述导电焊盘4和芯片3通过一引线5连接;
所述散热焊盘1的中央区开有一供芯片3嵌入的沉槽11,从而在散热焊盘1的边缘区形成一围堰部12,所述沉槽11的底部和围堰部12与芯片3的下表面和侧壁之间均设置有银浆层2,所述沉槽11的底部开有若干个延伸至散热焊盘1内的换热盲孔13,所述换热盲孔13中具有银浆填充部21;
上述换热盲孔13为锥形盲孔,上述换热盲孔13靠近芯片3一端端口的孔径大于换热盲孔13远离芯片3一端端口的孔径;
上述环氧绝缘体6的原料的制备方法包括以下步骤:
S1. 先将硅微粉80份和阻燃剂10份与3-氨基丙基三乙氧基硅烷2份混合均匀,进行表面处理;
S2. 再加入环氧树脂80份、线型酚醛树脂55份、液体丁腈橡胶16份、焦碳酸二乙酯8份、聚乙二醇单辛基苯基醚0.1份、醋酸丁酸纤维素5份、5-氟-2-甲氧基苯胺2份、2,4,6-三(二甲氨基甲基)苯酚5份和脱模剂3份,混合均匀;
S3. 将混合物于90~110℃混炼3~5分钟,产物冷却后粉碎过筛,以上份数均为重量份。
上述脱模剂为硬脂酸,阻燃剂为硼酸盐。
对比例1~3:一种环氧绝缘体,原料包括以下重量份组分:
表1
Figure DEST_PATH_IMAGE002A
对比例1中的脱模剂为硬脂酸,阻燃剂为硼酸盐;对比例2中的脱模剂为硬脂酸盐,阻燃剂为硼酸盐;对比例3中的脱模剂为氧化聚乙烯蜡,阻燃剂为钼酸盐。
制备工艺方法同实施例。
上述实施例和对比例1~3制得的环氧绝缘体的性能如表2所示:
表2
Figure 244054DEST_PATH_IMAGE003
各实施例和对比例中,环氧绝缘体的成型条件均为:模具温度180℃,注射压力700kg/cm2,固化时间2min。
如表2 的评价结果所示,各实施例中的环氧绝缘体无论是整体力学性能还是流动性均优于各对比例,用于DFN封装器件中能够保证封装结构稳定性,降低封装后内部气孔的发生率,提高封装成品率。
上述实施例只为说明本发明的技术构思及特点,其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施,并不能以此限制本发明的保护范围。凡根据本发明精神实质所作的等效变化或修饰,都应涵盖在本发明的保护范围之内。

Claims (5)

1.一种无引脚DFN封装器件的封装工艺,其特征在于:所述器件包括位于环氧绝缘体(6)中的散热焊盘(1)、芯片(3)和导电焊盘(4),所述芯片(3)位于散热焊盘(1)上,位于散热焊盘(1)周边设有若干个导电焊盘(4),所述导电焊盘(4)和芯片(3)通过一引线(5)连接;
所述散热焊盘(1)的中央区开有一供芯片(3)嵌入的沉槽(11),从而在散热焊盘(1)的边缘区形成一围堰部(12),所述沉槽(11)的底部和围堰部(12)与芯片(3)的下表面和侧壁之间均设置有银浆层(2),所述沉槽(11)的底部开有若干个延伸至散热焊盘(1)内的换热盲孔(13),所述换热盲孔(13)中具有银浆填充部(21);
所述环氧绝缘体(6)的原料的制备方法包括以下步骤:
S1. 先将硅微粉80份和阻燃剂10份与3-氨基丙基三乙氧基硅烷2份混合均匀,进行表面处理;
S2. 再加入环氧树脂80份、线型酚醛树脂55份、液体丁腈橡胶16份、焦碳酸二乙酯8份、聚乙二醇单辛基苯基醚0.1份、醋酸丁酸纤维素5份、5-氟-2-甲氧基苯胺2份、2,4,6-三(二甲氨基甲基)苯酚5份和脱模剂3份,混合均匀;
S3. 将混合物于90~110℃混炼3~5分钟,产物冷却后粉碎过筛,以上份数均为重量份。
2.根据权利要求1所述的无引脚DFN封装器件的封装工艺,其特征在于:所述换热盲孔(13)为锥形盲孔,所述换热盲孔(13)靠近芯片(3)一端端口的孔径大于换热盲孔(13)远离芯片(3)一端端口的孔径。
3.根据权利要求1所述的无引脚DFN封装器件的封装工艺,其特征在于:所述脱模剂选自硬脂酸、硬脂酸盐或者氧化聚乙烯蜡中的至少一种。
4.根据权利要求1所述的无引脚DFN封装器件的封装工艺,其特征在于:步骤S3中,混炼温度为100℃。
5.根据权利要求1所述的无引脚DFN封装器件的封装工艺,其特征在于:所述阻燃剂为硼酸盐和/或钼酸盐。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070025566A (ko) * 2005-09-02 2007-03-08 엘에스전선 주식회사 함몰부가 형성된 다이패드를 구비한 리드프레임 및반도체 패키지
TW200712089A (en) * 2005-07-05 2007-04-01 San Apro Ltd Epoxy resin composition for sealing up optical semiconductor
CN102191002A (zh) * 2011-04-02 2011-09-21 烟台德邦科技有限公司 一种耐高湿高热单组分环氧胶粘剂及其制备方法
CN102612744A (zh) * 2009-09-08 2012-07-25 克里公司 具有导热通路的电子器件基座和包括该基座的发光器件
CN104673111A (zh) * 2014-06-30 2015-06-03 广东丹邦科技有限公司 环氧树脂基各向异性导电胶膜的配方及制备方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07242733A (ja) * 1994-03-05 1995-09-19 Toshiba Chem Corp エポキシ樹脂組成物および半導体封止装置
JPH10116940A (ja) * 1996-10-09 1998-05-06 Toshiba Corp 樹脂封止型半導体装置及びその製造方法
JP2001081286A (ja) * 1999-09-13 2001-03-27 Sumitomo Bakelite Co Ltd 半導体用樹脂ペースト及びそれを用いた半導体装置
JP3420153B2 (ja) * 2000-01-24 2003-06-23 Necエレクトロニクス株式会社 半導体装置及びその製造方法
US8828806B2 (en) * 2009-06-01 2014-09-09 Shin-Etsu Chemical Co., Ltd. Dam composition for use with multilayer semiconductor package underfill material, and fabrication of multilayer semiconductor package using the same
WO2014167993A1 (ja) * 2013-04-11 2014-10-16 東洋紡株式会社 熱伝導性樹脂組成物およびそれを使用した熱伝導性封止体
JP6427974B2 (ja) * 2013-06-21 2018-11-28 住友ベークライト株式会社 半導体封止用樹脂組成物および半導体装置
CN104497490B (zh) * 2014-12-22 2017-08-25 科化新材料泰州有限公司 用于全包封器件的高导热环氧树脂组合物及其制备方法
CN105440588B (zh) * 2015-12-24 2017-11-03 江苏中鹏新材料股份有限公司 一种高导热模塑型环氧底填料及其制备方法与用途
JP6332488B2 (ja) * 2017-01-30 2018-05-30 日立化成株式会社 液状エポキシ樹脂組成物の選択方法及び製造方法、並びに電子部品装置及びその製造方法
CN206864460U (zh) * 2017-04-27 2018-01-09 江苏长电科技股份有限公司 一种防止芯片溢胶的封装结构
US10079198B1 (en) * 2017-05-31 2018-09-18 Stmicroelectronics, Inc. QFN pre-molded leadframe having a solder wettable sidewall on each lead

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200712089A (en) * 2005-07-05 2007-04-01 San Apro Ltd Epoxy resin composition for sealing up optical semiconductor
KR20070025566A (ko) * 2005-09-02 2007-03-08 엘에스전선 주식회사 함몰부가 형성된 다이패드를 구비한 리드프레임 및반도체 패키지
CN102612744A (zh) * 2009-09-08 2012-07-25 克里公司 具有导热通路的电子器件基座和包括该基座的发光器件
CN102191002A (zh) * 2011-04-02 2011-09-21 烟台德邦科技有限公司 一种耐高湿高热单组分环氧胶粘剂及其制备方法
CN104673111A (zh) * 2014-06-30 2015-06-03 广东丹邦科技有限公司 环氧树脂基各向异性导电胶膜的配方及制备方法

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