1297942 九、發明說明： 【發明所屬之技術領域】 一種嵌埋半導體晶片之承載板結構，尤指一種將半導 體嵌埋於承載板中之結構。 【先前技術】 隨著半導體封裝技術的演進，半導體裝置 (Semiconductor device)已開發出不同的封裝型態，其主要 係在一封裝基板（package substrate)或導線架上先裝置半 _導體晶片，再將半導體晶片電性連接在該封裝基板或導線 架上，接著以膠體進行封裝；其中球柵陣列式（Ball grid array, BGA)為一種先進的半導體封裝技術，其特點在於採 用一封裝基板來安置半導體晶片’並利用自動對位 (Self-alignment)技術以於該封裝基板背面植置多數個成柵 狀陣列排列之錫球（Solder ball)，使相同單位面積之半導體 晶片承載件上可以容納更多輸入/輸出連接端（I/O • connection)以符合高度集積化（Integration)之半導體晶片 所需，以藉由此些錫球將整個封裝單元銲結並電性連接至 外部裝置。 惟傳統半導體封裝結構是將半導體晶片黏貼於基板 頂面，進行打線接合（wirebonding)或覆晶接合（Flip chip) 封裝，再於基板之背面植以錫球以進行電性連接，如此’ 雖可達到高腳數的目的，但是在更高頻使用時或高速操作 時，其將因導線連接路徑過長導致阻抗增加，使電氣特性 之效能無法提昇，而有所限制。 5 19432 1297942 以鑑於此，為了能有效地提昇電性品質而符合下世代 產品之應用，業界紛紛研究採用將晶片埋入電路板内，作 直接的電性連接，來縮短電性傳導路徑，並減少訊號損失、 訊號失真及提昇在高速操作之能力。 習知嵌埋半導體晶片之電路板之製法流程圖如第1A 至ID圖所示，首先提供一承載板1〇，該承載板ι〇且有第 一表面10a及與該第一表面相對之第二表面1〇b,而該承 載板10係為絕緣板、金屬板或完成前段線路製程之單層或 •多層電路板，且於該承載板10中形成至少一貫穿之開口 100(如第1A圖所示）；接著將至少一具有複數電極墊 之半導體晶片11置於該承載板1〇之開口 1〇〇中（如第ib 圖所不），得於該承載板10之第二表面1〇b形成有一具黏 性且後績可移除之黏著板（圖式中未表示）；於該承載板ι〇 之開口 100中填充黏著材料12並經固化（Curing)製程以 將该半導體晶片11固定於該承載板1〇之開口 1〇〇中（如 ⑩第1C圖所不）；之後於該承載板1〇之第一及第二表面 l〇a、10b進行線路增層製程，以於該承載板1〇之第一及 第二表面10a、l〇b分別依序形成至少一第一介電層13a 及第二介電層13b，並於該第一及第二介電層13a,13b表面 分別形成第一及第二線路層14a與14b，且該線路層14a 係透過形成於该第一介電層丨3a中的導電盲孔14〇以電性 連接至該半導體晶片11之電極墊110，又該承載板10中 形成有電鍍導通孔142以電性連接該第一及第二線路層 14a與14b (如第1D圖所示）。 6 19432 1297942 之制=閱弟2圖’又另—習知嵌埋半導體晶片之電路板 之衣法係於一承載板10中形成至少一未貫穿之開口 ::，接著將至少-具有電極墊11〇之半導體晶片 = 中，並於該開σ1⑽，中填充黏著材料 =订固化製程以將該半導體晶片u固定於該開口1〇〇， 之後㈣承餘Η)之表㈣行㈣增層製程以形 括至少一介電層13及線路層14 路層係透過形成於該介以結構，且該線 性連接至該半導體晶片11之電極墊110。 依上習知述製程所製成之嵌 雖可縮短電性傳導轉，並減少之電路板 曰各一 札就才貝失、訊號矣直菸担 汁在南頻運作之能力以克服習知半導體 ς棱 表面之種種缺失。然，上述習知 2 1路板 上下尺寸相同的垂直開m 係於承載板中形成 該承載板之開口中。 ’於將該半導體晶片置放在 由於該半二:::::係直接於該開σ中填充黏著材料， 材料注入該細：時為狹小的直細縫’當黏著 料填滿’進而使得該能完，著材 留空氣而於後續熱猶環製程 現:均勾’且易殘 續製程信賴性。 生々板現象，嚴重影響後 千古以及’習知製程中係於承载板中形成上下尺 垂直之開口，由於熱膨脹係 &成上下尺寸相同的 於開口中並進行後鱗枚％ m ，虽该半導體晶片接置 進仃^之熱循環製程產生熱勝脹效應時，該 19432 7 1297942 半導體晶片之邊緣容易辱P弓、息 、 场又開口邊緣的擠壓而受損；或是丰 導體晶片主動面周緣i開口用絲 水"開口周緣因應力過大，而造成 線路增層製程所用之絕緣厣盥 、 琢喈興開口周緣產生分層現象，進 而影響電路板嵌埋晶片之品質。 因此，如何提出一種新的嵌埋半導體晶片之電路板結 構’以避免習知㈣於將該半導體晶片放置於電路板之垂 ΪΓ 口I’ 不均勻’且易殘留氣泡，容易因熱膨脹所 產生之應力損傷半導I#曰y V,. V體日日片，或半導體晶片周緣與開口 緣應力過大而不利德續綠&在 W设1線路增層製程問題，實已成為業者 急欲解決之課題。 【發明内容】 曰¥於上述習知技術之種種缺點，本發明之主要目的在 於提供-㈣埋半導體晶4之承載板結構，得利於將半導 體曰曰片接置於该承载板之開口中。 本毛明之又-目的在於提供—種鼓埋半導體晶片之 承載板結構’得利於將黏著材料充填於承載板之開口中， 以避免於該開口中殘留*氣。 、本毛月之再目的在於提供一種嵌埋半導體晶片之 承載板結構，得避免熱應力影響嵌埋於承載板中之半導體 本毛明之再-目的在於提供—種嵌埋半導體晶片之 承載板結構，得避免何體晶片周緣與開口周緣應力過大 而不利後續線路增層製程問題。 為達上述及其他目的，本發明提出一種嵌埋半導體晶 19432 8 1297942 片之承載板結構，係包括：_承載板，係具第一表面及相 對之第二表面，且該承載板具有至少一具導角之開口 ；至 )半導體晶片，係接置於該開口巾，該半導體晶片具有 主動面及相對之非主動面，且該半導體晶片之主動面具有 複數電極墊；以及黏著材料，係填充於該開口與該半導體 晶片之間的間隙中。 、於本發明之一貫施例中，上述具導角之開口係貫穿該 承載板之第一及第二表面，而該導角係為全導角或半導 籲角。本實施例之嵌埋半導體晶片之承載板結構復包括一第 一介電層係形成於該承载板之第一表面及該半導體晶片之 ^動面，以及第二介電層係形成於該承載板之第二表面及 該半導體晶片之非主動面。χ本實施例之嵌埋半導體晶片 之承載板結構復包括一形成於該第一及第二介電層表面所 組成群組其中一者之線路增層結構，且該線路增脣結構中 形成有複數個導電結構以電性連接至該半導體晶片，而該 _線路增層結構表面形成有複數電性連接墊。 相較於習之技術，本發明之嵌埋半導體晶片之承载板 結構係形成具有導角之開口，因而可利於將該半導體晶片 接置於該承載板之開口中，且可藉由該導角以將該黏著材 料均勻且充足的填充於該開口中，以避免於該承載板之開 口中殘留空氣，並可避免熱膨脹係數不同所產生之 而影響該半導體晶片。 心力 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 9 19432 1297942 式，热悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 第3A至3E圖所示者係為本發明之嵌埋半導體晶片之 承載板結構第一實施例之製法流程。 如第3A圖所示，首先，提供一具有第一表面2〇a及 與該第一表面相對之第二表面2〇b之承載板2〇，於該承載 板2〇中形成有至少一具導角21〇之開口 21，且該開口 係，或矩形，又該開口 21係貫穿該承載板2〇之第一 • 士第二表面20a及施，而該導角21〇係為全導角。於本 貝加例中，5亥開口 21係採用切割、衝壓、雷射等其中之一 成型方式形成者。 八 本實施例中，係於該承载板2〇中形成具導角21〇之 開：2卜因而在後續製程中，可藉由該導角以順利^ 該半導體晶片22接置於該開口 21中。 如第3B圖所示，將至少一半導體晶片^置放於該择 ，口 21巾’得於該承載板2〇之第二表面规开)成有一具赛 可移除之㈣板（圖式中未表示），該半導體晶片 2係八有一主動面22a及與該主動面相對之非主動面 22b’且該半導體晶片22之主動面仏具有多數電極墊 220。於本實施例中，該半導體晶片22係以其非主動面⑵ 置放於該開口 21令。 如第3C圖所示，而後於㈣口 21與該半導體晶片r 之間之間隙中填充例如樹脂材料或膠體等黏著材m，並 經固化（CUring)而將半導體晶片22固定於該開口 21中。 19432 10 1297942 本實施例中，由於該開口 21具有導角21〇，使該開口 2i 與半導體晶片22之間的間隙呈上大下小之漏斗狀，俾使該 黏著材料23可順利引流入該開口 21中，並且確實填充在 該，口 中，以避免於該開口 21中殘留空氣導致後續熱 楯％製程中發生爆板現象。又本實施例中，由於該開口以 係具有導角210，不僅得使該黏著材料23均勻充填，且該 半導體晶片22之邊緣與該開口 21具以導角21〇之邊緣有 較大的間距，而可避免熱膨脹係數不同所產生的熱應力導 籲致該半導體晶片22之邊緣受開口 21邊緣的擠壓而受損、. 或是避免半導體晶片22周緣與開口 21周緣應力過大而不 利後續線路增層製程問題。 如第3D圖所示，於該承載板2〇之第一表面2〇a及唁 半導體晶片22之主動面22a形成一第一介電層24，且^/ 該承載板20之第二表面20b及該半導體晶片22之非主動 面22b形成一第二介電層25。該第—及第二介電層2425 中係分別形成有複數開孔240以露出該半導體晶片， 極墊220。該第一及第二介電層24,25係可例：為環氧:電 脂（£卩〇又)^代5111)、聚乙醯胺（？〇13^11^(^)、氰脂（〇乂&111; ester)、玻璃纖維（Glass fiber)、雙順丁烯二酸醯亞胺/三氮 拼（BT，Bismaleimide triazine)、聚丙稀（pp， polypropylene )、ΑΒΓ或混合環氧樹脂與玻璃纖維 所構成。 、貝 如第3E圖所示’之後’復可於該第—介電層以及 二介電層25表面形成-線路增層結構26,而言亥線路增層 19432 11 1297942 加，以H;l $層26G '#置於該介電層上之線路層 電社構介電層中之導電結構262,且該部份導 電性連接至該半導體晶片22之電姉22〇，並 兮二線路增層結構26表面形成有電性連接塾加，且位於 由：電層24及第二介電層25表面之線路增層結構26 係錯由至少一電鍍導通孔29作電性連接。 此外，該線路增層結構26表面復形成有一防焊層28, ^亥防焊層中具有複數個開孔，俾以顯露該線路增層 、、、。構表面之電性連接墊263。 請參閱第4圖，係為本發明之另一實施例，上述之開 口 21的導角210,亦可為半導角（係為未將開口 21完全斜 切，而使其開口形成部分斜切，部分垂直之型態），同樣可 達利於將該半導體晶片22置於該開口 21中，且可便於將 該黏著材料23充填於該開口 21中，並可避免產生氣泡， 以及避免熱應力而影響該半導體晶片22之邊緣受開口 21 鲁邊緣的擠壓而受損；或是避免半導體晶片22周緣與開口 21周緣應力過大而不利後續線路增層製程問題。 透過上述製法所形成之嵌埋半導體晶片之承載板結 構係包括：一承載板2〇，至少一具導角21〇之開口 21、至 少一半導體晶片22以及黏著材料23。該承載板20係具有 第一表面20a及與該第一表面2〇a相對之第二表面20b， 且該承載板20中形成有至少一具導角2丨〇之開口 2丨；其 中’該開口 21係貫穿該承載板2〇之第一表面20a及第二 表面20b，且該導角210係為全導角或半導角。該半導體 12 19432 1297942 晶片22係接置於該開口 21中，且該半導體晶片22具有— 主動面22a及與該主動面相對之非主動面2凡，且該主動 面22a具有多數電極墊22〇。該黏著材料23係填充於該開 口 21與3半‘體晶片22之間的間隙中，以將該半導體晶 片22固定於該開口 21中。 於本實施例中，該嵌埋半導體晶片之承載板結構復包 括一形成於該承載板20之第一表面、及該半導體晶片 22之主動面22a之弟一介雷展94，. 癱 冤層24’以及一形成於該承載板 籲2—0之弟二表面鳩及該半導體晶片^之非主動面咖之 =介電層25;又於該第一介電層Μ及第二介電 面^有祕增層結構26，又料路增層結構㈣ :成有-防焊層28,且該防焊層28中具有複數個開孔 .伽，俾以顯露該線路增層結構表面之電性連接塾加。 本發明之嵌埋半導體晶Η 載板中形成至少-具導角之載板結構，主要係於承 口之導备^ (如開口 21)，藉由該開 ¥角，可利於將該半導體晶片接置於該開口中。 此外，本發明，可雜士 可利於將黏著材料均勾之導角有如漏斗狀’俾 得避免•中因該板之開…而 包含氣泡，導致後續熱循”程及填充量不足而 影響後續製歸馳。 I生爆板的現象’嚴重 再者’本發明中由於 半導體晶片之邊緣與該開 =口係具有導角，使該 免熱膨脹係數不同所產=有較大的間距，而可避 的熱應力導致該半導體晶片之邊 19432 13 1297942 . 緣叉開口邊緣的擠壓而受損。 上再者，本發明中由於承載板之開口係具有導角，避免 =半導體晶片之邊緣與該開口周緣因應力過大，而造成 /、、1線路增層製粒所用之絕緣層與開口周緣產生分層現 上述實施例僅為例示性說明本發明之原理及苴功 而非用於限制本發明。任何熟習此項技藝之I士均可 在不違背本發明之精神及範疇 與變仆。. 對上述貫施例進行修飾 衷w W匕’柄明之權利保護範目，應如後述之申喑 專利範圍所列。 欠、·^甲明 【圖式簡單說明】 圖；M 1A至1D圖係為習知嵌埋半導體晶片之製法流程 第2圖係為習知欲埋半導體 弟3 A至3 E圖係顯示本發明 籲板結構第一實施例之製法流程圖 晶片之另一結構剖視圖； 之嵌埋半導體晶片之承 ;以及 導體晶片之承载板的1297942 IX. Description of the Invention: [Technical Field of the Invention] A carrier board structure in which a semiconductor wafer is embedded, in particular, a structure in which a semiconductor body is embedded in a carrier board. [Prior Art] With the evolution of semiconductor packaging technology, semiconductor devices have developed different package types, mainly by mounting a semi-conductor wafer on a package substrate or a lead frame. The semiconductor wafer is electrically connected to the package substrate or the lead frame, and then encapsulated by a colloid; wherein a ball grid array (BGA) is an advanced semiconductor packaging technology, which is characterized by using a package substrate to be disposed. The semiconductor wafer' uses a self-alignment technique to deposit a plurality of solder balls arranged in a grid array on the back surface of the package substrate, so that the semiconductor wafer carrier of the same unit area can be accommodated. A multi-input/output connection (I/O • connection) is required to conform to a highly integrated semiconductor wafer to solder and electrically connect the entire package unit to an external device by means of the solder balls. However, in the conventional semiconductor package structure, the semiconductor wafer is adhered to the top surface of the substrate, and a wire bonding or Flip chip package is applied, and then a solder ball is implanted on the back surface of the substrate to electrically connect, so that The purpose of achieving a high number of feet, but in the case of higher frequency use or high speed operation, the impedance will increase due to the long connection path of the wire, so that the performance of the electrical characteristics cannot be improved, and there is a limit. 5 19432 1297942 In view of this, in order to effectively improve the electrical quality and meet the application of the next generation of products, the industry has studied the use of the chip embedded in the circuit board for direct electrical connection to shorten the electrical conduction path, and Reduce signal loss, signal distortion and improve the ability to operate at high speeds. A method for manufacturing a circuit board embedding a semiconductor wafer is as shown in FIGS. 1A to 1D. First, a carrier board 1 is provided. The carrier board has a first surface 10a and a first surface opposite to the first surface. The two surfaces 1〇b, and the carrier board 10 is an insulating board, a metal board or a single layer or a multi-layer circuit board that completes the front-end circuit process, and at least one opening 100 is formed in the carrier board 10 (such as the 1A). The semiconductor wafer 11 having a plurality of electrode pads is then placed in the opening 1 of the carrier plate 1 (as shown in FIG. ib), and the second surface 1 of the carrier 10 is obtained. 〇b forms a viscous and removable adhesive sheet (not shown); the adhesive material 12 is filled in the opening 100 of the carrier 〇 and cured to form the semiconductor wafer 11 is fixed in the opening 1〇〇 of the carrier board 1 (as shown in FIG. 1C); then the line layering process is performed on the first and second surfaces 10a, 10b of the carrier board 1 Forming at least one of the first and second surfaces 10a, 10b of the carrier plate 1 in sequence a dielectric layer 13a and a second dielectric layer 13b, and first and second circuit layers 14a and 14b are formed on the surfaces of the first and second dielectric layers 13a, 13b, respectively, and the circuit layer 14a is formed through the channel layer 14a The conductive vias 14 in the first dielectric layer 3a are electrically connected to the electrode pads 110 of the semiconductor wafer 11, and the plating vias 142 are formed in the carrier 10 to electrically connect the first and second electrodes. Circuit layers 14a and 14b (as shown in Figure 1D). 6 19432 1297942 system = reading brother 2 Figure 'again — the conventional method of embedding a semiconductor wafer circuit board is formed in a carrier plate 10 to form at least one non-penetrating opening::, then at least - with electrode pads 11〇 semiconductor wafer = medium, and in the opening σ1 (10), filled with adhesive material = order curing process to fix the semiconductor wafer u to the opening 1 〇〇, then (4) bearing Η) table (four) line (four) layering process The at least one dielectric layer 13 and the wiring layer 14 are formed in the via structure, and the electrode pad 110 is linearly connected to the semiconductor wafer 11. The embedding made according to the conventional process can shorten the electrical conduction, and reduce the ability of the circuit board to be lost, and the ability of the signal to operate in the south frequency to overcome the conventional semiconductor edge. The variety of surfaces is missing. However, the vertical opening m of the above-mentioned conventional 1 1 board has the same upper and lower dimensions, and is formed in the opening of the carrying board to form the carrying board. 'Placing the semiconductor wafer in the semi-two::::: system is directly filled with the adhesive material in the opening σ, and the material is injected into the fine: a narrow straight slit 'when the adhesive fills up' This can be finished, the material is left in the air and the subsequent heat is still ringing the process: both hooks and easy to survive the process reliability. The slab phenomenon, which seriously affects the post-Equatorial and the conventional process, forms an opening perpendicular to the upper and lower slabs in the carrier plate, because the thermal expansion system & is the same size in the opening and the rear scale is % m, although the semiconductor When the thermal cycling process of the wafer is placed in a thermal cycling process, the edge of the 19432 7 1297942 semiconductor wafer is easily damaged by the squeezing of the bow, the interest, and the open edge of the field; or the active surface of the conductive wafer The edge of the i-opening of the silk water " the periphery of the opening due to excessive stress, resulting in the insulation of the line build-up process, the edge of the opening edge of the Zhaoxing opening, which affects the quality of the embedded chip of the board. Therefore, how to propose a new circuit board structure for embedding a semiconductor wafer 'to avoid the conventional (4) placing the semiconductor wafer on the circuit board, the nozzle I' is not uniform and easy to remain bubbles, which is easily caused by thermal expansion. Stress damage semi-conducting I#曰y V,. V body day film, or semiconductor wafer peripheral edge and opening edge stress is too large, but Lide continued green & In the W set 1 line build-up process, it has become an urgent solution The subject. SUMMARY OF THE INVENTION In view of the above disadvantages of the prior art, the main object of the present invention is to provide a carrier substrate structure of the (four) buried semiconductor crystal 4, which facilitates the attachment of the semiconductor wafer to the opening of the carrier. The purpose of the present invention is to provide a carrier structure for burying a semiconductor wafer, which is advantageous for filling the adhesive material in the opening of the carrier to avoid residual gas in the opening. The second objective of the present invention is to provide a carrier structure for embedding a semiconductor wafer, which avoids thermal stress and affects the semiconductor embedded in the carrier. The purpose of the present invention is to provide a carrier structure for embedding a semiconductor wafer. It is necessary to avoid excessive stress on the periphery of the wafer and the periphery of the opening, which is disadvantageous for the subsequent line build-up process. To achieve the above and other objects, the present invention provides a carrier structure for embedding a semiconductor crystal 19432 8 1297942, comprising: a carrier plate having a first surface and an opposite second surface, and the carrier has at least one a semiconductor wafer, the semiconductor wafer has an active surface and a relatively inactive surface, and the active surface of the semiconductor wafer has a plurality of electrode pads; and an adhesive material is filled In the gap between the opening and the semiconductor wafer. In a consistent embodiment of the invention, the opening with the lead angle extends through the first and second surfaces of the carrier plate, and the lead angle is a full or semi-lead angle. The carrier board structure of the embedded semiconductor wafer of the embodiment further comprises a first dielectric layer formed on the first surface of the carrier board and the switching surface of the semiconductor wafer, and a second dielectric layer formed on the carrier a second surface of the board and an inactive surface of the semiconductor wafer. The carrier board structure of the semiconductor wafer embedded in the embodiment further includes a line build-up structure formed on one of the groups of the first and second dielectric layers, and the line lip-increasing structure is formed A plurality of electrically conductive structures are electrically connected to the semiconductor wafer, and a surface of the wiring buildup structure is formed with a plurality of electrical connection pads. Compared with the prior art, the carrier substrate structure of the embedded semiconductor wafer of the present invention forms an opening having a conductive angle, thereby facilitating the attachment of the semiconductor wafer to the opening of the carrier board, and the lead angle can be The adhesive material is uniformly and sufficiently filled in the opening to avoid residual air in the opening of the carrier plate, and the semiconductor wafer can be affected by the difference in thermal expansion coefficient. [Embodiment] The following is a description of the embodiments of the present invention by way of specific embodiments 9 19432 1297942, and those skilled in the art can readily appreciate other advantages and effects of the present invention from the disclosure herein. The figures 3A to 3E show the manufacturing process of the first embodiment of the carrier board structure for embedding the semiconductor wafer of the present invention. As shown in FIG. 3A, first, a carrier board 2 having a first surface 2〇a and a second surface 2〇b opposite to the first surface is provided, and at least one of the carrier board 2〇 is formed. The opening 21 of the lead angle 21, and the opening is or rectangular, and the opening 21 is penetrated through the first surface 20a of the carrier plate 2, and the lead angle 21 is a full angle. . In the case of Benbega, the 5th opening 21 series is formed by one of molding methods such as cutting, stamping, and laser. In the eighth embodiment, the opening 21 is formed in the carrier plate 2: 2, so that in the subsequent process, the semiconductor wafer 22 can be placed in the opening 21 by the lead angle. in. As shown in FIG. 3B, at least one semiconductor wafer is placed on the second surface of the carrier plate 2 to form a removable (four) plate (pattern). The semiconductor wafer 2 has an active surface 22a and an inactive surface 22b' opposite to the active surface, and the active surface of the semiconductor wafer 22 has a plurality of electrode pads 220. In the present embodiment, the semiconductor wafer 22 is placed in the opening 21 by its inactive surface (2). As shown in FIG. 3C, the gap between the (four) port 21 and the semiconductor wafer r is filled with an adhesive material m such as a resin material or a colloid, and the semiconductor wafer 22 is fixed in the opening 21 by CUring. . 19432 10 1297942 In this embodiment, since the opening 21 has a lead angle 21〇, the gap between the opening 2i and the semiconductor wafer 22 is a funnel shape that is large and small, so that the adhesive material 23 can be smoothly introduced into the opening. The opening 21, and indeed filled in the mouth, to avoid residual air in the opening 21 causes a blasting phenomenon in the subsequent heat 楯% process. In this embodiment, since the opening has a lead angle 210, the adhesive material 23 is not only uniformly filled, and the edge of the semiconductor wafer 22 and the opening 21 have a larger pitch at the edge of the lead angle 21〇. The thermal stress caused by the difference in thermal expansion coefficient can be avoided, and the edge of the semiconductor wafer 22 is damaged by the edge of the opening 21, or the peripheral edge of the semiconductor wafer 22 and the opening 21 are prevented from being excessively stressed. Addition process problems. As shown in FIG. 3D, a first dielectric layer 24 is formed on the first surface 2〇a of the carrier board 2 and the active surface 22a of the germanium semiconductor wafer 22, and the second surface 20b of the carrier board 20 And a non-active surface 22b of the semiconductor wafer 22 forms a second dielectric layer 25. A plurality of openings 240 are formed in the first and second dielectric layers 2425 to expose the semiconductor wafer and the pad 220. The first and second dielectric layers 24, 25 can be exemplified by epoxy: electric grease (also known as 5111), polyethylamine (?? 13^11^(^), cyanide (〇乂&111; ester), Glass fiber, Bismuthimide/Bismaleimide triazine, Polypropylene (pp, polypropylene), Bismuth or mixed epoxy Resin and glass fiber are formed. As shown in Fig. 3E, the 'after' complex can be formed on the surface of the first dielectric layer and the second dielectric layer 25 - the line build-up structure 26, and the wiring layer is 19432 11 1297942 plus, H; l $layer 26G '# is placed on the dielectric layer of the conductive layer 262 in the dielectric layer of the dielectric layer, and the portion is electrically connected to the semiconductor 22 of the semiconductor wafer 22 〇, and the surface of the second line build-up structure 26 is electrically connected, and the line build-up structure 26 on the surface of the electrical layer 24 and the second dielectric layer 25 is faulty by at least one plated via 29 In addition, a solder resist layer 28 is formed on the surface of the line build-up structure 26, and a plurality of openings are formed in the solder resist layer to expose the line buildup layer. The electrical connection pad 263 of the surface is shown in Fig. 4. According to another embodiment of the present invention, the lead angle 210 of the opening 21 may be a semi-conducting angle (the opening 21 is not provided). Fully chamfering, with its opening forming a partially chamfered, partially vertical pattern), also facilitates placement of the semiconductor wafer 22 in the opening 21, and facilitates filling the adhesive material 23 in the opening 21 And avoiding the generation of air bubbles, and avoiding thermal stress, affecting the edge of the semiconductor wafer 22 being damaged by the extrusion of the edge of the opening 21; or avoiding excessive stress on the periphery of the semiconductor wafer 22 and the periphery of the opening 21, which is disadvantageous for subsequent circuit buildup. Process board problem The carrier board structure of the embedded semiconductor wafer formed by the above method comprises: a carrier board 2, at least one opening 21 with a lead angle 21, at least one semiconductor wafer 22 and an adhesive material 23. The carrier board The 20 series has a first surface 20a and a second surface 20b opposite to the first surface 2〇a, and the carrier plate 20 is formed with at least one opening 2丨 with a lead angle 2丨; wherein the opening 21 is Through The carrier board 2 has a first surface 20a and a second surface 20b, and the lead angle 210 is a full or semi-conducting angle. The semiconductor 12 19432 1297942 is mounted in the opening 21, and the semiconductor is The wafer 22 has an active surface 22a and a non-active surface 2 opposite to the active surface, and the active surface 22a has a plurality of electrode pads 22A. The adhesive material 23 is filled in the openings 21 and 3 half-body wafers 22. The semiconductor wafer 22 is fixed in the opening 21 in the gap therebetween. In this embodiment, the carrier board structure of the embedded semiconductor wafer further includes a first surface formed on the carrier board 20 and an active surface 22a of the semiconductor wafer 22. And a dielectric layer 25 formed on the surface of the carrier board and the non-active surface of the semiconductor wafer; and the first dielectric layer and the second dielectric surface There is a secret layer structure 26, and a material addition layer structure (4): a solder mask layer 28 is formed, and the solder resist layer 28 has a plurality of openings. Gamma, 俾 to reveal the electrical properties of the surface of the build-up structure of the line The connection is added. The embedded semiconductor wafer carrier of the present invention forms at least a conductive carrier structure, mainly for the guide of the socket (such as the opening 21), and the semiconductor wafer can be facilitated by the opening angle Connected to the opening. In addition, the present invention can be used to facilitate the bonding of the adhesive material to the funnel shape. In the present invention, since the edge of the semiconductor wafer and the opening/porting system have a guiding angle, the coefficient of thermal expansion is different, and there is a large spacing, but The thermal stress of avoiding causes the edge of the semiconductor wafer to be damaged by the extrusion of the edge of the edge of the opening 19432 13 1297942. Further, in the present invention, since the opening of the carrier plate has a lead angle, the edge of the semiconductor wafer is avoided. The periphery of the opening is excessively stressed, causing delamination of the insulating layer and the periphery of the opening for granulation of the /, 1 line. The above embodiments are merely illustrative of the principles and advantages of the present invention and are not intended to limit the present invention. Anyone who is familiar with this skill can refrain from violating the spirit and scope of the invention. The modification of the above-mentioned examples is to protect the scope of the rights protection as described below.Listed in the range of benefits. 欠,·^甲明 [Simple description of the diagram] Figure; M 1A to 1D diagram is the process flow of the conventional embedded semiconductor wafer. Figure 2 is the conventional method of burying the semiconductor brothers 3 A to 3 Figure 6 is a cross-sectional view showing another structure of the wafer of the first embodiment of the present invention; the embedded semiconductor wafer; and the carrier of the conductor wafer
第4圖係顯示本發明之傲埋半 口導角另一實施例之剖視圖。 【主要元件符號說明】 10、20 承載板 100 、 100, 、 21 開口 l〇a、20a 第一表面 10b 、 20b 第二表面 11、22 半導體晶 19432 14 1297942 110 、 220 電極墊 12、23 黏者材料 13 > 260 介電層 13a、24 第一介電層 13b 、 25 第二介電層 14、14a、261 線路層 140 導電盲孔 142 > 29 電鍍導通孔 1 14a 第一線路層 14b 第二線路層 210、21(T 導角 22a 主動面 22b 非主動面 240 、 280 開孔 262 導電結構 263 電性連接墊 28 防焊層 15 19432Figure 4 is a cross-sectional view showing another embodiment of the proud half-guide angle of the present invention. [Main component symbol description] 10, 20 carrier plate 100, 100, 21 opening l〇a, 20a first surface 10b, 20b second surface 11, 22 semiconductor crystal 19432 14 1297942 110 , 220 electrode pad 12, 23 adhesive Material 13 > 260 dielectric layer 13a, 24 first dielectric layer 13b, 25 second dielectric layer 14, 14a, 261 circuit layer 140 conductive blind via 142 > 29 plated via 1 14a first circuit layer 14b Two circuit layers 210, 21 (T lead angle 22a active surface 22b inactive surface 240, 280 opening 262 conductive structure 263 electrical connection pad 28 solder mask 15 19432