CN112382607A - Method for manufacturing metal trench in copper process - Google Patents
Method for manufacturing metal trench in copper process Download PDFInfo
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- CN112382607A CN112382607A CN202011174770.XA CN202011174770A CN112382607A CN 112382607 A CN112382607 A CN 112382607A CN 202011174770 A CN202011174770 A CN 202011174770A CN 112382607 A CN112382607 A CN 112382607A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
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Abstract
The invention discloses a method for manufacturing a metal groove in a copper process, which comprises the following steps: sequentially forming a first NFDARC layer, a metal hard mask layer and a second NFDARC layer on the bottom layer structure; carrying out a first photoetching process to define a forming area of a first part of metal groove opening; performing a first etching process to form a first partial metal trench opening with the bottom stopped on the surface of the first NFDARC layer; carrying out a first ashing process to remove the first photoresist pattern; carrying out a second photoetching process to define a forming area of a second part of metal groove opening; performing a second etching process to form a second metal trench opening with the bottom stopped on the surface of the first NFDARC layer; and carrying out a second ashing process to remove the second photoresist pattern. The invention can form the metal hard mask layer opening of the metal groove by adopting 2P2E, can avoid the adverse effect of the photoresist removing process on the key size of the metal hard mask layer opening, and can keep the key size of the metal hard mask layer opening consistent.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a metal trench in a copper process.
Background
As the process advances, copper interconnects are formed in the back end of line (BEOL) using a copper process, which includes copper interconnects formed in metal trenches and copper-formed vias filled in via openings. Copper lines and vias are usually implemented by a damascene process such as a dual damascene process, in which a metal trench needs to be defined by a metal hard mask layer, the metal hard mask layer usually adopts TiN, and a nitrogen-free anti-reflective coating (NFDARC) needs to be formed on the bottom and the top of the TiN layer, respectively. Unlike SiON composed DARC, NFDARC contains no nitrogen.
In the prior art, before forming the metal trench, an opening of the metal hard mask layer needs to be formed first, so the opening forming process of the metal hard mask layer is very important, and when the critical dimension of the opening of the metal hard mask layer is deviated, the critical dimension of the metal trench is most deviated. As the technology node of semiconductor devices is reduced to below 14nm, the critical dimension of the metal trench is often below 64nm, the opening of the metal hard mask layer with such a dimension needs to be formed by two etching processes (2P2E) with 2 exposures, and the critical dimension of the opening of the metal hard mask layer is easily shifted by the conventional 2P2E process.
Disclosure of Invention
The invention aims to solve the technical problem of providing a method for manufacturing a metal groove in a copper process, which can form a metal hard mask layer opening of the metal groove by adopting 2-time exposure and two-time etching (2P2E) and can avoid the adverse effect of a photoresist removing process corresponding to the 2-time exposure on the key size of the metal hard mask layer opening, so that the key sizes of the metal hard mask layer openings formed by the two-time etching can be kept consistent, and finally the metal groove with smaller key size and better uniformity can be obtained.
In order to solve the above technical problem, the method for manufacturing a metal trench in a copper process according to the present invention comprises the following steps:
step one, providing a bottom layer structure needing to manufacture a metal groove, and sequentially forming a first NFDARC layer, a metal hard mask layer and a second NFDARC layer on the bottom layer structure.
And secondly, carrying out a first photoetching process and forming a first photoresist pattern, wherein a first opening of the first photoresist pattern defines a forming area of a first part of metal groove openings.
And step three, carrying out a first etching process to remove the second NFDARC layer and the metal hard mask layer at the bottom of the first opening and form a first partial metal trench opening with the bottom stopped on the surface of the first NFDARC layer.
And fourthly, carrying out a first ashing process to remove the first photoresist pattern, and preventing the first ashing process from changing the appearance of the first part of metal trench openings by utilizing the surface characteristics that the bottom of the first part of metal trench openings is stopped on the first NFDARC layer.
And fifthly, carrying out a second photoetching process and forming a second photoresist pattern, wherein a second opening of the second photoresist pattern defines a forming area of a second part of the metal groove opening.
And sixthly, performing a second etching process to remove the second NFDARC layer and the metal hard mask layer at the bottom of the second opening and form a second partial metal trench opening with the bottom stopped on the surface of the first NFDARC layer.
And seventhly, carrying out a second ashing process to remove the second photoresist pattern, and preventing the second ashing process from changing the appearance of the second part of the metal trench opening by utilizing the surface feature that the bottom of the second part of the metal trench opening is stopped on the first NFDARC layer.
The further improvement is that the material of the metal hard mask layer is TiN.
In a further improvement, in the first photolithography process, a first organic bottom layer and a first intermediate silicon-oxygen-based hard mask layer are further formed at the bottom of the first photoresist pattern.
In a further improvement, the first silicon-based hard mask intermediate layer and the first organic bottom layer are etched in the first etching process, and then the second NFDARC layer and the metal hard mask layer are etched.
The first ashing process removes the first silicon-based hard mask intermediate layer and the first organic base layer simultaneously.
In a further improvement, the first ashing process employs an oxygen plasma etching process.
In a further improvement, in the second photolithography process, a second organic bottom layer and a second intermediate layer of a silicon-oxygen-based hard mask are formed on the bottom of the second photoresist pattern.
In a further improvement, the second silicon-based hard mask intermediate layer and the second organic bottom layer are etched first in the second etching process, and then the second NFDARC layer and the metal hard mask layer are etched.
The second ashing process removes the second silicon-based hard mask intermediate layer and the second organic base layer simultaneously.
In a further improvement, the second ashing process employs an oxygen plasma etching process.
In a further improvement, the second opening and the first opening are offset from each other, such that the first partial metal trench opening and the second partial metal trench opening are offset from each other.
In a further improvement, in the first step, the bottom layer structure includes an interlayer film formed on the semiconductor substrate, and the interlayer film is etched to form the metal trench under the definition of the first part of the metal trench opening and the second part of the metal trench opening.
In a further improvement, the metal trench is filled with a copper layer to form a copper connection.
In a further refinement, the method further comprises the step of forming a via formed at the bottom of the selected region of the metal trench.
In a further improvement, openings of the metal groove and the through hole are formed by adopting a dual damascene process, and then copper layers are filled in the openings of the metal groove and the through hole simultaneously to form the copper connecting line and the through hole.
In a further improvement, a semiconductor device is formed on the semiconductor substrate.
In a further improvement, the process node of the semiconductor device is below 14 nm.
The copper connecting line is a back-end process, and the minimum width of the metal groove is less than 64 nm.
The invention adopts 2P2E process to form metal hard mask layer opening, namely first part metal trench opening and second part metal trench opening, which define metal trench, in order to eliminate the influence of ashing process for removing photoresist in the photoetching process on the first part metal trench opening and the second part metal trench opening, the invention makes special arrangement for two etching processes, wherein the two etching processes are arranged to directly etch through the metal hard mask layer by using corresponding photoresist pattern as mask and stop on the NFDARC layer at the bottom, namely the first NFDARC layer, thus eliminating the adverse effect of ashing process such as ashing process adopting oxygen plasma etching process on the surface of the metal hard mask layer when the etching process after the two photoetching processes is stopped on the surface of the metal hard mask layer, thereby eliminating the adverse effect on the critical dimension of the metal hard mask layer opening, the method can be particularly suitable for metal grooves of copper connecting lines of the back-end process of semiconductor devices with process nodes below 14nm, and can ensure that the minimum width of the metal grooves can reach below 64 nm.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIGS. 1A-1G are schematic views of a device structure in each step of a conventional copper process metal trench fabrication method;
FIG. 2 is a flowchart illustrating a method for forming a metal trench in a copper process according to an embodiment of the present invention;
FIGS. 3A-3D are schematic views of the device structure in the steps of the method for forming a metal trench in copper process according to the embodiment of the present invention.
Detailed Description
The existing copper process metal groove manufacturing method comprises the following steps:
the technical scheme of the embodiment of the invention is obtained on the basis of analyzing the technical problems of the prior method, so the prior method is introduced before the technical scheme of the embodiment of the invention is described in detail,
as shown in fig. 1A to fig. 1G, the device structure in each step of the method for manufacturing a metal trench in the conventional copper process is shown; the existing manufacturing method of the copper process metal groove comprises the following steps:
step one, as shown in fig. 1A, a bottom structure 101 requiring a metal trench to be fabricated is provided, and a first NFDARC layer 102, a metal hard mask layer 103, and a second NFDARC layer 104 are sequentially formed on the bottom structure 101.
Typically, the material of the metal hard mask layer 103 is TiN.
Step two, as shown in fig. 1A, a first photolithography process is performed to form a first photoresist pattern 107a, and a first opening 108a of the first photoresist pattern 107a defines a formation region of a first portion of the metal trench opening 109 a.
In general, in the first photolithography process, a first Organic underlayer (ODL) 105a and a first silicon-based Hard Mask intermediate Layer (Si-O-based Hard Mask, SHB)106a are further formed on the bottom of the first photoresist pattern 107 a. The first SHB layer 106a typically employs a bottom anti-reflective coating (BARC). The first ODL layer 105a is coated with Carbon (Spin-On-Carbon, SOC), which is a high Carbon content polymer.
Step three, as shown in fig. 1B, a first etching process is performed to remove the second NFDARC layer 104 at the bottom of the first opening 108a and form a first partial metal trench opening 109a whose bottom is stopped on the surface of the metal hard mask layer 103.
In general, in the first etching process, the first intermediate silicon-oxide-based hard mask layer 106a and the first organic bottom layer 105a are etched first, and then the second NFDARC layer 104 is etched.
Step four, as shown in fig. 1C, a first ashing process is performed to remove the first photoresist pattern 107 a.
Typically, the first ashing process removes the first intermediate silicon-based hard mask layer 106a and the first organic bottom layer 105a simultaneously.
The first ashing process adopts an oxygen plasma etching process.
The first ashing process is prone to adversely affect the metal hard mask layer 103, such as oxidation, which may affect the critical dimensions of the first portion of the metal trench opening 109 a.
And step five, as shown in fig. 1D, performing a second photolithography process and forming a second photoresist pattern 107b, wherein a second opening 108b of the second photoresist pattern 107b defines a formation region of a second portion of the metal trench opening 109 b.
In general, in the second photolithography process, a second organic underlayer 105b and a second intermediate siloxane-based hard mask layer 106b are also formed at the bottom of the second photoresist pattern 107 b.
The second SHB layer 106b is typically BARC. The second ODL layer 105b employs SOC.
Step six, as shown in fig. 1E, a second etching process is performed to remove the second NFDARC layer 104 at the bottom of the second opening 108b and form a second partial metal trench opening 109b whose bottom is stopped at the surface of the metal hard mask layer 103.
In general, the second etching process etches the second intermediate silicon-based hard mask layer 106b and the second organic bottom layer 105b first, and then etches the second NFDARC layer 104.
And seventhly, as shown in fig. 1F, performing a second ashing process to remove the second photoresist pattern 107 b.
Typically, the second ashing process will remove both the second intermediate siloxane-based hard mask layer 106b and the second bottom organic layer 105 b.
And the second ashing process adopts an oxygen plasma etching process.
The second opening 108b and the first opening 108a are offset from each other, so that the first partial metal trench opening 109a and the second partial metal trench opening 109b are offset from each other.
The second ashing process is prone to adversely affect the metal hard mask layer 103, such as oxidation, and affects the critical dimensions of the first and second portions of the metal trench openings 109a and 109b, since the surface of the first portion of the metal trench opening 109a is also affected during the second ashing process.
The manufacturing method of the metal groove in the copper process of the embodiment of the invention comprises the following steps:
FIG. 2 is a flow chart of a method for fabricating a metal trench in a copper process according to an embodiment of the present invention; as shown in fig. 3A to 3D, the schematic device structure in each step of the method for manufacturing a metal trench in a copper process according to the embodiment of the present invention is shown; the manufacturing method of the metal groove in the copper process comprises the following steps:
step one, as shown in fig. 3A, providing a bottom layer structure 1 where a metal trench needs to be fabricated, and sequentially forming a first NFDARC layer 2, a metal hard mask layer 3, and a second NFDARC layer 4 on the bottom layer structure 1.
In the embodiment of the present invention, the metal hard mask layer 3 is made of TiN.
Step two, as shown in fig. 3A, a first photolithography process is performed to form a first photoresist pattern 7a, and a first opening 8a of the first photoresist pattern 7a defines a formation region of a first portion of the metal trench opening 9 a.
In the embodiment of the present invention, in the first photolithography process, a first organic bottom layer 5a and a first intermediate silicon-oxygen-based hard mask layer 6a are further formed at the bottom of the first photoresist pattern 7 a.
Step three, as shown in fig. 3B, a first etching process is performed to remove both the second NFDARC layer 4 and the metal hard mask layer 3 at the bottom of the first opening 8a and form a first partial metal trench opening 9a with the bottom stopped on the surface of the first NFDARC layer 2.
In the embodiment of the present invention, in the first etching process, the first silicon-oxygen-based hard mask intermediate layer 6a and the first organic bottom layer 5a are etched first, and then the second NFDARC layer 4 and the metal hard mask layer 3 are etched.
Step four, as shown in fig. 3B, a first ashing process is performed to remove the first photoresist pattern 7a, and the first ashing process is prevented from changing the topography of the first portion of the metal trench opening 9a by stopping the bottom of the first portion of the metal trench opening 9a at the surface feature of the first NFDARC layer 2.
In the embodiment of the present invention, the first ashing process removes the first intermediate silicon-oxygen-based hard mask layer 6a and the first organic bottom layer 5a simultaneously.
The first ashing process adopts an oxygen plasma etching process.
And step five, as shown in fig. 3C, performing a second photolithography process and forming a second photoresist pattern 7b, wherein a second opening 8b of the second photoresist pattern 7b defines a forming region of a second portion of the metal trench opening 9 b.
In the embodiment of the present invention, in the second photolithography process, a second organic bottom layer 5b and a second intermediate silicon-oxygen-based hard mask layer 6b are further formed at the bottom of the second photoresist pattern 7 b.
Step six, as shown in fig. 3D, a second etching process is performed to remove both the second NFDARC layer 4 and the metal hard mask layer 3 at the bottom of the second opening 8b and form a second partial metal trench opening 9b with the bottom stopped on the surface of the first NFDARC layer 2.
In the embodiment of the present invention, in the second etching process, the second silicon-oxygen-based hard mask intermediate layer 6b and the second organic bottom layer 5b are etched first, and then the second NFDARC layer 4 and the metal hard mask layer 3 are etched.
Seventhly, as shown in fig. 3D, performing a second ashing process to remove the second photoresist pattern 7b, and stopping the bottom of the second portion of the metal trench opening 9b on the surface feature of the first NFDARC layer 2 to prevent the second ashing process from changing the topography of the second portion of the metal trench opening 9 b.
In the embodiment of the present invention, the second ashing process removes the second intermediate silicon-oxygen-based hard mask layer 6b and the second organic bottom layer 5b simultaneously.
And the second ashing process adopts an oxygen plasma etching process.
The second opening 8b and the first opening 8a are offset from each other, so that the first partial metal trench opening 9a and the second partial metal trench opening 9b are offset from each other.
In the first step, the underlying structure 1 includes an interlayer film formed on a semiconductor substrate, and the interlayer film is etched to form a metal trench under the definition of the first part of the metal trench opening 9a and the second part of the metal trench opening 9 b.
The following steps are also included: and filling a copper layer in the metal groove to form a copper connecting line.
Further comprising the step of forming a via formed at the bottom of the selected region of the metal trench.
And forming openings of the metal groove and the through hole by adopting a dual damascene process, and then filling copper layers in the openings of the metal groove and the through hole simultaneously to form the copper connecting line and the through hole.
A semiconductor device is formed on the semiconductor substrate.
The process node of the semiconductor device is below 14 nm.
The copper connecting line is a back-end process, and the minimum width of the metal groove is less than 64 nm.
In the embodiment of the invention, 2P2E technology is adopted to form the openings of the metal hard mask layer 3 for defining the metal groove, namely the first part of metal groove opening 9a and the second part of metal groove opening 9b, in order to eliminate the influence of the ashing technology for removing photoresist in the photoetching technology at two sides on the first part of metal groove opening 9a and the second part of metal groove opening 9b, the embodiment of the invention makes special setting for the two etching technologies, the two etching technologies are set to directly etch the metal hard mask layer 3 through by taking the corresponding photoresist pattern as a mask and stop on the NFDARC layer at the bottom, namely the first NFDARC layer 2, thus the adverse influence of the ashing technology such as oxygen plasma etching technology on the surface of the metal hard mask layer 3 when the etching technologies after the two photoetching technologies stop on the surface of the metal hard mask layer 3 can be eliminated, therefore, the adverse effect on the critical dimension of the opening of the metal hard mask layer 3 can be eliminated, the deviation of the critical dimension of the opening of the metal hard mask layer 3 is prevented, the critical dimension of the opening of the metal hard mask layer 3 formed by two times of etching can be kept consistent, and finally the metal groove with smaller critical dimension and better uniformity can be obtained.
The present invention has been described in detail with reference to the specific embodiments, but these are not to be construed as limiting the invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. A method for manufacturing a metal groove in a copper process is characterized by comprising the following steps:
providing a bottom layer structure needing to manufacture a metal groove, and sequentially forming a first NFDARC layer, a metal hard mask layer and a second NFDARC layer on the bottom layer structure;
performing a first photoetching process and forming a first photoresist pattern, wherein a first opening of the first photoresist pattern defines a forming area of a first part of metal groove openings;
step three, carrying out a first etching process to remove the second NFDARC layer and the metal hard mask layer at the bottom of the first opening and form a first part of metal groove opening with the bottom stopped on the surface of the first NFDARC layer;
fourthly, carrying out a first ashing process to remove the first photoresist pattern, and utilizing the surface characteristics that the bottom of the first part of the metal trench opening is stopped on the first NFDARC layer to prevent the first ashing process from changing the appearance of the first part of the metal trench opening;
fifthly, carrying out a second photoetching process and forming a second photoresist pattern, wherein a second opening of the second photoresist pattern defines a forming area of a second part of metal groove opening;
sixthly, performing a second etching process to remove the second NFDARC layer and the metal hard mask layer at the bottom of the second opening and form a second part of metal trench opening with the bottom stopped on the surface of the first NFDARC layer;
and seventhly, carrying out a second ashing process to remove the second photoresist pattern, and stopping the bottom of the second part of the metal groove opening on the surface feature of the first NFDARC layer to prevent the second ashing process from changing the appearance of the second part of the metal groove opening.
2. The method of claim 1, further comprising: the metal hard mask layer is made of TiN.
3. The method of claim 2, further comprising: in the first photoetching process, a first organic bottom layer and a first silicon-oxygen-based hard mask middle layer are further formed at the bottom of the first photoresist pattern.
4. The method of claim 3, further comprising: in the first etching process, the first silicon-oxygen-based hard mask middle layer and the first organic bottom layer are etched firstly, and then the second NFDARC layer and the metal hard mask layer are etched;
the first ashing process removes the first intermediate silicon-based hard mask layer and the first organic bottom layer simultaneously.
5. The method of claim 1 or 4, further comprising: the first ashing process adopts an oxygen plasma etching process.
6. The method of claim 2, further comprising: in the second photoetching process, a second organic bottom layer and a second silicon-oxygen-based hard mask middle layer are further formed at the bottom of the second photoresist pattern.
7. The method of claim 6, further comprising: in the second etching process, the second silicon-based hard mask middle layer and the second organic bottom layer are etched firstly, and then the second NFDARC layer and the metal hard mask layer are etched;
the second ashing process removes the second intermediate silicon-based hard mask layer and the second organic bottom layer simultaneously.
8. The method of claim 1 or 7, further comprising: and the second ashing process adopts an oxygen plasma etching process.
9. The method of claim 1, further comprising: the second openings and the first openings are staggered with each other, so that the first part of metal groove openings and the second part of metal groove openings are staggered with each other.
10. The method of claim 9, further comprising: in the first step, the bottom layer structure comprises an interlayer film formed on the semiconductor substrate, and the interlayer film is etched to form the metal trench under the definition of the first part of the metal trench opening and the second part of the metal trench opening.
11. The method of claim 10, further comprising: and filling a copper layer in the metal groove to form a copper connecting line.
12. The method of claim 10, further comprising: further comprising the step of forming a via formed at the bottom of the selected region of the metal trench.
13. The method of claim 12, further comprising: and forming openings of the metal groove and the through hole by adopting a dual damascene process, and then filling copper layers in the openings of the metal groove and the through hole simultaneously to form the copper connecting line and the through hole.
14. The method of claim 10, further comprising: a semiconductor device is formed on the semiconductor substrate.
15. The method of claim 14, further comprising: the process node of the semiconductor device is below 14 nm;
the copper connecting line is a back-end process, and the minimum width of the metal groove is less than 64 nm.
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| US20050048788A1 (en) * | 2003-08-26 | 2005-03-03 | Tang Woody K. Sattayapiwat | Methods of reducing or removing micromasking residue prior to metal etch using oxide hardmask |
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| CN104124149A (en) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN104934364A (en) * | 2014-03-19 | 2015-09-23 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of interconnection layer and manufacturing method of semiconductor device |
| CN109727910A (en) * | 2018-12-29 | 2019-05-07 | 上海华力集成电路制造有限公司 | A kind of semiconductor structure and its manufacturing method |
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| US20050048788A1 (en) * | 2003-08-26 | 2005-03-03 | Tang Woody K. Sattayapiwat | Methods of reducing or removing micromasking residue prior to metal etch using oxide hardmask |
| US20130216776A1 (en) * | 2012-02-22 | 2013-08-22 | International Business Machines Corporation | Dual hard mask lithography process |
| CN103811409A (en) * | 2012-11-12 | 2014-05-21 | 中微半导体设备(上海)有限公司 | Method for enhancing etching selectivity of low dielectric material for TiN hard mask |
| CN104124149A (en) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN104934364A (en) * | 2014-03-19 | 2015-09-23 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of interconnection layer and manufacturing method of semiconductor device |
| CN109727910A (en) * | 2018-12-29 | 2019-05-07 | 上海华力集成电路制造有限公司 | A kind of semiconductor structure and its manufacturing method |
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