CN114496913A - Etching structure and method for contact hole of integrated circuit - Google Patents
Etching structure and method for contact hole of integrated circuit Download PDFInfo
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Abstract
The invention relates to the technical field of integrated circuits, and discloses an etching structure and a method for a contact hole of an integrated circuit.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an etching structure and method for a contact hole of an integrated circuit.
Background
In an integrated circuit process, a contact hole is mainly used for connecting a CMOS device and a back-end copper process circuit, and whether the hole shape of the contact hole is good or not is crucial to the performance of a chip. At present, the difficulty of the manufacturing process of the contact hole is to meet the performance of different structures, which means that the contact resistance and related electrical parameters are in accordance with the design requirements. In addition, the aperture and the profile of the contact hole also meet the relevant requirements of the wafer to be tested.
In the existing deep hole and contact hole process, under different loading effects, in order to ensure that the profile of the deep hole or the contact hole is not disconnected, a sufficient or even excessive etching amount needs to be provided when the deep hole or the contact hole is etched. However, excessive lateral etching causes the outline of the Contact Hole to be expanded, i.e. a bowl-shaped outline appears, for example, in fig. 1 and fig. 2, when a deep via connected to a PMD Contact is formed on a DRAM and a Contact Hole connected to a gate is formed on a logic CMOS device, respectively, in the BT & ME step, a Contact Hole Critical Dimension must be defined, the step is biased toward chemical etching, F etching radicals are required to be used as a main etching gas to react, the energy of the lateral etching is required to completely define the size of a CD to be a main etching function, but in the subsequent ME → OE step, although the etching behavior is continued, because of the requirement of high aspect ratio and the size requirement of a soft landing device, the conversion mode of the etching gas must be converted into a high bombardment mode (physical etching), due to the mode conversion factor, the bowl-shaped contour appears on the upper part of the deep through hole, and the whole contact hole is in the bowl-shaped contour. In addition, in the production process or production line of the semiconductor device, the production process of each chip or device is carried out step by step according to the design requirements, and if the original process specification is changed to solve the problem of bowl-shaped profile during the contact hole manufacturing, the problem of production cost increase may be brought.
Disclosure of Invention
In view of the shortcomings of the prior art, the present invention provides an etching structure and method for a contact hole of an integrated circuit, which solves the problem of bowl-shaped profile during the manufacture of the contact hole without changing the process specification of the existing contact hole.
In order to solve the above technical problems, a first aspect of the present invention provides an etching structure for a contact hole of an integrated circuit, including a substrate, wherein a first dielectric layer and a second dielectric layer are sequentially disposed on a top of the substrate from bottom to top, and an etching rate of the second dielectric layer is smaller than an etching rate of the first dielectric layer.
In a certain implementation manner of the first aspect, a silicon nitride layer and a dielectric layer are sequentially disposed from bottom to top between the substrate and the first dielectric layer, and an anti-reflection layer and a photoresist layer are sequentially disposed from bottom to top on the second dielectric layer.
In a certain implementation manner of the first aspect, the second dielectric layer is provided with an ODL layer, an SHB layer, and a photoresist layer in this order from bottom to top.
In a second aspect, the present invention provides a method for etching a contact hole of an integrated circuit, comprising the steps of:
s1: growing a first dielectric layer on the top of the substrate through a deposition process;
s2: growing a second dielectric layer on the first dielectric layer through a deposition process, wherein the etching rate of the second dielectric layer is less than that of the first dielectric layer;
s3: defining the position of a contact hole on the second dielectric layer through a photoetching process;
s4: and etching the contact hole by an etching process.
In one embodiment of the second aspect, the first dielectric layer and the second dielectric layer are made of the same material, and the deposition rate of the first dielectric layer is greater than that of the second dielectric layer.
In one embodiment of the second aspect, in step S1, before growing the first dielectric layer, a silicon nitride layer and a dielectric layer are grown on the substrate in sequence from bottom to top; in step S2, after the second dielectric layer is grown, an anti-reflection layer and a photoresist layer are sequentially formed on the second dielectric layer from bottom to top.
In one embodiment of the second aspect, step S4 includes the steps of:
s40: etching the anti-reflection layer through a one-time etching process, and transferring the contour of the contact hole defined on the photoresist layer to the anti-reflection layer;
s41: etching a second dielectric layer by a secondary etching process, transferring the outline of the contact hole on the anti-reflection layer to the second dielectric layer, and adjusting the etching rate by adjusting the radio frequency power of an etching machine in the etching process;
s42: etching the first dielectric layer by three etching processes and adjusting the radio frequency of an etching machine and generating an etching selection ratio to stop the etching on the silicon nitride layer between the substrate and the first dielectric layer, and transferring the outline of the contact hole on the second dielectric layer to the first dielectric layer by the etching;
s43: etching the silicon nitride layer by four times of etching processes and adjusting the radio frequency of the etching machine, completely etching through the silicon nitride layer, and transferring the outline of the contact hole on the first dielectric layer onto the silicon nitride layer to form a complete contact hole.
In one embodiment of the second aspect, in step S2, after the second dielectric layer is formed, the ODL layer, the SHB layer and the photoresist layer are sequentially formed on the second dielectric layer from bottom to top.
In one embodiment of the second aspect, step S4 includes the steps of:
s40: etching the SHB layer and the ODL layer by a primary etching process, and transferring the contour of the contact hole defined on the photoresist layer to the SHB layer and the ODL layer;
s41: etching a second dielectric layer by a secondary etching process, transferring the outlines of the contact holes on the SHB layer and the ODL layer to the second dielectric layer, and adjusting the etching rate by adjusting the radio frequency power of an etching machine in the etching process;
s42: the first dielectric layer is etched and penetrates through the first dielectric layer by the three-time etching process and by adjusting the radio frequency of the etching machine, and the outline of the contact hole in the second dielectric layer is transferred to the first dielectric layer by the etching, so that a complete contact hole is formed.
In one embodiment of the second aspect, the present invention further comprises step S5, wherein step S5 is as follows: and cleaning the residual photoresist and polymer in the contact hole by using gas.
Compared with the prior art, the invention has the following beneficial effects: because the deposition rate and the plasma density during the film deposition and the density of the oxide layer film formed by the deposition rate and the plasma density can show a positive correlation trend, namely the density of the stack during the deposition can be better than the behaviors of high plasma and high deposition rate; in other words, when the oxide layer density is enhanced, the etching resistance of the film itself is also enhanced. In the invention, the first dielectric layer and the second dielectric layer are respectively manufactured on the substrate, and the etching rate of the second dielectric layer is smaller than that of the first dielectric layer, so that the second dielectric layer has better anti-etching benefit, the lateral etching behavior can be effectively improved, and the problem of bowl-shaped outline during the etching of the contact hole is avoided.
Drawings
FIG. 1 is a schematic diagram of a bowl-shaped profile during deep via etching of a conventional DRAM;
FIG. 2 is a schematic diagram of a bowl-shaped profile that occurs during contact hole etching for a prior art logic CMOS device;
FIG. 3 is a schematic diagram of a first embodiment of an etched structure according to the present invention;
FIG. 4 is a second schematic diagram of an etched structure of the present invention in an example;
FIG. 5 is a schematic diagram of a third structure of an etched structure of the present invention in accordance with an embodiment;
FIG. 6 is a flow chart of an etching method of the present invention;
FIGS. 7a to 7f are schematic views showing structural changes in etching of a contact hole of a DRAM by the etching method of the present invention;
FIGS. 8a 8e are schematic structural changes of logic CMOS devices etched by the etching method of the present invention.
Detailed Description
Illustrative embodiments of the present application include, but are not limited to, an etching structure and method for a contact hole of an integrated circuit.
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if," as used herein, may be interpreted as "when or" responsive to a determination, "depending on the context.
In the conventional manufacturing process of the contact hole of the integrated circuit, a dielectric layer is mostly manufactured on a substrate, and then the pattern of the contact hole is etched on the dielectric layer. As shown in fig. 1 and 2, the conventional contact hole manufacturing method has a problem that a bowl-shaped profile of the contact hole occurs during actual use, which affects the performance of the manufactured chip.
In order to overcome the defects of the prior art, as shown in fig. 3, an etching structure for a contact hole of an integrated circuit includes a substrate 1, a first dielectric layer 4 and a second dielectric layer 5 are sequentially disposed on the top of the substrate 1 from bottom to top, and an etching rate of the second dielectric layer 5 is smaller than that of the first dielectric layer 4.
In practical use, electronic components for interconnection, such as MOS transistors, resistors, capacitors, or the like, are arranged on the substrate, and the electronic components on the substrate can be interconnected according to a circuit diagram by forming contact holes on the first dielectric layer and the second dielectric layer.
As shown in fig. 4, the inventive etch structure of fig. 4 is primarily useful for deep hole etching, such as the etching of deep holes that make communication with PMD contacts of DRAMs. In the etching structure in fig. 4, a silicon nitride layer 2, a dielectric layer 3, a first dielectric layer 4 and a second dielectric layer 5 are sequentially arranged on a substrate 1 from bottom to top, the etching rate of the second dielectric layer 5 is smaller than that of the first dielectric layer 4, and an anti-reflection layer 6 and a photoresist layer 7 are sequentially arranged on the second dielectric layer 5 from bottom to top.
In practical use, the silicon nitride layer 2 is used as an etching barrier layer, the dielectric layer 3 is used for isolating connection between wires, the photoresist layer is used for defining the position of a deep hole in a photoetching process, and the anti-reflection layer 6 is spin-coated on the interface between the photoresist and the substrate to absorb substances of photoetching reflection light and used as the anti-reflection layer to avoid the standing wave effect caused by optical reflection to further generate photoresist deformation.
As shown in fig. 5, the inventive etched structure of fig. 5 is primarily used for etching contact holes that communicate with contacts of logic CMOS devices. In the etching structure shown in fig. 5, a first dielectric layer 4 and a second dielectric layer 5 are sequentially arranged on a substrate 1 from bottom to top, the etching rate of the second dielectric layer 5 is smaller than that of the first dielectric layer 4, and an ODL layer 10, an SHB layer 11 and a photoresist layer 7 are sequentially arranged on the second dielectric layer 5 from bottom to top.
In practical applications, the photoresist layer 7 may be used to define the position of the contact hole, the ODL layer 10 is used to etch the mask layer to define the depth and CD of the oxide layer, so the thickness of the ODL layer 10 is greater than that of the SHB layer, the SHB layer 11 is used as a CD definition transfer layer, the CD size of the lithography definition photoresist must be effectively and correctly transferred to the SHB layer, and the SHB layer is thinner than the original oxide layer, so the problem of lithography resolution can be effectively solved.
In the etching structure of fig. 3 to 5, the materials of the first dielectric layer 4 and the second dielectric layer 5 are the same. In this embodiment, the first dielectric layer 4 and the second dielectric layer 5 are both made of an tetraethyl orthosilicate oxide film. In one embodiment, the first dielectric layer 4 and the second dielectric layer 5 may be configured as other oxide films with the same material according to actual requirements. In one embodiment, the first dielectric layer 4 and the second dielectric layer 5 may be formed of other oxide films having different materials, so that the etching rate of the second dielectric layer 5 is smaller than that of the first dielectric layer 4. In one embodiment, the lateral etching rate of the second dielectric layer 5 is made smaller than the etching rate of the first dielectric layer 4.
In addition, the etching rate of the second dielectric layer 5 is smaller than that of the first dielectric layer 4 in this embodiment may be understood as that the etching rate of the second dielectric layer 5 is smaller than that of the first dielectric layer 4 in the same etching environment, or when the first dielectric layer 4 is etched in the first etching environment and the second dielectric layer 5 is etched in the second etching environment, the etching rate of the second dielectric layer 5 in the second etching environment is smaller than that of the first dielectric layer 4 in the first etching environment.
In the etching structures of fig. 3 to 5, the photoresist used for the photoresist layer 7 may be a positive photoresist or a negative photoresist, and an ultraviolet photoresist, a deep ultraviolet photoresist, an X-ray photoresist, an electron beam photoresist or an ion beam photoresist may be used according to the difference between the exposure light source and the radiation source.
In the etching structures in fig. 3 to 5, since the etching rate of the second dielectric layer 5 is less than that of the first dielectric layer 4, the second dielectric layer 5 has better etching resistance, and can effectively improve the lateral etching behavior, thereby preventing the contact hole from having a bowl-shaped profile when the contact hole is etched.
As shown in fig. 6, an etching method of a contact hole for an integrated circuit includes the steps of:
s1: growing a first dielectric layer 4 on the top of the substrate 1 by a deposition process;
s2: growing a second dielectric layer 5 on the first dielectric layer 4 through a deposition process, wherein the etching rate of the second dielectric layer 4 is less than that of the first dielectric layer 5;
s3: defining the position of a contact hole on the second medium layer 5 through a photoetching process;
s4: the contact holes are etched by an etching process.
In steps S1 and S2, the first dielectric layer 4 and the second dielectric layer 5 can be formed by chemical vapor deposition or physical vapor deposition. In addition, the materials of the first dielectric layer 4 and the second dielectric layer 5 grown in steps S1 and S2 are the same and are both tetraethoxysilane oxidation films, and since the materials of the first dielectric layer 4 and the second dielectric layer 5 are the same, in order to make the etching rate of the second dielectric layer 5 smaller than that of the first dielectric layer 4, the deposition rate of the second dielectric layer 5 during growth is smaller than that of the first dielectric layer 4, so that the grown second dielectric layer 5 is denser and has better etching resistance, when the first dielectric layer 4 and the second dielectric layer 5 are grown by using the physical vapor deposition process, in order to make the growth rate of the second dielectric layer 5 lower, the power of a radio frequency device used by the physical vapor deposition equipment is required to be lower when the second dielectric layer 5 is grown.
In one embodiment, in order to shorten the total growth time of the first dielectric layer 4 and the second dielectric layer 5, the first dielectric layer 3 and the second dielectric layer 5 may be made of different materials, and the etching rate of the second dielectric layer 5 is less than that of the first dielectric layer 4 in the same etching environment.
In practical use, after the first dielectric layer 4 is grown, the CMP planarization process is performed on the top of the first dielectric layer 4 to provide a good growth environment for the second dielectric layer 5.
Taking the example of making contact holes on the substrate 1 in communication with PMD contacts of the DRAM chip on the substrate 1, before step S1 is performed, a silicon nitride layer 2 and a dielectric layer 3 are grown on the substrate 1, and a schematic structural diagram of the grown silicon nitride layer 2 and dielectric layer 3 is shown in fig. 7 a;
then, step S1 is executed, a first dielectric layer 4 is grown on the dielectric layer 3, a schematic structural diagram of the grown first dielectric layer 4 is shown in fig. 7b, a second dielectric layer 5 is grown on the first dielectric layer 4, a schematic structural diagram of the grown second dielectric layer 5 is shown in fig. 7c, and the growth of the first dielectric layer 4 and the growth of the second dielectric layer 5 can refer to the above description;
in step S2, after the second dielectric layer 5 is grown, the antireflection layer 6 and the photoresist layer 7 are sequentially formed on the second dielectric layer 5 from bottom to top; the schematic structural diagram after the growth of the anti-reflection layer 6 and the photoresist layer 7 is shown in fig. 7d, and the position of the contact hole pattern 8 is defined on the photoresist layer 7 through an exposure process, and the specific structural diagram is shown in fig. 7 e.
In step S4, since the contact hole 9 needs to be etched on the first dielectric layer 4 and the second dielectric layer 5 according to the position of the contact hole pattern 8, step-by-step etching is required, which specifically includes the following steps:
s40: etching the anti-reflection layer 6 by a one-time etching process to transfer the profile of the contact hole defined on the photoresist layer 7 to the anti-reflection layer 6; in the one-time etching process in this step, the antireflection layer 6 is etched using an etching gas including CxFy gas and CHxFy gas, where x and y are integers;
s41: etching the second dielectric layer 5 by a secondary etching process, transferring the outline of the contact hole on the anti-reflection layer 6 onto the second dielectric layer 5, and adjusting the etching rate by adjusting the radio frequency power of an etching machine in the etching process; in the secondary etching process in this step. The second dielectric layer 5 may be etched using an etching gas including CxFy gas and CHxFy gas, where x and y are integers, and an inert gas may be argon or oxygen, or an inert gas and a diluent gas may be oxygen;
s42: etching the first dielectric layer 4 by three etching processes and adjusting the radio frequency of an etching machine and generating an etching selection ratio to stop the etching on the silicon nitride layer 2 between the substrate 1 and the first dielectric layer 4, and transferring the outline of the contact hole on the second dielectric layer 5 to the first dielectric layer 4 by the etching; in the third etching process in this step, the first dielectric layer 4 may be etched using an etching gas, an inert gas, and a gas containing a CH-long carbon chain structure, or the first dielectric layer 4 may be etched using an etching gas, a diluent gas, and a gas containing a CH-long carbon chain structure; wherein the etching gas includes CxFy gas and CHxFy gas, x and y are integers, the inert gas may be argon or oxygen, the diluent gas may be oxygen, and the CH-containing long carbon chain in the CH-containing long carbon chain structure gas may be C-OH, C ═ O, or-C ═ O.
S43: etching the silicon nitride layer 2 by four etching processes and adjusting the radio frequency of the etching machine, completely etching through the silicon nitride layer 2, and transferring the outline of the contact hole on the first dielectric layer 4 onto the silicon nitride layer 2 to form a complete contact hole 9, wherein the structure schematic diagram of the etched contact hole 9 is shown in fig. 7 f; in the four etching processes in this step, the silicon nitride layer 2 may be etched using an etching gas, an inert gas, and a CH-gas containing a long carbon chain structure, or the silicon nitride layer 2 may be etched using an etching gas, a diluent gas, and a CH-gas containing a long carbon chain structure; wherein the etching gas includes CxFy gas and CHxFy gas, x and y are integers, the inert gas may be argon or oxygen, the diluent gas may be oxygen, and the long carbon chain structure-containing gas in the CH-long carbon chain structure-containing gas may be C-OH, C ═ O, or-C ═ O.
After step S4 is completed, step S5 is also executed, and step S5 is as follows: cleaning the residual photoresist and polymer in the contact hole by using gas; wherein the gas in this step may be argon, oxygen or nitrogen.
Taking the example of manufacturing contact holes communicated with contacts of a CMOS device on a substrate 1 on the substrate 1 as an example, a first dielectric layer 4 and a second dielectric layer 5 are sequentially grown on the substrate 1, the structural schematic diagram of the grown first dielectric layer 4 is shown in FIG. 8a, the structural schematic diagram of the grown second dielectric layer 5 is shown in FIG. 8b, and the growth modes of the first dielectric layer 4 and the second dielectric layer 5 refer to the above description;
in step S2, sequentially growing an ODL layer 10, an SHB layer 11, and a photoresist layer 7 on the second dielectric layer 5, where a structural schematic diagram of the grown ODL layer 10, SHB layer, and photoresist layer 7 is shown in fig. 8c, and then defining a position of the contact hole pattern 8 on the photoresist layer 7 through an exposure process, where a specific structural schematic diagram is shown in fig. 8 d;
in step S4, since the contact hole 9 needs to be etched on the first dielectric layer 4 and the second dielectric layer 5 according to the position of the contact hole pattern 8, distributed etching is needed, which specifically includes the following steps:
s40: etching the SHB layer 11 and the ODL layer 10 by a single etching process, and transferring the profile of the contact hole defined on the photoresist layer 7 onto the SHB layer 11 and the ODL layer 10; etching the SHB layer 11 and the ODL layer 10 using an etching gas in one etching process in this step, the etching gas including a CxFy gas and a CHxFy gas, wherein x and y are integers;
s41: etching the second dielectric layer 5 by a secondary etching process, transferring the outlines of the contact holes on the SHB layer 11 and the ODL layer 10 onto the second dielectric layer 5, and adjusting the etching rate by adjusting the radio frequency power of an etching machine in the etching process; in the secondary etching process in this step, the second dielectric layer 5 is etched using an etching gas including CxFy gas and CHxFy gas, x and y being integers, and an inert gas which may be argon or oxygen, and an inert gas which may be CHxFy gas, or the second dielectric layer 5 is etched using an etching gas and a diluent gas;
s42: etching the first dielectric layer 4 and etching through the first dielectric layer 4 by three etching processes and adjusting the radio frequency of the etching machine, transferring the outline of the contact hole on the second dielectric layer 5 to the first dielectric layer 4 by the etching, so as to form a complete contact hole, wherein the structural schematic diagram of the etched contact hole 9 is shown in fig. 8 e; in the third etching process in this step, the first dielectric layer 4 is etched using an etching gas including a CxFy gas and a CHxFy gas, x and y are integers, an inert gas may be argon or oxygen, a diluent gas may be oxygen, and a gas containing a CH-long carbon chain structure may be C-OH, C ═ O, or-C ═ O, or a diluent gas including a CHxFy gas and a CHxFy gas;
s43: and cleaning the residual photoresist and polymer in the contact hole by using gas, wherein the gas in the step can be argon, oxygen or nitrogen.
After step S4 is completed, step S5 is also executed, and step S5 is as follows: cleaning the residual photoresist and polymer in the contact hole in fig. 8e with gas; wherein the gas in this step may be argon, oxygen or nitrogen.
In summary, in the etching method of the present invention, the first dielectric layer 4 and the second dielectric layer 5 are sequentially grown on the top of the substrate 1 from bottom to top, so that the etching rate of the second dielectric layer 5 is greater than the etching rate of the first dielectric layer 4, and the second dielectric layer 5 can obtain better anti-etching effect, thereby effectively improving the lateral etching behavior and avoiding the bowl-shaped profile of the contact hole during etching.
In light of the foregoing, it is to be understood that various changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.
Claims (10)
1. The etching structure for the contact hole of the integrated circuit comprises a substrate and is characterized in that a first dielectric layer and a second dielectric layer are sequentially arranged on the top of the substrate from bottom to top, and the etching rate of the second dielectric layer is smaller than that of the first dielectric layer.
2. The etching structure of claim 1, wherein a silicon nitride layer and a dielectric layer are sequentially disposed from bottom to top between the substrate and the first dielectric layer, and an anti-reflection layer and a photoresist layer are sequentially disposed from bottom to top on the second dielectric layer.
3. The etching structure of claim 1, wherein the second dielectric layer is provided with an ODL layer, an SHB layer and a photoresist layer from bottom to top.
4. A method for etching a contact hole for an integrated circuit, comprising the steps of: s1:
growing a first dielectric layer on the top of the substrate through a deposition process;
s2: growing a second dielectric layer on the first dielectric layer through a deposition process, wherein the etching rate of the second dielectric layer is less than that of the first dielectric layer;
s3: defining the position of a contact hole on the second medium layer through a photoetching process;
s4: and etching the contact hole by an etching process.
5. The etching method according to claim 4, wherein the first dielectric layer and the second dielectric layer are made of the same material, and the deposition rate of the first dielectric layer is greater than that of the second dielectric layer.
6. The etching method according to claim 4, wherein in step S1, before growing the first dielectric layer, a silicon nitride layer and a dielectric layer are grown on the substrate in sequence from bottom to top; in step S2, after the second dielectric layer is grown, an anti-reflection layer and a photoresist layer are sequentially formed on the second dielectric layer from bottom to top.
7. The etching method according to claim 6,
step S4 includes the following steps:
s40: etching the anti-reflection layer through a one-time etching process, and transferring the contour of the contact hole defined on the photoresist layer to the anti-reflection layer;
s41: etching a second dielectric layer by a secondary etching process, transferring the outline of the contact hole on the anti-reflection layer to the second dielectric layer, and adjusting the etching rate by adjusting the radio frequency power of an etching machine in the etching process;
s42: etching the first dielectric layer by three etching processes and adjusting the radio frequency of an etching machine and generating an etching selection ratio to stop the etching on the silicon nitride layer between the substrate and the first dielectric layer, and transferring the outline of the contact hole on the second dielectric layer to the first dielectric layer by the etching;
s43: etching the silicon nitride layer by four times of etching processes and adjusting the radio frequency of the etching machine, completely etching through the silicon nitride layer, and transferring the outline of the contact hole on the first dielectric layer onto the silicon nitride layer to form a complete contact hole.
8. The etching method according to claim 4, wherein in step S2, after the second dielectric layer is formed, the ODL layer, the SHB layer and the photoresist layer are formed on the second dielectric layer in sequence from bottom to top.
9. The etching method according to claim 8,
step S4 includes the following steps:
s40: etching the SHB layer and the ODL layer by a primary etching process, and transferring the contour of the contact hole defined on the photoresist layer to the SHB layer and the ODL layer;
s41: etching the second dielectric layer by a secondary etching process, transferring the outlines of the contact holes on the SHB layer and the ODL layer to the second dielectric layer, and adjusting the etching rate by adjusting the radio frequency power of an etching machine in the etching process;
s42: the first dielectric layer is etched and penetrates through the first dielectric layer by the three-time etching process and by adjusting the radio frequency of the etching machine, and the outline of the contact hole on the second dielectric layer is transferred to the first dielectric layer by the etching, so that a complete contact hole is formed.
10. The etching method according to claim 7 or 9, further comprising step S5, wherein step S5 is as follows: and cleaning the residual photoresist and polymer in the contact hole by using gas.
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| CN202210077313.1A CN114496913A (en) | 2022-01-24 | 2022-01-24 | Etching structure and method for contact hole of integrated circuit |
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| CN202210077313.1A CN114496913A (en) | 2022-01-24 | 2022-01-24 | Etching structure and method for contact hole of integrated circuit |
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