JPWO2007116515A1 - Semiconductor device and manufacturing method thereof, dry etching method, wiring material manufacturing method, and etching apparatus - Google Patents

Abstract

Using a resist mask formed using ArF exposure technology and having a pattern width and / or a pattern spacing of 32 to 130 nm, a halogenated carbon compound gas (provided that halogen is at least 2 of F, I and Br) A semiconductor device comprising a step of dry etching the thin film using at least one of I and Br in an atomic composition ratio of 26% or less of the total amount of halogen atoms to transfer a pattern to the thin film. Etching can be performed without damaging the resist mask for ArF exposure. The underlying material is dry-etched using the thin film having the transferred pattern as a mask.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, by enabling etching without damaging a fragile ArF exposure resist, there is a problem of line edge roughness (also referred to as LER or striation). The present invention relates to a semiconductor device and a method for manufacturing the same that can form a fine pattern of 130 nm or less with high accuracy by solving the above. The present invention also relates to a dry etching method capable of etching a fragile ArF exposure resist without damaging it and a method for producing a wiring material using this dry etching method.

  In recent years, along with higher integration and higher speed of LSI, semiconductor devices have been miniaturized and multilayered. As an exposure method in LSI manufacturing in this case, as represented by an ArF exposure method, a method using a laser having a short wavelength (for example, an excimer laser) is used. Thus, for example, a mask pattern is transferred to a resist material made of methacrylic resin, acrylic resin, or the like to form a resist mask, and the film covered with the resist mask is dry-etched, for example, a wiring hole or groove And so on. In such fine processing, high processing accuracy is required to obtain precise etching shapes in the lateral and depth directions. Therefore, since etching is performed while increasing anisotropy, a technique is known in which dry etching is performed by introducing a predetermined etching gas into a plasma atmosphere (see, for example, Patent Document 1).

  By the way, it is known that a compound having no benzene ring is used as a resist material used in the ArF exposure method in order to provide transparency in the wavelength region of vacuum ultraviolet light (see, for example, Non-Patent Document 1). When this resist material is exposed using an ArF laser, it becomes brittle and has a low plasma resistance compared to a resist material having a benzene ring (for example, a resist material for KrF exposure). For this reason, when dry etching is performed in a plasma atmosphere, the resist mask is exposed to an etchant in the plasma, and the edge of the patterned region becomes rough due to the influence of ultraviolet light and ion bombardment emitted from the plasma discharge. This causes a problem that the periphery of the pattern shape is deformed.

15A to 15C and 15A to 15C are schematic views of a cross-sectional view and a top view of a semiconductor device showing a method of manufacturing a gate of a transistor in a conventional semiconductor device. According to this conventional gate manufacturing method, as shown in FIGS. 15A and 15A, first, a gate oxide film 152 is grown on the Si substrate 151 to a predetermined thickness, and then a film for a gate electrode is formed. For example, after forming a laminated film 153 of a polysilicon film 153a and a tungsten film 153b, an electric insulating film SiO ₂ film 154 for a hard mask is formed (deposited) by a known CVD method or the like. Then, after applying an antireflection film 155, an ArF exposure resist 156 (for example, TARF-P6111 manufactured by Tokyo Ohka Kogyo Co., Ltd.) based on an acrylic resin is applied and formed thereon. The resist film 156 is exposed by a known ArF exposure apparatus (for example, TWINSCAN-XT1400 manufactured by ASML), and a resist mask 156 having a pattern for the gate electrode is formed on the laminated film 153 for the gate electrode. In addition, as a thin film for a hard mask, an electrical insulating film such as a SiN film or a SiC film by a CVD method is generally used.

When the pattern of the resist mask 156 is transferred to the electrical insulating film 154 by dry etching the electrical insulating film 154 for hard mask covered with the resist mask 156 having such a pattern in a plasma atmosphere, the resist mask Since 156 is fragile, the end of the pattern may be distorted to change its shape, or a part of the resist may be thin, or sometimes a hole may be formed (resist LER). If the etching is continued in such a resist mask state, the shape of the pattern that is distorted, deformed, or has a peripheral defect is transferred to the hard mask 154 as shown in FIGS. 15B and 15B '. There is a problem that so-called striation occurs. For this reason, when the pattern is transferred from the hard mask 154b to the laminated film 153 for the gate electrode by further using the hard mask 154b in which the striation occurs, the patterns shown in FIGS. 15 (c) and 15 (c ′). As shown, the striation is transferred as it is to the laminated film 153 for the gate electrode. Such striations sometimes reach as large as 50 nm, so that it is impossible to satisfy the requirement for high etching accuracy.

  When the deformation called striation is 50 nm, a pattern having a line width of 200 nm as a design value is acceptable as a line pattern, but if the design is a line width of 130 nm or less, If there is a defect, the remaining line width is relatively unacceptable. This cannot be used in the manufacture of fine pattern semiconductor devices.

  As described above, a material structure in which polysilicon or tungsten is laminated thereon is usually used as the gate of the transistor. In this case, since the gate length Lg is an important manufacturing parameter that determines a threshold voltage for distinguishing between ON and OFF when the transistor operates, it is necessary to accurately control the gate length Lg. If striation, which is a deformation of the pattern edge, occurs during the etching of the gate material, a distribution of the gate length Lg is formed in one gate. As a result, transistors with mixed Lg lengths are connected in parallel, so that the threshold voltage of the transistors becomes broad and a sharp on / off characteristic cannot be obtained.

  When the threshold voltage becomes broad, it is necessary to provide a margin for the operating voltage of the transistor, so that the power supply voltage is designed to be high, resulting in an adverse effect of increasing power consumption. Also, if there is a dispersion of the center value of the threshold voltage, it is necessary to design a long logic cycle in order to match the operation timing, so high speed operation cannot be expected. The high power supply voltage and the slow logic cycle do not meet the recent demand for product design for high integration, high speed and low power consumption. Therefore, it is important to process with a small value of the gate length Lg distribution in one gate.

  Because of the above background, control of the line width in gate fabrication is important. However, when the pattern is transferred to the resist by ArF exposure and the gate material is directly etched using the pattern as a mask, the resist as the mask must be designed to be thicker than the thickness of the material to be etched. In this thick design, the depth of focus DOF (Depth of Focus) is smaller than the resist thickness, so that there is a part that is out of focus in the depth direction of the resist, so that accurate pattern transfer cannot be expected. Happens. As a method of avoiding this problem, conventionally, a method of transferring a resist pattern to a hard mask having high etching resistance using a thin resist as a mask has been employed. However, if the resist is thin, striations occur when the hard mask is etched, and the striations are transferred to the hard mask, resulting in a distribution of the gate length Lg.

On the other hand, in the case where Cu wiring is formed by using, for example, a single damascene method according to the conventional ArF exposure technique and etching technique, as shown in FIG. 16A, an SiO ₂ film is formed on the transistor preparation region 161 by a CVD method. Next, an SiN film 162b is deposited as an etching stopper layer, an SiO ₂ film 162c is deposited, and an SiN film 162d is deposited again as a CMP stopper layer, thereby forming an interlayer insulating film 162. . Next, an ArF resist mask (not shown) having a wiring pattern is formed on the interlayer insulating film 162 using a known ArF exposure technique in the same manner as the above-described gate manufacturing method. Then, the interlayer insulating film 162 covered with the resist mask for ArF exposure is dry-etched in a plasma atmosphere, and the wiring pattern is transferred to the interlayer insulating film 162, whereby grooves or holes for embedding the metal wiring material ( A hole) pattern is formed in the interlayer insulating film 162. In the groove and hole formed here, TaN163 or the like is formed as a barrier metal by a known sputtering method, and then a Cu film is formed by a Cu plating method to embed a metal wiring material. Finally, the Cu wiring 164 is completed by applying a known CMP method.

In this way, when the Cu wiring 164 is formed by applying the conventional pattern transfer method, striations occur in holes, grooves, etc., as shown in FIG. For this reason, as shown in FIG. 16 (c), a deep constricted portion 165 is formed at the edge of the hole or groove pattern of the SiO ₂ film 162c constituting the interlayer insulating film, and the barrier metal 163 sufficiently enters there. As a result, there is a problem that the barrier performance becomes insufficient, and Cu 164 as a wiring material penetrates and diffuses into the thin film and short-circuits between adjacent wirings. When the degree of this short circuit is light, it causes current leakage, and when there is a change over time, it also causes product market failure. Here, the market defect of a product means that a product with a semiconductor device is defective during a period in which the product is distributed in the market.

  If even a part of the semiconductor wiring is thin, disconnection is likely to occur at that part. To prevent the fineness from falling below a certain value, the wiring is thickened at the design stage. However, the chip area of the semiconductor device is increased correspondingly, and the number of design chips that can be taken from one wafer is reduced, which increases the cost. For this reason, it is necessary to produce a product whose finished line width does not vary.

  When an interlayer insulating film (electrical insulating film) is dry-etched using a resist mask, the resist is first deformed, and the interlayer insulating film is etched with the deformed resist mask, so that the resist mask deformation is transferred as a film pattern deformation. (This transformation is a striation). Since the wiring of the semiconductor device is formed by embedding a barrier metal film and a Cu film in the groove in which the striation occurs, the striation in the groove is transferred as a wiring striation. Since the number of wiring layers of a semiconductor device exceeds 10 layers in a normal system LSI or memory device, it is important to reduce the striation that causes a decrease in yield, in order to reduce the manufacturing cost. .

In the case of transfer of a pattern having a line width of 200 nm or more and an interval between lines, occurrence of striation can be suppressed by using a resist having a benzene ring for KrF exposure as a mask. The resist used for KrF exposure is highly resistant to ultraviolet irradiation by plasma generated in the chamber during dry etching and fluorine radicals generated by decomposition of C ₃ F ₈ as an etching gas. For this reason, the striation, which is an irregular deformation of the resist, is relatively small, and the design line width is larger than that of the striation, so that there is no problem. However, in the semiconductor generation of 130 nm or less, especially 100 nm or less, since the exposure technique using ArF laser is used, the resist structure at this time becomes a structure sensitive to ultraviolet irradiation and fluorine radicals. The alation becomes larger than the resist (compound containing a benzene ring) subjected to KrF exposure. Therefore, the ratio of the striation to the line width is increased, causing a problem that the manufacturing yield of the semiconductor device is reduced.

  In order to solve the above-mentioned striation problem, a technique for dry etching a film (interlayer insulating film) using a resist formed by an ArF exposure method as a mask by introducing a mixed gas containing a fluorocarbon gas into a low-pressure plasma atmosphere Has been proposed (see, for example, Patent Document 2). However, by performing dry etching at a low pressure, even if the occurrence of striation can be suppressed, the etching rate is lowered, so that the economical practicality is poor.

The present applicant, as a dry etching method of an interlayer insulating film that can achieve high etching processing accuracy by suppressing the occurrence of the striations, interlayer insulation covered with a resist mask formed using ArF exposure (photolithography) method The film is an etching gas and is a halogen-based gas (halogen is F, I, Br), and at least one of I and Br is an atomic composition ratio of 26% or less of the total amount of halogen, and the rest is F A dry etching method for an interlayer insulating film in which a hole or a groove is finely processed by dry etching in a plasma atmosphere while introducing a fluorocarbon compound gas has already been proposed (Japanese Patent Application No. 2004-294882). However, this prior application does not describe that this etching method is useful for manufacturing a semiconductor device that requires a pattern dimension of 130 nm or less.
Japanese Patent Laid-Open No. 11-31678 (Claims etc.) Japanese Patent Application No. 2004-56962 (for example, claims) Koji Nozaki and Ei Yano, FUJITSU Sei.Tech.J., 38,1 P3-12 (June 2002)

As described above, in the conventional semiconductor device, since the ArF exposure technique must be used as a method for manufacturing a semiconductor device including a fine pattern of 130 nm or less, particularly 100 nm or less, the gate length, the wiring width, or the contact hole Since the ratio of striation to the pattern dimension such as the diameter has increased, there has been a problem that the manufacturing yield of the semiconductor device is reduced.

In order to solve the above-mentioned problems of the prior art, the present invention is capable of etching a fragile ArF exposure resist mask without damaging even a fine pattern of 130 nm or less formed by using an ArF exposure technique. Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device which can suppress the occurrence of striations and improve the manufacturing yield.

  Another object of the present invention is to provide a dry etching method capable of etching without damaging a fragile ArF exposure resist and a method for producing a wiring material using the dry etching method.

In order to solve the above problems, a semiconductor device according to the present invention has a pattern obtained by dry-etching a thin film covered with a resist mask having a pattern formed using ArF exposure technology in a plasma atmosphere. In a semiconductor device including a transferred thin film, this thin film uses a resist mask having a pattern whose pattern width and / or the distance between the patterns is 32 to 130 nm, and carbon halide as an etching gas. From the resist mask by etching using a compound gas (provided that halogen is at least two of F, I and Br, and at least one of I and Br is an atomic composition ratio of 26% or less of the total amount of halogen atoms). It has a transferred pattern.

  In another semiconductor device according to the present invention, a thin film covered with a resist mask having a pattern formed by using ArF exposure technology is dry-etched in a plasma atmosphere to form a hard mask, and further etched to remove the hard mask. In a semiconductor device including a portion to which the pattern is transferred, the portion to which the pattern is transferred is a resist mask having a pattern whose pattern width and / or the interval between the patterns is 32 to 130 nm. A halogenated carbon compound gas (provided that halogen is at least two of F, I and Br, and at least one of I and Br is an atomic composition ratio of 26% or less of the total amount of halogen atoms). Transfer from the resist mask to the hard mask by etching used Is characterized by having a further pattern transferred from the hard mask.

  The method for manufacturing a semiconductor device according to the present invention includes a step of dry etching a thin film covered with a resist mask having a pattern formed using ArF exposure technology in a plasma atmosphere to transfer the pattern to the thin film. A thin film covered with a resist mask having a pattern whose pattern width and / or pattern spacing is 32 to 130 nm is used as an etching gas. Etching using a compound gas (provided that halogen is at least two of F, I and Br, and at least one of I and Br is an atomic composition ratio of 26% or less of the total amount of halogen atoms) To do.

  According to the present invention, a resist pattern having a pattern width and / or a pattern-to-pattern spacing of 32 to 130 nm is used as a mask, and it is a stable compound as an etching gas and itself as an etchant for Si or the like. Since a fluorocarbon compound gas containing at least one of I and Br having a function is applied, when etching a fine pattern having a pattern dimension of 130 nm or less, occurrence of striation that becomes a large ratio to the pattern dimension occurs. In addition to being suppressed and reducing the density of the number of F atoms in the plasma atmosphere without relying on reducing the pressure during etching, damage to the resist mask is reduced. Therefore, since it is possible to transfer the pattern by plasma etching the thin film without damaging (deformation or defect) the resist, holes or grooves can be overcome while overcoming the problem of striation even with a fine pattern of 130 nm or less. It is possible to form a pattern such as. Therefore, precise thin film processing becomes possible.

  It is also possible to precisely etch the underlying material using the pattern transferred from the resist mask to the thin film as a hard mask, so it is possible to transfer the resist pattern to the underlying material with high accuracy via this hard mask. become able to.

  As the thin film, an electric insulating film can be applied. When the electric insulating film is an interlayer insulating film, a metal wiring material can be further embedded in the transferred pattern by a damascene method.

The electrical insulating film is preferably made of a material containing C or N, and the relative dielectric constant thereof is desirably in the range of 1.5 or more and 3.7 or less.

  It is also possible to etch the underlying material of the thin film using the thin film to which the pattern has been transferred as a mask, and this underlying material can be used as a gate electrode film or a Si substrate.

  As the gate electrode film, a conductive film containing W, Ti, Ta, Co, or Ni, a polysilicon film, or a stacked film of the conductive film and the polysilicon film can be used.

  Further, the present invention is suitable as a memory selected from DRAM and flash memory, a logic device, a system LSI, or a semiconductor device partially including these, and a manufacturing method thereof.

  The dry etching method of the present invention is a resist mask having a pattern formed by using an ArF exposure technique and having a pattern width and / or a distance between patterns of 32 to 130 nm. The covered thin film is used as an etching gas with a halogenated carbon compound gas (provided that halogen is at least two of F, I and Br, and at least one of I and Br is an atomic composition ratio of 26% or less of the total amount of halogen atoms) The pattern is transferred to the thin film by dry etching in a plasma atmosphere.

  In the dry etching method described above, it is possible to precisely etch the underlying material using the pattern transferred from the resist mask to the thin film as a hard mask. It becomes possible to transfer accurately. As the thin film, an electric insulating film can be applied. When the electric insulating film is an interlayer insulating film, a metal wiring material can be further embedded in the transferred pattern by a damascene method. The electrical insulating film is preferably made of a material containing C or N, and the relative dielectric constant thereof is desirably in the range of 1.5 or more and 3.7 or less.

  It is also possible to etch the underlying material of the thin film using the thin film to which the pattern has been transferred as a mask, and this underlying material can be used as a gate electrode film or a Si substrate. As the gate electrode film, a conductive film containing W, Ti, Ta, Co, or Ni, a polysilicon film, or a stacked film of the conductive film and the polysilicon film can be used.

  According to the present invention, when a semiconductor device is manufactured by etching a fine pattern having a pattern dimension of 130 nm or less, plasma etching of a thin film can be performed without damaging (deformation or defect) the resist mask. Even the following fine patterns enable precise thin film processing. Therefore, holes and grooves can be formed in the insulating film while overcoming the problem of striations, and the resist pattern can be precisely used as the underlying material by precisely etching the underlying material using the insulating film pattern as a mask. Can be transferred to. For this reason, since a hole, a groove, or the like without striation can be formed, it is possible to manufacture a semiconductor device including wiring with a precise dimension, a gate of a transistor, and the like. Therefore, even with a pattern of 130 nm or less, damage such as deformation around the pattern can be suppressed to 50 nm or less, so that a semiconductor device that functions as designed can be provided with high yield.

  In addition, since the effect of the etching gas used in the present invention does not depend on the pattern size, it is also effective in the manufacture of 90 nm generation, 65 nm generation, and 45 nm generation semiconductor devices.

  The best mode for carrying out a semiconductor device and a manufacturing method thereof, a thin film dry etching method and a wiring material manufacturing method using the dry etching method according to the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a schematic cross-sectional view showing an example of a semiconductor device according to the present invention. In the semiconductor device a of the present embodiment, a part of the surface of the silicon crystal 1 is covered with the gate oxide film 2, and element isolation (STI: Shallow) is included in the silicon crystal 1.
Trench Isolation) structure 3, deep source and drain 4, and shallow source and drain 5 are arranged. On the gate oxide film 2, a gate electrode 11 made of a laminated film of a polysilicon film 11a and a tungsten (W) film 11b is disposed. Tungsten wiring 12 electrically connected to these source and drain is connected to an upper layer wiring made of a barrier metal film (TiN film) 10 and copper (Cu) 13, and these tungsten wirings 12 are electrically connected to each other. A BPSG film 7 that insulates between the lower SiO ₂ film 6 and the upper SiN film 8. Similarly, a TEOS-SiO ₂ film 9 is formed on the SiN film 8 to insulate the upper wiring made of the barrier metal 10 and Cu 13 from each other.

  In the present invention, a fluorocarbon compound gas containing at least one of I and Br, which forms a stable compound and itself functions as an etchant for Si, is used as a gas for etching the insulating film. The fluorinated carbon compound gas is one of iodinated fluorinated carbon compound gas and brominated fluorinated carbon compound gas, or a mixed gas thereof.

  Since the semiconductor device a according to this embodiment includes a thin film having a pattern that is dry-etched without being damaged by the etching gas and transferred from the resist mask, the STI 3, the gate electrode 11, the W wiring 12, and the Cu wiring are provided. There is no striation in the pattern structure such as 13. Therefore, it is possible to include a transistor having a small distribution of the gate length Lg and a sharp on / off characteristic, and a wiring with reduced wiring leakage. In addition, the occurrence rate of defects based on changes over time such as Cu diffusion caused by striation is small.

  Here, the etching apparatus used in the present invention will be described with reference to FIG. The etching apparatus 21 uses discharge plasma (NLD plasma) generated in a region including a magnetic field of zero, and has a vacuum chamber 23 provided with a vacuum pumping means 22 such as a dry pump, a rotary pump, or a turbo molecular pump. .

  The chamber 23 includes an upper plasma generation chamber 23a having a cylindrical side wall 23c made of a dielectric material such as quartz and a lower substrate processing chamber 23b. Three magnetic field coils 24a, 24b and 24c are provided at predetermined intervals on the outside of the cylindrical side wall 23c to constitute a magnetic field generating means. The three magnetic field coils 24a, 24b, and 24c are attached to a yoke member 25 made of a high magnetic permeability material so as to surround the outside from above and below. In this case, a current in the same direction is supplied to the upper and lower magnetic field coils 24a and 24c, and a reverse current is supplied to the intermediate coil 24b. As a result, a position of zero magnetic field continuous inside the cylindrical side wall 23c is formed near the level of the intermediate coil 24b, and an annular magnetic neutral line is formed.

  The size of the annular magnetic neutral line can be set as appropriate by changing the ratio of the current flowing through the upper and lower coils 24a and 24c and the current flowing through the intermediate coil 24b. The position of can be appropriately set by the ratio of the currents flowing through the upper and lower magnetic field coils 24a and 24c. Further, as the current flowing through the intermediate coil 24b is increased, the diameter of the annular magnetic neutral wire is reduced, and at the same time, the gradient of the magnetic field at the position where the magnetic field is zero becomes gentler. An antenna 26a for generating a high-frequency electric field is provided between the intermediate coil 24b and the cylindrical side wall 23c, and this antenna is connected to a high-frequency power source 26b to constitute a magnetic field generating means. Then, NLD plasma is generated along the annular magnetic neutral line formed by the three magnetic field coils 24a, 24b and 24c.

  In the substrate processing chamber 23b, a substrate electrode 27 having a circular cross section, which is a substrate mounting portion on which the processing substrate S is mounted, is provided via an insulator 28 so as to face the surface formed by the annular magnetic neutral line. Yes. The substrate electrode 27 is connected to the second high-frequency power source 29b via the capacitor 29a, and becomes a floating electrode in terms of potential and has a negative bias potential.

The top plate 23d above the plasma generation chamber 23a is hermetically fixed to the upper part of the cylindrical side wall 23c, and is in a floating state in terms of potential to form a counter electrode. A gas introduction means 30 for introducing an etching gas into the chamber 23 is provided on the inner surface of the top plate. The gas introduction means 30 is connected to a gas source via a gas flow rate control means (not shown). Yes. In the etching apparatus 21 having such a configuration, a pattern without striation can be formed by introducing Ar and an etching gas (for example, C ₃ F ₇ I gas) to etch the thin film.

  Next, as an application example of the method for manufacturing a semiconductor device according to the present invention, a model process of a semiconductor manufacturing process including a transistor manufacturing process to a single damascene Cu wiring forming process will be described below with reference to FIGS. . There are processes such as washing and measurement between each process, but the explanation is omitted because it is not directly related to the present invention.

First, as shown in FIG. 3 (a), to prepare the silicon wafer 31, about to 10nm grown oxide film at about 900 ° C. using a known oxidation furnace, as shown in FIG. 3 (b), SiO ₂ A film 32 is formed. Next, as shown in FIG. 3C, a resist mask having a groove pattern of 100 nm is formed by using an ArF exposure method after forming a SiN film 33 with a thickness of about 90 nm at about 800 ° C. using a known LP-SiN furnace. 34 is formed.

As shown in FIG. 3D, the SiO ₂ film 32 and the SiN film 33 covered with the resist mask 34 are made of a halogenated carbon compound gas (however, the halogen is at least two of F, I and Br, At least one of I and Br is 26% or less of the total amount of halogen atoms in atomic composition ratio), and as shown in FIG. 33 is formed. At this time, no striation is allowed in the hard masks 32 and 33. By further etching the silicon wafer 31 which is the base material of the hard masks 32 and 33, a trench (groove) pattern 35 having a width of 100 nm is formed in the silicon wafer 31 as shown in FIG. Since the hard masks 32 and 33 to which the pattern is transferred are smooth, no striation occurs in the groove pattern 35.

After the silicon wafer 31 having the groove pattern 35 formed thereon is oxidized at about 900 ° C., as shown in FIG.
The groove pattern 35 is embedded with a Density Plasma (SiO ₂ film 41). Then, planarization is performed by applying a known HDP-CMP (Chemical Mechanical Polishing) (FIG. 4B), and after an oxidation process at about 850 ° C., for example, a SiN peeling process using a known ICP etcher is performed. After the execution, as shown in FIG. 4C, a silicon wafer 31 having a planarized surface and an STI structure 35a is obtained by an oxide film removing process using dilute hydrofluoric acid (HF).

Next, as shown in FIG. 4D, a gate oxide film 42 is grown by an oxidation process at about 850 ° C., and as shown in FIG. After forming a W film 44 to a thickness of about 200 nm and laminating a gate electrode film, a hard mask PE-TEOS (tetraethoxysilane) -SiO ₂ film 45 is formed to a thickness of 200 nm. .

As shown in FIG. 4 (f), a gate electrode pattern 46 is formed by a gate exposure process using an ArF exposure method, and the above-described halogenated carbon compound gas (however, halogen is F, I) using this patterned resist mask 46. 2) using the etching apparatus 21 of FIG. 2 using 50% of the TEOS-SiO ₂ film 45 by using at least two of N and Br, and at least one of I and Br is 26% or less of the total amount of halogen atoms in terms of atomic composition ratio. Etching is performed for 300 nm including overetching to form a hard mask 45 shown in FIG. In this hard mask / etching step, no striation occurs, so that a hard mask 45 having a smooth shape can be formed.

  Next, as shown in FIG. 5A, the gate electrode 51 is completed by etching the W film 44 and the polysilicon film 43 with a known ICP etcher or the like as a gate etch. The resist pattern 46 is etched out (disappeared) during this etching. Also, here, since the pattern is transferred from the hard mask 45 formed by suppressing the occurrence of striation according to the present invention to the gate electrode 51, no striation is observed in the gate electrode 51.

Next, after performing an oxide film regrowth step at about 850 ° C., As: 1 × 10 ¹⁵ / cm ² is ion-implanted to form a lightly doped drain (LDD) 52 having a shallow source / drain (SD) implantation.

Thereafter, as shown in FIG. 5B, a SiN film 53 is grown by a PE-CVD process at about 400 ° C., and the side shown in FIG. 5C is used by RIE (Reactive Ion Etching). The wall 53c is formed. Then, As: 5 × 10 ¹⁵ / cm ² is ion-implanted using the side wall 53c as a mask, and annealing is performed at 850 ° C. for 30 minutes, thereby forming the source / drain 54.

  Next, as shown in FIG. 5D, after a PE-SiN film 55 is formed to a thickness of about 100 nm, a BPSG (boro-phospho silicate glass) film 56 is grown by 700 nm as shown in FIG. 5E. Then anneal at 800 ° C. Then, by applying known ILD-CMP, the BPSG film 56 is polished and removed so that the protrusions are eliminated, thereby forming a flattened first interlayer insulating film 56a as shown in FIG. .

Next, as shown in FIG. 6B, a TEOS-SiO ₂ cap film 61 is grown on the planarized insulating film 56a by a CVD method at about 400 ° C., and then shown in FIG. 6C. Thus, a resist mask 63 having a contact hole pattern 62 with a diameter of about 100 nm is formed by ArF exposure. The TEOS-SiO ₂ film 61 covered with the resist mask 63 is etched without generating striations by the above-described halogenated carbon compound gas, and subsequently the lower BPSG film 56a, PE-SiN film 55, and gate oxide film 42 is also etched to form a contact hole 64 as shown in FIG.

  The resist mask 63 is peeled off by a known ashing method, and as shown in FIG. 7A, a TiN film is formed as a barrier metal 71 with a thickness of about 20 nm by CVD. Then, as shown in FIG. The contact hole 64 is embedded by forming a W film 72 with a thickness of about 50 nm. Subsequently, by using a known W-CMP method, the barrier metal 71 is used as a stopper to remove the excess W film, and then the barrier metal film 71 is also removed, thereby forming a W plug 73 as shown in FIG. To do. These W plugs establish electrical connection between the source / drain 54 and the gate electrode 51. A contact plug to the gate electrode 51 is not shown.

  A method for forming a Cu wiring in the transistor thus formed by a single damascene process will be described below. As shown in FIG. 7D, first, a PE-SiN cap film 74 is grown at about 400 ° C. by about 50 nm by a known plasma CVD method.

Similarly, as shown in FIG. 8A, a TEOS-SiO ₂ film 81 is formed to a thickness of about 250 nm by plasma CVD, and then a PE-SiN film 82 is grown to a thickness of 50 nm in the same manner as the PE-SiN film 74. Subsequently, an ArF resist film 84 having a wiring pattern 83 is formed with a thickness of about 200 nm using an ArF exposure method. The wiring pattern 83 is a fine wiring having a wiring width and / or a wiring interval of 130 nm or less, and may be 100 nm or less in order to promote further miniaturization.

Next, the pattern is transferred from the ArF resist mask 84 to the PE-SiN film 82 without causing striation by dry etching using the halogenated carbon compound gas according to the present invention (FIG. 8B). Further, as shown in FIG. 9A, the etching is continued up to the lower TEOS-SiO ₂ film 81. As a result, the wiring pattern is formed as a groove pattern in the interlayer insulating film 81 with smooth sidewalls without striations.

  Thereafter, the resist mask 84 is peeled off by a normal microwave asher, and further, SiN etching is performed by an ICP etching apparatus, thereby removing the SiN film 74 from the bottom of the wiring groove 83a as shown in FIG. 9B. .

  Next, as shown in FIG. 10A, a barrier metal film 101 is formed by forming a TaN film by about 10 nm using a known sputtering method and then forming a Ta film by about 15 nm. After forming a Cu film 102 to a thickness of about 1 μm by Cu plating, annealing at about 200 ° C. is performed. Finally, as shown in FIG. 10B, the excess Cu film is removed by polishing using the Ta film of the barrier metal film 101 as a stop layer using the CMP method. As a result, Cu 102b to be a metal wiring is buried in the pattern transferred from the resist mask 84, that is, the wiring groove 83a by the damascene method.

  According to the Cu wiring 102b according to the above-described embodiment, the barrier metal film 101 and the Cu film 102 are embedded in the groove pattern 83 formed smoothly by applying the etching method according to the present invention. Since there is no striation 165 like the Cu wiring 164, the diffusion of Cu into the interlayer insulating film 81 cannot occur. Therefore, in the semiconductor device a according to the present embodiment, the occurrence of defects such as inter-wiring leakage due to Cu diffusion due to the striation 165 in the conventional Cu wiring 164 is reduced to a wiring width and / or wiring interval of 130 nm or less. Since even the pattern can be completely prevented, the manufacturing yield of the semiconductor device can be remarkably improved.

Here, the etching gas used in the present invention will be described in detail. In the present invention, as described above, as the gas for etching the insulating film, a fluorocarbon compound gas containing a stable compound and containing at least one of I and Br that itself has a function as an etchant for Si is used. The fluorinated carbon compound gas is one of iodinated fluorinated carbon compound gas and brominated fluorinated carbon compound gas, or a mixed gas thereof.

The iodinated fluorocarbon compound gas and / or brominated fluorocarbon compound gas is _expressed as C _n (Hal) _{2n + 2} (wherein Hal represents a halogen atom, n = 1 to 3). Preferably, in CF ₃ I, CF ₃ Br, C ₂ F ₅ I, C ₂ F ₅ Br, C ₃ F ₇ I, C ₃ F ₇ Br, C ₃ F ₆ I ₂ , C ₃ F ₆ Br ₂ It is preferable that the mixed gas contains at least one selected from the above or two or more selected from these fluorocarbon compound gas and HI or Br. When the number of n exceeds 3, problems such as contamination of the chamber occur during etching, which is not practical.

The etching gas may also be used brominated fluorocarbon compound gas such as C ₂ F ₄ iodination fluoride such as I ₂ carbon compound gas and C ₂ F ₄ Br _2. In this case, CF ₄ gas or the like is added and used so that the atomic composition ratio is 26% or less of the total amount of halogen.

Further, the etching gas is at least one of HI and HBr, and a perfluorocarbon compound such as tetrafluoroethylene (C _n (Hal) _2n ( _where Hal represents a halogen atom, n = 1 to 3)) A mixed gas with a gas may be used, and a mixed gas of CF ₃ I and a fluorocarbon compound or a mixed gas of CF ₃ Br and a fluorocarbon compound may be used as an etching gas.

The etching gas may be a mixed gas of CF ₄ and C ₂ F ₄ I ₂ or C ₂ F ₄ Br ₂ , or a mixed gas of at least one of HI and HBr and a fluorocarbon compound. , CF ₃ I and a perfluorocarbon compound may be used as a mixed gas, or CF ₃ Br and a perfluorocarbon compound may be used as a mixed gas.

  In order to prevent the etched holes and grooves from being filled by adjusting the deposition amount of the reaction product by etching according to the present invention, the etching gas is 3% of the total flow rate of the gas introduced into the chamber. It is preferable to add about 15% oxygen. In this case, if it is less than 3%, the above effect cannot be achieved, and the amount of deposition cannot be adjusted. On the other hand, if it exceeds 15%, the ArF resist is damaged and etched.

As an insulating film to be etched using the etching apparatus 21, an oxide film such as SiO ₂ , a SiOCH material formed by spin coating such as HSQ or MSQ, a SiOC material formed by CVD, or A SiOF film formed by a CVD method, which is a low-k material having a relative dielectric constant of 1.5 to 3.7, and includes a porous material.

Examples of the SiOCH-based material include, for example, trade name NCS / Catalyst Chemical Industries, trade name LKD5109r5 / JSR, trade name HSG-7000 / Hitachi Chemical Co., trade name HOSP / Honeywell
Product name Nanoglass / Honeywell Electric, made by Electric Materials
Made by Materials, trade name OCD T-12 / manufactured by Tokyo Ohkasha, trade name OCD T-32 / manufactured by Tokyo Ohkasha, trade name IPS 2.4 / manufactured by Catalytic Kasei Kogyo Co., Ltd. And trade name ALCAP-S5100 / Asahi Kasei Co., Ltd., trade name ISM / ULVAC, etc.

Examples of the SiOC material include trade name Aurola 2.7 / Japan ASM Co., trade name Aurola 2.4 / Japan ASM Co., trade name Orion 2.7 / TRIKON, trade name Coral / Novellus, trade name Black Diamond / AMAT and others. Also, the brand name SiLK / Dow
Product name Porous-SiLK / Dow
Product name FLARE / Honeywell, manufactured by Chemical
Product name Porous FLARE / Honeywell
Product name GX-3P / Honeywell, manufactured by Electric Materials
It may be an organic low dielectric constant interlayer insulating film such as that manufactured by Electric Materials.

Here, the background to the present invention will be explained and the principle of the present invention will be considered. For example, using an inductively coupled (ICP plasma) etching apparatus (not shown), an etching gas containing a fluorocarbon gas (C _x F _y ) is introduced in a plasma atmosphere under an operating pressure of 1 to 3 Pa. When oxide film etching is performed (in this case, the Ar plasma density is ˜1 × 10 ¹¹ cm ⁻³ ), the resist mask is exposed to plasma and damaged, and the edge portion of the resist mask is roughened and deformed (edge (Roughness) occurs (referred to as striation). If the oxide film etching is continued in this state, the shape is transferred to the hole or groove, and the film striation occurs.

When the NLD device 21 used in the present invention is used, plasma discharge is possible even at a pressure (0.3-0.7 Pa) lower than a normal pressure (1 Pa or more). It has been found that when this is used to etch with C ₃ F ₈ gas at low pressure, striation can be suppressed. Generally, there are F, CF, CF ₂ , CF _3, etc. as the decomposition species generated by decomposing C ₃ F ₈ gas. Among these, molecular radicals other than F mainly function as polymerization precursors and are used for resists. The work as an etchant is low. From this, it was considered that the F atom radical reacts with the C═O group of the resist and other functional groups to weaken the resist mask. From this, in order to suppress striations, it was speculated that the reaction of eliminating this F radical was effective.

When C ₃ F ₇ I was used as an etching gas instead of C _x F _y , the resist etching rate decreased even at the same pressure. At this time, the resist etching rate decreases because the F radical, which is an etchant of the resist mask, reacts with I in the gas phase to form IF ₃ , IF ₅ , IF _7, etc., and the F radical decreases. Thought.

  In order to demonstrate the above considerations, specific examples are described below.

In the present invention, since the insulating film is basically etched without striation, in this embodiment, the insulating film is grown (deposited) on the silicon substrate (wafer) by a plasma CVD method from TEOS gas with a film thickness of 300 nm. ) Oxide film (TEOS-SiO ₂ ) was prepared.

  Then, after applying an anti-reflection film and an ArF exposure resist film so as to cover the insulating film, a wiring pattern including a groove having a width of 100 nm was formed using an ArF exposure technique. Then, the insulating film covered with the resist film having the wiring pattern was dry etched in a plasma atmosphere.

In the etching, Ar and etching gas C ₃ F ₇ I gas are introduced into the vacuum chamber 23 under a pressure of 2.67 Pa in the etching apparatus 21, and the insulating film is etched to form a 100 nm groove. The resist was peeled off. At this time, the flow rate of Ar was set to 230 sccm, the flow rate of C ₃ F ₇ I was set to 50 sccm, and the flow rate of oxygen was set to 20 sccm. The output of the high frequency power supply 26b connected to the plasma generating high frequency antenna coil 26a was set to 1 kW, the output of the high frequency power supply 29b connected to the substrate electrode 27 was set to 0.3 kW, and the substrate temperature was set to 10 ° C.

  FIG. 11A shows an SEM photograph of the obtained groove state observed from the upper surface of the substrate. A groove pattern 112a having a width of 100 nm was smoothly formed in the insulating film 111a, and a base crystal silicon crystal was observed at the bottom of the groove pattern 112a. Thus, in this example, it was confirmed that the occurrence of striation in the groove was suppressed to less than 3 nm. Therefore, according to the present invention, it is clear that a defect due to the striation of the wiring groove pattern does not occur, and it has been proved that the yield reduction due to the defect due to the striation can be completely prevented.

For comparison with the prior art, FIG. 11B shows a shape obtained by using C ₃ F ₈ gas instead of C ₃ F ₇ I gas under the same apparatus conditions. In the conventional example, the groove pattern 112b is formed with a width of about 100 nm in the insulating film 111b. However, since the striation 113 is generated in the groove, the wiring width with the design value of 100 nm is distributed as 100 nm ± 15% after etching. Confirmed to have. In the prior art, since the metal wiring material is buried in the wiring groove 112b in which the striation 113 is generated in this way, the yield in the wiring process is lowered due to the above-described Cu diffusion or the like.

Here, has been described the embodiment using the C _{3 F} 7 _I gas, applying a C 3 _F 7 _Br gas, striation-free groove pattern was obtained exhibit the same effects.

  In this embodiment, a method for forming a Cu wiring of a semiconductor device according to a Cu damascene method will be described. The basic part of the formation process for one layer will be described. When two or more layers of wiring are formed, the wiring can be formed by repeating or slightly modifying the following procedure (see FIGS. 12A to 12C).

(1) First, a 250 nm TEOS-SiO ₂ film 122a was formed on the Si substrate 121 at 400 ° C. by plasma CVD, and then a cap-SiN film 122b was grown to a thickness of 50 nm.
(2) on the SiN film 122b, the TEOS-SiO ₂ interlayer insulating film 122c plan to form a Cu interconnection, formed to a thickness of 200nm at 400 ° C. by a known plasma CVD method, further by plasma CVD 400 A plasma silicon nitride film (p-SiN) 122d as a CMP stopper was grown at a temperature of 30 nm at a temperature of 30 ° C.

(3) A resist for ArF exposure (trade name: UV-6 manufactured by Shipley) was coated on the SiN film 122d. In this case, in order to prevent reflection of light from the lower layer, an antireflection film (BARC (manufactured by Tokyo Ohka Kogyo Co., Ltd.)) was coated, and then a resist for ArF exposure was coated to a thickness of 300 nm.

(4) A 100 nm wide wiring pattern was transferred to this resist film using a known ArF exposure apparatus.
(5) The wiring pattern was developed as a groove.

(6) Next, the SiN film 122d and the SiO ₂ interlayer insulating film 122c were etched by 200 nm under the following process conditions to form a groove in the SiO ₂ film 122c.
Etching gas: C ₃ F ₇ I gas added with O ₂ and diluted with Ar gas. For comparison, a conventional example using C ₃ F ₈ gas instead of C ₃ F ₇ I gas was also carried out.
Ar gas flow rate: 230sccm
C ₃ F ₇ I gas flow rate: 50 sccm (C ₃ F ₈ gas flow rate is the same)
・ O ₂ gas flow rate: 20 sccm
・ Pressure: 2.67 Pa
・ Antenna high frequency power: 1kW
・ Substrate high frequency power: 0.3kW
・ Set substrate temperature: 10 ℃

(7) The resist was removed by ashing.
(8) After cleaning, a TaN film 123 was grown uniformly in a thickness of 10 nm in the formed groove by sputtering.
(9) A Cu seed layer was sputtered to 30 nm on this TaN film, and then known Cu plating was performed to form a Cu film having a thickness of 500 nm.

(10) The Cu film was polished and removed by the CMP method. In this case, Cu wiring 124 was obtained by stopping at the surface of the SiN film 122d.
(11) After cleaning, the upper surface of the obtained sample was observed.
The cross-sectional structure of the sample obtained through the above steps (1) to (11) is shown in FIG. 12 (a), the top view of the sample is shown in FIG. 12 (b), and the line X in FIG. A top view of the Cu wiring cut at −X is schematically shown in FIG.

  As is apparent from FIG. 12B, no striation was observed in the groove as a result of the etching performed according to the present invention. However, as shown in FIGS. 16B and 16C, the conventional etching was performed. When gas was used, striations 165 were generated in the grooves. If such a striation 165 is generated, when the trench is filled with the TaN film 163, the TaN 163 does not grow sufficiently in the deeply constricted portion, or it does not grow in this portion. I understood. The TaN film 163 has a function as a barrier film that prevents the Cu film from entering and diffusing into the interlayer insulating film 162c. If the function is insufficient, the semiconductor characteristics are deteriorated and the product yield is reduced. It becomes.

FIG. 16C schematically shows a case where the section taken along line XX in FIG. 16A is observed, the wiring cross section is observed from above, and the striation 165 portion is enlarged. In the experiment of the Cu wiring formed by the method of the present invention shown in FIG. 12, there is no striation. On the other hand, in the case of the conventional method using the C ₃ F ₈ gas shown in FIG. 16B, the wiring in which the striation 165 was generated was formed. It can be seen that part A in FIG. 16C is in a state in which Cu and the interlayer insulating film 162c are close to contact.

  On the other hand, in the embodiment according to the present invention, as is apparent from FIG. 12, since no striation occurs at the time of forming the groove, the manufacturing finished dimensions are constant within the allowable value over the entire wiring, so that there are no locally narrow portions. .

  If there is local variation in the wiring width, the design value of the line width is increased so that the narrowest part of the conventional technology does not fall below the design value. According to the present invention, since the line width can be designed with a small margin, the chip can be designed small. Therefore, the cost can be reduced as compared with the conventional case, and price competitiveness can be obtained.

  In addition, when a sharp dent due to striation occurs, a barrier metal film (TiN film, TaN film, etc.) becomes thin, and there is a problem that Cu diffuses from there. However, in the pattern transfer method according to this embodiment, In addition, since no dent is generated on the whole, the reliability of the function of the barrier metal as a Cu diffusion barrier is enhanced. Since defects caused by striations such as wiring according to the prior art can be prevented, the manufacturing yield of the semiconductor device a can be improved.

In the above etching, when the interlayer insulating film (film thickness: 200 nm) is etched, a mixed gas such as IH containing C ₃ F ₈ and I atoms is used as an etching gas instead of the C ₃ F ₇ I gas. It is also possible to use a method in which a C ₃ F ₇ I gas is generated by reacting in a reaction chamber when etching is performed, and this gas is introduced into a vacuum chamber. This method is technically possible and can be expected to have the same effect, but is not suitable for mass production because the number of parameters to be controlled increases.

  In this embodiment, a main process part for accurately manufacturing a gate included in the semiconductor device a according to the present invention will be described. 13A to 13C and 13A to 13C schematically show a cross-sectional view and a top view of the semiconductor device obtained in the main process. The transistor isolation process before gate fabrication, the gate insulation film fabrication process, the sidewall formation after the gate material is etched, and the source / drain diffusion process can be performed according to known methods and will not be described here.

Gate fabrication process:
(1) After a gate oxide film 132 is grown to a predetermined thickness on a silicon (Si) wafer 131, a doped amorphous Si (a-Si) film 133a is formed to a thickness of 200 nm at 500 ° C. by a known CVD method. I let you.
(2) On this a-Si film 133a, a tungsten (W) film 133b was grown by CVD at 400 ° C. to a thickness of 200 nm.

(3) Next, annealing was performed at 700 ° C. for 30 minutes. Thus, a gate electrode film 133 was formed.
(4) on the tungsten film 133b, a plasma oxide film (TEOS-SiO ₂₎ 134 as a hard mask, grown 200nm thickness at 400 ° C..

(5) A resist (trade name: UV-6, manufactured by Shipley) 136 for ArF exposure was coated on the hard mask 134. In this case, in order to prevent reflection of light from the lower layer, an antireflection film (BARC) 135 was coated, and then a resist 136 for ArF exposure was coated to a thickness of 300 nm.
(6) Next, an 80 nm wide gate pattern was transferred to the resist using a known ArF exposure apparatus. Thus, a resist mask having a pattern with a gate length of 80 nm was formed as shown in FIG.

(7) The plasma oxide film 134 was etched by 200 nm under the following process conditions.
Etching gas: C ₃ F ₇ I gas added with O ₂ and diluted with Ar gas. For comparison, a case where C ₃ F ₈ gas was used instead of C ₃ F ₇ I gas (prior art, see FIG. 15) was also carried out.
Ar gas flow rate: 230sccm
-C ₃ F ₇ I gas flow rate: 50 sccm (C ₃ F ₈ flow rate is the same)
・ O ₂ gas flow rate: 20 sccm
・ Pressure: 2.67 Pa
・ Antenna high frequency power: 1kW
・ Substrate high frequency power: 0.3kW
・ Setting board temperature: 10 ℃

(8) The resist 136 and the antireflection film 135 were peeled off (see FIG. 13B). At this time, striations of 3 nm or more were not recognized on the hard mask 134b, and the appearance was smooth.
(9) Next, by using HBr gas, the W film 133b is etched by 200 nm and the polysilicon film 133a is etched by 200 nm, thereby forming a gate electrode structure 137 as shown in FIG.
(10) Finally, it was cleaned and reoxidized while leaving the hard mask 134b.

  In the gate electrode structure 137 obtained through the above steps (1) to (10), since the pattern of the resist mask 136 is transferred without generating striation when the hard mask 134b is formed, the side wall is smooth. This pattern was further transferred by etching from the hard mask 134b having a gate electrode structure 137. Therefore, since the gate electrode structure 137 can be formed from the resist mask 136 with the gate length as designed, the generation of the distribution of the gate length Lg due to striation can be completely suppressed.

In this embodiment, a known thermal oxide film is used as the gate oxide film, but a high dielectric constant gate oxide film (for example, HfO _x ) may be used. In addition, although a laminated structure of an amorphous silicon film and a tungsten film is used as the gate structure, a polysilicon film may be used instead of the amorphous silicon film, or tungsten (W), titanium (Ti), and tantalum (Ta). Alternatively, a metal film (conductive film) containing cobalt (Co) or nickel (Ni) alone may be used. Furthermore, although the gate length is 80 nm in this embodiment, the present invention can also be applied to a finer pattern (possible to about 50 nm or less) that is resolved by ArF immersion exposure, electron beam exposure, or the like.

In the case of etching using a conventional C ₃ F ₈ gas, as shown in FIG. 15C, when viewed with one gate, the shortest and longest evaluations are ± 15% ((maximum-minimum). ) / (Maximum + minimum% display) gate length distribution has occurred, but in the pattern obtained in the present invention, the gate length distribution range is ± 5% as shown in FIG. The roughness of the edge portion was less than 5 nm.

  Therefore, according to the present invention, it is possible to provide a finished semiconductor device having a smaller gate length Lg distribution than conventional ones by etching by a method that suppresses the occurrence of striations. By using the present invention, it is possible to obtain a smooth side surface even in the manufacture of a transistor using the side surface of the Si crystal as a channel. Next, examples will be described.

  In this embodiment, a method for manufacturing a channel of a fin-type transistor will be described as a method for manufacturing a semiconductor device according to the present invention.

  14A to 14E and 14A to 14E are a cross-sectional view and a top view, respectively, schematically showing a method for manufacturing a channel of a fin-type transistor to which the present invention is applied. Since the fin-type transistor uses the side surface of the Si crystal as a channel, when striation occurs during etching of the Si crystal as in the prior art, there is a problem that the transistor characteristics deteriorate due to surface scattering.

  In this embodiment, as shown in FIG. 14A, after a thermal oxide film 142 is grown to 100 nm on a silicon wafer 141, an ArF exposure resist 144 is applied and formed after the antireflection film 143. A resist mask 144 having a fine pattern for channel formation was formed by patterning the resist film 144 using a known ArF exposure method. In order to make the channel potential follow the gate potential, this fine pattern is usually desirably 100 nm or less.

Next, the thermal oxide film 142 covered with the resist mask 144 was etched in a plasma atmosphere under the same process conditions as in Example 3 to form a hard mask 142b (see FIG. 14B). At this time, the occurrence of striation was not recognized in the hard mask 142b by the action of the present invention. Further, etching was continued using a mixed gas of chlorine (Cl ₂ ) and HBr capable of etching silicon as the etching gas system, and the pattern was transferred from the hard mask 142b to the silicon wafer 141 (see FIG. 14C). No striation of 3 nm or more was observed in the silicon wafer 141d to which the pattern was transferred from the hard mask 142b.

  Next, as shown in FIG. 14D, the fin-type channel 141d is produced by dissolving and removing the hard mask 142c with about 0.5% dilute hydrofluoric acid. Then, the gate oxide film 145 was grown by thermally oxidizing the silicon wafer 141 having the pattern of the fin-type channel 141d. Thus, a fin-type channel 141d was produced. A gate electrode made of polysilicon or the like is formed on the fin-type channel 141d according to a known method to complete a fin-type transistor. Since there are many known examples of the method for forming the gate electrode, it will not be described here.

  According to this embodiment, since the fine silicon line 141d formed in the silicon crystal 141 can be smoothly formed on the side wall without causing striations, a fin-type transistor using the side wall as a channel is formed. Control with high accuracy is possible.

  The present invention can be used as a memory selected from DRAM and flash memory, a logic device, a system LSI, or a semiconductor device partially including these, and a manufacturing method thereof.

FIG. 3 is a schematic cross-sectional view of a semiconductor device obtained by manufacturing a gate of a transistor by applying the dry etching method of the present invention. The arrangement sectional view showing roughly an example of the etching device used for the dry etching method of the present invention. 1 is a cross-sectional view of a semiconductor device showing a first step of the process for explaining an embodiment of a method for producing a semiconductor device according to the present invention; FIG. 4 is a cross-sectional view of a semiconductor device for explaining a next step of the process of FIG. 3. FIG. 5 is a cross-sectional view of a semiconductor device for explaining a next step of the process of FIG. 4. FIG. 6 is a cross-sectional view of a semiconductor device for explaining a next step of the process of FIG. 5. Sectional drawing of the semiconductor device for demonstrating the next process of the process of FIG. FIG. 8 is a cross-sectional view of a semiconductor device for illustrating a next step of the process of FIG. 7. FIG. 9 is a cross-sectional view of a semiconductor device for illustrating a next process of the process of FIG. 8. FIG. 10 is a cross-sectional view of a semiconductor device for explaining a wiring formation step next to the process of FIG. 9. The SEM photograph (a) which observed the state of the groove | channel obtained in Example 1 from the board | substrate upper surface, and the SEM photograph in the case of the prior art example performed for the comparison. Sectional structure (a) of the sample obtained in steps (1) to (11) of Example 2, a schematic top view (b), and a wiring cross section when cut along line XX in (a) are shown. FIG. 9A to 9C are cross-sectional views (a) to (c) and top views (a ′) to (c ′) of a semiconductor device for explaining a main process portion for manufacturing a gate included in the semiconductor device a according to the present invention. Sectional drawing (a) thru | or (e) and top view (a ') thru | or (e') which show typically the manufacturing method of the channel of the fin type transistor to which this invention is applied. Schematics of cross-sectional views (a) to (c) and top views (a ′) to (c ′) of a semiconductor device showing a conventional transistor gate manufacturing method. Sectional view (a) when Cu wiring is produced in accordance with the prior art, top view (b) and top view (c) enlarging the wiring section when cut along line (XX) in (a).

Explanation of symbols

1 Si crystal 2 Gate oxide film 3 STI 4 Deep source drain 5 Drain 6 SiO ₂ film 7 BPSG film 8 Cap film (SiN film)
9 TEOS-SiO ₂ cap film 10 Barrier metal film (TiN film)
DESCRIPTION OF SYMBOLS 11 Poly Si film (amorphous Si film) 12 Tungsten film 13 Cu wiring film 21 Etching device 22 Vacuum exhaust means 23 Chamber 23a Plasma generating chamber 23b Substrate processing chamber 23c Cylindrical side wall 23d Top plates 24a, 24b, 24c Magnetic field coil 25 York member 26a Antenna coil 27 Substrate electrode 30 Gas introduction means S Processing substrate 31 Silicon wafer 32 SiO ₂ film 33 SiN film 34 Resist mask 35 Groove pattern
35a STI structure 41 HDP-SiO ₂ film 42 Gate oxide film 43 Polysilicon film (doped amorphous Si film)
44 Gate electrode pattern 45 PE-TEOS-SiO ₂ film 46 Resist mask 47 Cu film 51 Gate electrode 52 LDD
53 SiN 53c Side wall 54 Source drain 55 PE-SiN film 56 BPSG film 56 a Insulating film 61 TEOS-SiO ₂ cap film 62 Contact hole pattern 63 Resist mask 64 TEOS-SiO ₂ film 71 Barrier metal 72 W film 73 W plug 74 PE -SiN cap film 81 TEOS-SiO ₂ film 82 PE-SiN film 83 wiring pattern 84 ArF resist film 83a groove 101 barrier metal film 102 Cu film 111a for wiring, 111b insulating film 112a, 112b groove pattern 113 striations 121 Si substrate 122a TEOS-SiO ₂ film 122b SiN film 122c TEOS-SiO ₂ interlayer insulating film 122d p-SiN film 123 TaN film 124 Cu wiring 131 Si wafer 132 gate oxide film 133 gate electrode film 133a a-Si film 133b W film 134 TEOS-SiO ₂ film 135 antireflection film 136 Resist 137 Gate electrode structure 141 Silicon wafer 142 Thermal oxide film 142b Hard mask 142c Hard mask 142d Silicon wafer 143 Antireflection film 144 Resist mask 145 Gate oxide film 1 51 Si substrate 152 Gate oxide film 153 Multilayer film 153a Polysilicon film 153b Tungsten film 154 SiO ₂ film 154b Hard mask 155 Antireflection film 156 Resist 157 Gate electrode 161 Transistor fabrication region 162 Interlayer insulating film 162a SiO ₂ film 162b SiN film 162c SiO ₂ films 162d SiN film 163 TaN 164 Cu wiring A Cu intruded portion

The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, by enabling etching without damaging a fragile ArF exposure resist, there is a problem of line edge roughness (also referred to as LER or striation). The present invention relates to a semiconductor device and a method for manufacturing the same that can form a fine pattern of 130 nm or less with high accuracy by solving the above. The present invention also relates to a dry etching method capable of etching without damaging a fragile ArF exposure resist, a method for producing a wiring material using the dry etching method, and an etching apparatus .

Claims (22)

In a method for manufacturing a semiconductor device comprising a step of dry etching a thin film covered with a resist mask having a pattern formed using ArF exposure technology in a plasma atmosphere and transferring the pattern to the thin film,
A thin film covered with a resist mask having a pattern whose pattern width and / or pattern spacing is 32 to 130 nm is used as an etching gas with a halogenated carbon compound gas (where halogen is F, I And at least one of Br and at least one of I and Br is 26% or less of the total amount of halogen atoms in atomic composition ratio). The method of manufacturing a semiconductor device according to claim 1, wherein the thin film is an electrical insulating film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the base material of the thin film is etched using the thin film to which the pattern is transferred as a mask. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the base material is a gate electrode film or a Si substrate. 5. The semiconductor according to claim 4, wherein the film for the gate electrode comprises a conductive film containing W, Ti, Ta, Co or Ni, a polysilicon film, or a laminated film of the conductive film and the polysilicon film. Device manufacturing method. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the electrical insulating film is made of a material containing C or N, and a relative dielectric constant thereof is in a range of 1.5 or more and 3.7 or less. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the electrical insulating film is an interlayer insulating film, and a metal wiring material is further embedded in the transferred pattern by a damascene method. 8. The method according to claim 1, wherein the method is applied to etching of a thin film when manufacturing a memory selected from a DRAM and a flash memory, a logic device, a system LSI, or a semiconductor device including a part thereof. 2. A method for manufacturing a semiconductor device according to item 1. In a semiconductor device provided with a thin film to which the pattern obtained by dry etching a thin film covered with a resist mask having a pattern formed by using ArF exposure technology in a plasma atmosphere is transferred.
The thin film uses a resist mask having a pattern with a pattern width and / or a pattern spacing of 32 to 130 nm, and a halogenated carbon compound gas (where halogen is F, I and It has a pattern transferred from the resist mask by etching using at least two types of Br, and at least one type of I and Br is 26% or less of the total amount of halogen atoms in terms of atomic composition ratio). Semiconductor device. The semiconductor device according to claim 9, wherein the thin film is an electrical insulating film, and further includes metal wiring embedded in the transferred pattern by a damascene method. 11. The semiconductor device according to claim 10, wherein the electrical insulating film is made of a material containing C or N, and has a relative dielectric constant in the range of 1.5 or more and 3.7 or less. A thin film covered with a resist mask having a pattern formed using ArF exposure technology is dry-etched in a plasma atmosphere to form a hard mask, and further includes a portion where the pattern is transferred from the hard mask by etching. In semiconductor devices,
The portion to which the pattern is transferred uses a resist mask having a pattern in which the pattern width and / or the interval between the patterns is 32 to 130 nm, and a halogenated carbon compound gas (however, a halogen gas) Is transferred from the resist mask to the hard mask by etching using at least two of F, I, and Br, and at least one of I and Br is 26% or less of the total amount of halogen atoms in terms of atomic composition ratio). A semiconductor device comprising a pattern further transferred from the hard mask. 13. The semiconductor device according to claim 12, wherein the portion to which the pattern is transferred is a film for a gate electrode or a Si substrate. 14. The semiconductor according to claim 13, wherein the gate electrode film is composed of a conductive film containing W, Ti, Ta, Co, or Ni, a polysilicon film, or a laminated film of the conductive film and a polysilicon film. apparatus. 15. The semiconductor device according to claim 9, wherein the semiconductor device includes a memory selected from a DRAM and a flash memory, a logic device, a system LSI, or a part thereof. In a method of dry etching a thin film covered with a resist mask having a pattern formed using ArF exposure technology in a plasma atmosphere,
A thin film covered with a resist mask having a pattern whose pattern width and / or pattern spacing is 32 to 130 nm is used as an etching gas with a halogenated carbon compound gas (where halogen is F, I And at least one kind of Br, and at least one kind of I and Br is an atomic composition ratio of 26% or less of the total amount of halogen atoms, and the pattern is transferred. . The dry etching method according to claim 16, wherein the thin film is an electrical insulating film. 18. The dry etching method according to claim 16, wherein the base material is etched using the thin film to which the pattern is transferred as a mask, and the pattern is transferred to the base material. 19. The dry etching method according to claim 18, wherein the base material is a gate electrode film or a Si substrate. 20. The dry etching according to claim 19, wherein the gate electrode film comprises a conductive film containing W, Ti, Ta, Co or Ni, a polysilicon film, or a laminated film of the conductive film and the polysilicon film. Method. 18. The dry etching method according to claim 17, wherein the electrical insulating film is made of a material containing C or N, and has a relative dielectric constant of 1.5 or more and 3.7 or less. An interlayer insulating film, which is an electrical insulating film covered with a resist mask having a pattern formed using ArF exposure technology, is dry-etched in a plasma atmosphere to transfer the pattern, and a metal wiring material is transferred to the transferred pattern In the manufacturing method of the wiring material to embed
A thin film covered with a resist mask having a pattern whose pattern width and / or pattern spacing is 32 to 130 nm is used as an etching gas with a halogenated carbon compound gas (where halogen is F, I And at least one of I and Br, and at least one of I and Br is an atomic composition ratio of 26% or less of the total amount of halogen atoms. A method for producing a wiring material, wherein a metal wiring material is embedded by a method.