CN112382607B - Method for manufacturing metal groove in copper process - Google Patents
Method for manufacturing metal groove in copper process Download PDFInfo
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- CN112382607B CN112382607B CN202011174770.XA CN202011174770A CN112382607B CN 112382607 B CN112382607 B CN 112382607B CN 202011174770 A CN202011174770 A CN 202011174770A CN 112382607 B CN112382607 B CN 112382607B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
Abstract
The invention discloses a method for manufacturing a metal groove in a copper process, which comprises the following steps: sequentially forming a first nitrogen-free anti-reflective coating (NFDARC), a metal hard mask layer, and a second NFDARC layer on the underlying structure; performing a first photolithography process to define a formation region of the first portion of the metal trench opening; performing a first etching process to form a first part of metal groove opening with the bottom stopping on the surface of the first NFDARC layer; performing a first ashing process to remove the first photoresist pattern; performing a second photoetching process to define a forming area of the second part of metal groove opening; performing a second etching process to form a second part of metal groove opening with the bottom stopping on the surface of the first NFDARC layer; and performing a second ashing process to remove the second photoresist pattern. The invention can form the opening of the metal hard mask layer of the metal groove by adopting 2 times of exposure and twice etching, and can avoid the adverse effect of the photoresist removing process on the critical dimension of the opening of the metal hard mask layer.
Description
Technical Field
The present invention relates to a method for manufacturing semiconductor integrated circuits, and more particularly to a method for manufacturing metal trenches in a copper process.
Background
With the development of processes, copper interconnect structures including copper interconnects formed in metal trenches and vias formed of copper filled in via openings are required to be formed using copper processes in back end of line (BEOL). Copper lines and vias are typically implemented using a damascene process, such as a dual damascene process, wherein metal trenches are defined using a metal hard mask layer, typically TiN, which requires the formation of a nitrogen-free antireflective coating (NFDARC) on the bottom and top of the TiN layer, respectively. Unlike the SiON composed DARC, NFDARC contains no nitrogen.
In the prior art, the opening of the metal hard mask layer is required to be formed before the metal trench is formed, so that the opening forming process of the metal hard mask layer is important, and when the critical dimension of the opening of the metal hard mask layer is offset, the critical dimension of the metal trench is offset. As the technology nodes of semiconductor devices shrink, for example, to below 14nm, the critical dimension of the metal trench often reaches below 64nm, and the opening of the metal hard mask layer under such dimension needs to be formed by two times of etching (2P 2E) with 2 times of exposure, and the critical dimension of the opening of the metal hard mask layer is easily shifted by the existing 2P2E process.
Disclosure of Invention
The invention aims to provide a manufacturing method of a metal trench in a copper process, which can form a metal hard mask layer opening of the metal trench by adopting 2 times of exposure and twice etching (2P 2E), and can avoid adverse effects of a photoresist removing process corresponding to 2 times of exposure on the critical dimension of the metal hard mask layer opening, so that the critical dimension of the metal hard mask layer opening formed by the two times of etching can be kept consistent, and finally, the metal trench with smaller critical dimension and better uniformity can be obtained.
In order to solve the technical problems, the method for manufacturing the metal trench in the copper process provided by the invention comprises the following steps:
providing a bottom structure needing to manufacture a metal groove, and sequentially forming a first NFDARC layer, a metal hard mask layer and a second NFDARC layer on the bottom structure.
And secondly, performing a first photoetching process and forming a first photoresist pattern, wherein a first opening of the first photoresist pattern defines a forming area of a first part of metal groove opening.
And thirdly, performing a first etching process to remove the second NFDARC layer and the metal hard mask layer at the bottom of the first opening and form a first partial metal trench opening with the bottom stopping on the surface of the first NFDARC layer.
And step four, performing a first ashing process to remove the first photoresist pattern, and preventing the first ashing process from changing the morphology of the first partial metal trench opening by utilizing the surface features of the first NFDARC layer stopped at the bottom of the first partial metal trench opening.
And fifthly, performing a second photoetching process and forming a second photoresist pattern, wherein the second opening of the second photoresist pattern defines a forming area of the second part of metal groove opening.
And step six, performing a second etching process to remove the second NFDARC layer and the metal hard mask layer at the bottom of the second opening and form a second part of metal trench opening with the bottom stopping on the surface of the first NFDARC layer.
And seventhly, removing the second photoresist pattern by performing a second ashing process, and preventing the second ashing process from changing the appearance of the second part metal trench opening by utilizing the surface characteristics of the second part metal trench opening, wherein the surface characteristics stop at the first NFDARC layer.
The further improvement is that the material of the metal hard mask layer is TiN.
In a further improvement, in the first photolithography process, a first organic underlayer and a first silicon-oxygen-based hard mask interlayer are further formed at the bottom of the first photoresist pattern.
In a further improvement, the first silicon oxide-based hard mask intermediate layer and the first organic bottom layer are etched first in the first etching process, and then the second NFDARC layer and the metal hard mask layer are etched.
The first ashing process removes both the first silicon oxide-based hard mask intermediate layer and the first organic underlayer.
A further improvement is that the first ashing process adopts an oxygen plasma etching process.
In a further improvement, in the second photolithography process, a second organic bottom layer and a second silicon-oxygen-based hard mask intermediate layer are further formed at the bottom of the second photoresist pattern.
In a further improvement, the second silicon oxide-based hard mask intermediate layer and the second organic bottom layer are etched in the second etching process, and then the second NFDARC layer and the metal hard mask layer are etched.
The second ashing process removes both the second silicon-based hard mask intermediate layer and the second organic underlayer.
A further improvement is that the second ashing process adopts an oxygen plasma etching process.
A further improvement is that the second opening and the first opening are offset from each other such that the first portion metal trench opening and the second portion metal trench opening are offset from each other.
In a further improvement, in the first step, the bottom structure includes an interlayer film formed on the semiconductor substrate, and the interlayer film is etched to form a metal trench under the definition of the first part metal trench opening and the second part metal trench opening.
A further improvement is that a copper layer is filled in the metal groove to form a copper connecting wire.
Further improvements include the step of forming a via formed at the bottom of selected regions of the metal trench.
The method is characterized in that a dual damascene process is adopted to form openings of the metal groove and the through hole, and then a copper layer is filled in the openings of the metal groove and the through hole simultaneously to form the copper connecting wire and the through hole simultaneously.
A further improvement is that a semiconductor device is formed on the semiconductor substrate.
Further improvement is that the process node of the semiconductor device is below 14 nm.
The copper wire is a back-end process, and the minimum width of the metal groove is up to below 64 nm.
The invention adopts a 2P2E process to form the metal hard mask layer opening defining the metal groove, namely the first part metal groove opening and the second part metal groove opening, in order to eliminate the influence of photoresist removing ashing process in the photoetching process on the first part metal groove opening and the second part metal groove opening on the two sides, the invention makes special setting for the two etching processes, the two etching processes are both set to directly etch the metal hard mask layer through the corresponding photoresist pattern as a mask and stop on the NFDARC layer at the bottom, namely the first NFDARC layer, so that the adverse influence of the ashing process, such as the ashing process adopting the oxygen plasma etching process, on the surface of the metal hard mask layer is eliminated, the adverse influence on the critical dimension of the opening of the metal hard mask layer is prevented, the critical dimension of the opening of the metal hard mask layer formed by the two etching processes is kept consistent, and finally, the critical dimension of the opening of the metal hard mask layer formed by the two etching processes is kept consistent, the critical dimension of the opening is smaller and the uniformity is better, and the critical dimension of the opening is suitable for the semiconductor device with the minimum width of the semiconductor groove of the semiconductor device below the metal groove of which is particularly equal to 14 nm.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIGS. 1A-1G are schematic views of a device structure at various steps in a conventional method for fabricating a metal trench in a copper process;
FIG. 2 is a flow chart of a method for fabricating a metal trench in a copper process according to an embodiment of the present invention;
fig. 3A-3D are schematic views of a device structure at each step in a method for fabricating a metal trench in a copper process according to an embodiment of the invention.
Detailed Description
The prior method for manufacturing the metal groove in the copper process comprises the following steps:
the technical proposal of the embodiment of the invention is obtained on the basis of analyzing the technical problems of the prior method, so the prior method is introduced before the technical proposal of the embodiment of the invention is introduced in detail,
as shown in fig. 1A to 1G, a schematic device structure of a conventional method for manufacturing a metal trench in a copper process is shown; the prior method for manufacturing the metal groove in the copper process comprises the following steps:
step one, as shown in fig. 1A, an underlying structure 101 requiring metal trench fabrication is provided, and a first NFDARC layer 102, a metal hard mask layer 103, and a second NFDARC layer 104 are sequentially formed on the underlying structure 101.
Typically, the material of the metal hard mask layer 103 is TiN.
Step two, as shown in fig. 1A, a first photolithography process is performed and a first photoresist pattern 107a is formed, where a first opening 108a of the first photoresist pattern 107a defines a formation region of a first portion of the metal trench opening 109a.
In general, in the first photolithography process, a first organic underlayer (Organic Under Layer, ODL) 105a and a first silicon-oxygen-based Hard Mask interlayer (SHB) 106a are further formed at the bottom of the first photoresist pattern 107 a. The first SHB layer 106a typically employs a bottom antireflective coating (BARC). The first ODL layer 105a employs a Carbon coating (Spin-On-Carbon, SOC), which is a polymer with high Carbon content.
Step three, as shown in fig. 1B, a first etching process is performed to remove the second NFDARC layer 104 at the bottom of the first opening 108a and form a first portion of the metal trench opening 109a with the bottom stopping on the surface of the metal hard mask layer 103.
Typically, the first etching process will etch the first silicon-based hard mask intermediate layer 106a and the first organic bottom layer 105a before etching the second NFDARC layer 104.
Step four, as shown in fig. 1C, a first ashing process is performed to remove the first photoresist pattern 107 a.
Typically, the first ashing process will remove both the first silicon-based hard mask intermediate layer 106a and the first organic underlayer 105 a.
The first ashing process adopts an oxygen plasma etching process.
The first ashing process tends to adversely affect, e.g., oxidize, the metal hard mask layer 103, thereby affecting the critical dimensions of the first portion metal trench opening 109a.
Step five, as shown in fig. 1D, a second photolithography process is performed and a second photoresist pattern 107b is formed, where the second opening 108b of the second photoresist pattern 107b defines a forming region of the second portion metal trench opening 109b.
In general, in the second photolithography process, a second organic underlayer 105b and a second silicon-based hard mask interlayer 106b are further formed at the bottom of the second photoresist pattern 107 b.
The second SHB layer 106b typically employs BARC. The second ODL layer 105b employs an SOC.
Step six, as shown in fig. 1E, a second etching process is performed to remove the second NFDARC layer 104 at the bottom of the second opening 108b and form a second portion of the metal trench opening 109b with the bottom stopping at the surface of the metal hard mask layer 103.
Typically, the second silicon-based hard mask intermediate layer 106b and the second organic bottom layer 105b will be etched first in the second etching process, followed by etching the second NFDARC layer 104.
Step seven, as shown in fig. 1F, a second ashing process is performed to remove the second photoresist pattern 107 b.
Typically, the second ashing process will remove both the second silicon-based hard mask intermediate layer 106b and the second organic underlayer 105 b.
The second ashing process adopts an oxygen plasma etching process.
The second opening 108b and the first opening 108a are offset from each other such that the first partial metal trench opening 109a and the second partial metal trench opening 109b are offset from each other.
The second ashing process is prone to adversely affecting, e.g., oxidizing, the metal hard mask layer 103, and since the surface of the first portion of the metal trench opening 109a is also affected in the second ashing process, the second ashing process affects the critical dimensions of both the first portion of the metal trench opening 109a and the second portion of the metal trench opening 109b.
The manufacturing method of the metal groove in the copper process comprises the following steps:
FIG. 2 is a flow chart showing a method for fabricating a metal trench in a copper process according to an embodiment of the invention; as shown in fig. 3A to 3D, a schematic device structure of the method for manufacturing a metal trench in a copper process according to an embodiment of the invention is shown; the method for manufacturing the metal groove in the copper process comprises the following steps:
step one, as shown in fig. 3A, an underlying structure 1 requiring metal trench fabrication is provided, and a first NFDARC layer 2, a metal hard mask layer 3, and a second NFDARC layer 4 are sequentially formed on the underlying structure 1.
In the embodiment of the present invention, the material of the metal hard mask layer 3 is TiN.
Step two, as shown in fig. 3A, a first photolithography process is performed and a first photoresist pattern 7a is formed, where the first opening 8a of the first photoresist pattern 7a defines a formation region of the first portion metal trench opening 9a.
In the embodiment of the present invention, in the first photolithography process, a first organic underlayer 5a and a first silicon-oxygen-based hard mask interlayer 6a are further formed at the bottom of the first photoresist pattern 7 a.
Step three, as shown in fig. 3B, a first etching process is performed to remove both the second NFDARC layer 4 and the metal hard mask layer 3 at the bottom of the first opening 8a and form a first portion of the metal trench opening 9a with the bottom stopping on the surface of the first NFDARC layer 2.
In the embodiment of the present invention, the first silicon-oxygen-based hard mask intermediate layer 6a and the first organic bottom layer 5a are etched first in the first etching process, and then the second NFDARC layer 4 and the metal hard mask layer 3 are etched.
Step four, as shown in fig. 3B, a first ashing process is performed to remove the first photoresist pattern 7a, and the first ashing process is prevented from changing the morphology of the first portion metal trench opening 9a by using the surface features of the first NFDARC layer 2 that the bottom of the first portion metal trench opening 9a stops.
In the embodiment of the present invention, the first ashing process removes the first silicon oxide-based hard mask intermediate layer 6a and the first organic underlayer 5a at the same time.
The first ashing process adopts an oxygen plasma etching process.
Step five, as shown in fig. 3C, a second photolithography process is performed and a second photoresist pattern 7b is formed, where the second opening 8b of the second photoresist pattern 7b defines a forming region of the second partial metal trench opening 9b.
In the embodiment of the present invention, in the second photolithography process, a second organic underlayer 5b and a second silicon-oxygen-based hard mask interlayer 6b are further formed at the bottom of the second photoresist pattern 7 b.
Step six, as shown in fig. 3D, a second etching process is performed to remove both the second NFDARC layer 4 and the metal hard mask layer 3 at the bottom of the second opening 8b and form a second portion of the metal trench opening 9b with the bottom stopping on the surface of the first NFDARC layer 2.
In the embodiment of the present invention, the second silicon-oxygen-based hard mask intermediate layer 6b and the second organic bottom layer 5b are etched first in the second etching process, and then the second NFDARC layer 4 and the metal hard mask layer 3 are etched.
Step seven, as shown in fig. 3D, a second ashing process is performed to remove the second photoresist pattern 7b, and the second ashing process is prevented from changing the morphology of the second portion metal trench opening 9b by using the surface features of the second portion metal trench opening 9b that stop at the first NFDARC layer 2.
In the embodiment of the present invention, the second ashing process removes the second silicon oxide-based hard mask intermediate layer 6b and the second organic underlayer 5b at the same time.
The second ashing process adopts an oxygen plasma etching process.
The second opening 8b and the first opening 8a are offset from each other such that the first partial metal trench opening 9a and the second partial metal trench opening 9b are offset from each other.
In the first step, the substructure 1 includes an interlayer film formed on a semiconductor substrate, and the interlayer film is etched to form a metal trench under the definition of the first portion metal trench opening 9a and the second portion metal trench opening 9b.
The following steps are also included: and filling a copper layer in the metal groove to form a copper connecting wire.
Further comprising the step of forming a via formed at the bottom of the selected region of the metal trench.
And forming openings of the metal groove and the through hole by adopting a dual damascene process, and then simultaneously filling a copper layer in the openings of the metal groove and the through hole to simultaneously form the copper connecting wire and the through hole.
A semiconductor device is formed on the semiconductor substrate.
The process node of the semiconductor device is below 14 nm.
The copper wire is a back-end process, and the minimum width of the metal groove is up to below 64 nm.
In the embodiment of the invention, the 2P2E process is adopted to form the openings of the metal hard mask layer 3 defining the metal grooves, namely the first part metal groove opening 9a and the second part metal groove opening 9b, in order to eliminate the influence of the photoresist removing ashing process in the two-side photoetching process on the first part metal groove opening 9a and the second part metal groove opening 9b, the embodiment of the invention particularly sets the two etching processes, wherein the two etching processes are set to directly etch the metal hard mask layer 3 through the corresponding photoresist pattern as a mask and stop on the bottom NFDARC layer, namely the first NFDARC layer 2, in this way, the adverse effect of the ashing process such as the ashing process adopting the oxygen plasma etching process on the surface of the metal hard mask layer 3 when the etching process after the two times of photoetching processes is stopped on the surface of the metal hard mask layer 3 can be eliminated, the adverse effect on the critical dimension of the opening of the metal hard mask layer 3 can be eliminated, the deviation of the critical dimension of the opening of the metal hard mask layer 3 is prevented, the critical dimension of the opening of the metal hard mask layer 3 formed by the two times of etching can be kept consistent, and finally, the metal groove with smaller critical dimension and better uniformity can be obtained.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (15)
1. The method for manufacturing the metal groove in the copper process is characterized by comprising the following steps of:
providing a bottom structure of a metal groove to be manufactured, and sequentially forming a first nitrogen-free anti-reflection coating, a metal hard mask layer and a second nitrogen-free anti-reflection coating on the bottom structure;
step two, performing a first photoetching process and forming a first photoresist pattern, wherein a first opening of the first photoresist pattern defines a forming area of a first part of metal groove opening;
step three, performing a first etching process to remove the second nitrogen-free anti-reflection coating at the bottom of the first opening and the metal hard mask layer and form a first part of metal groove opening with the bottom stopping on the surface of the first nitrogen-free anti-reflection coating;
step four, removing the first photoresist pattern by a first ashing process, and preventing the first ashing process from changing the morphology of the first partial metal trench opening by utilizing the surface characteristics of the first nitrogen-free anti-reflection coating stopped at the bottom of the first partial metal trench opening;
fifthly, performing a second photoetching process and forming a second photoresist pattern, wherein a second opening of the second photoresist pattern defines a forming area of a second part of metal groove opening;
step six, performing a second etching process to remove the second nitrogen-free anti-reflection coating at the bottom of the second opening and the metal hard mask layer and form a second part of metal groove opening with the bottom stopping on the surface of the first nitrogen-free anti-reflection coating;
and seventhly, removing the second photoresist pattern by a second ashing process, and preventing the second ashing process from changing the appearance of the second part metal groove opening by utilizing the surface characteristics of the first nitrogen-free anti-reflection coating stopped at the bottom of the second part metal groove opening.
2. The method of claim 1, wherein the step of forming the metal trench comprises: the material of the metal hard mask layer is TiN.
3. The method of fabricating a metal trench for a copper process of claim 2, wherein: in the first photolithography process, a first organic underlayer and a first silicon-oxygen-based hard mask interlayer are further formed at the bottom of the first photoresist pattern.
4. The method of fabricating a copper process metal trench as claimed in claim 3, wherein: etching the first silicon-oxygen-based hard mask intermediate layer and the first organic bottom layer in the first etching process, and then etching the second nitrogen-free anti-reflection coating and the metal hard mask layer;
the first ashing process removes both the first silicon oxide-based hard mask intermediate layer and the first organic underlayer.
5. The method of forming a metal trench in a copper process of claim 1 or 4, wherein: the first ashing process adopts an oxygen plasma etching process.
6. The method of fabricating a metal trench for a copper process of claim 2, wherein: in the second photolithography process, a second organic underlayer and a second silicon-based hard mask interlayer are further formed at the bottom of the second photoresist pattern.
7. The method of claim 6, wherein the step of forming the metal trench comprises: in the second etching process, the second silicon-oxygen-based hard mask intermediate layer and the second organic bottom layer are etched first, and then the second nitrogen-free anti-reflection coating and the metal hard mask layer are etched;
the second ashing process removes both the second silicon-based hard mask intermediate layer and the second organic underlayer.
8. The method of fabricating a copper process metal trench as claimed in claim 1 or 7, wherein: the second ashing process adopts an oxygen plasma etching process.
9. The method of claim 1, wherein the step of forming the metal trench comprises: the second opening and the first opening are offset from each other such that the first portion metal trench opening and the second portion metal trench opening are offset from each other.
10. The method of claim 9, wherein the step of forming the metal trench comprises: in the first step, the bottom layer structure comprises an interlayer film formed on the semiconductor substrate, and the interlayer film is etched to form a metal groove under the definition of the first part metal groove opening and the second part metal groove opening.
11. The method of claim 10, wherein the step of forming the metal trench comprises: and filling a copper layer in the metal groove to form a copper connecting wire.
12. The method of claim 10, wherein the step of forming the metal trench comprises: further comprising the step of forming a via formed at the bottom of the selected region of the metal trench.
13. The method of claim 12, wherein the step of forming the metal trench comprises: and forming openings of the metal groove and the through hole by adopting a dual damascene process, and then filling a copper layer in the openings of the metal groove and the through hole simultaneously to form a copper connecting wire and the through hole simultaneously.
14. The method of claim 10, wherein the step of forming the metal trench comprises: a semiconductor device is formed on the semiconductor substrate.
15. The method of claim 14, wherein the step of forming the metal trench comprises: the process node of the semiconductor device is below 14 nm;
the copper wire is a back-end process, and the minimum width of the metal groove is up to below 64 nm.
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| CN103811409A (en) * | 2012-11-12 | 2014-05-21 | 中微半导体设备(上海)有限公司 | Method for enhancing etching selectivity of low dielectric material for TiN hard mask |
| CN104124149A (en) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
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| US20050048788A1 (en) * | 2003-08-26 | 2005-03-03 | Tang Woody K. Sattayapiwat | Methods of reducing or removing micromasking residue prior to metal etch using oxide hardmask |
| US8916337B2 (en) * | 2012-02-22 | 2014-12-23 | International Business Machines Corporation | Dual hard mask lithography process |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103811409A (en) * | 2012-11-12 | 2014-05-21 | 中微半导体设备(上海)有限公司 | Method for enhancing etching selectivity of low dielectric material for TiN hard mask |
| CN104124149A (en) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN104934364A (en) * | 2014-03-19 | 2015-09-23 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of interconnection layer and manufacturing method of semiconductor device |
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