CN104124149A - Method for forming semiconductor device - Google Patents
Method for forming semiconductor device Download PDFInfo
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- CN104124149A CN104124149A CN201310157855.0A CN201310157855A CN104124149A CN 104124149 A CN104124149 A CN 104124149A CN 201310157855 A CN201310157855 A CN 201310157855A CN 104124149 A CN104124149 A CN 104124149A
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- side wall
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- mask layer
- column
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- 238000000034 method Methods 0.000 title claims abstract description 79
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000000463 material Substances 0.000 claims description 69
- 230000015572 biosynthetic process Effects 0.000 claims description 49
- 238000005530 etching Methods 0.000 claims description 37
- 229910052751 metal Inorganic materials 0.000 claims description 37
- 239000002184 metal Substances 0.000 claims description 37
- 229910052802 copper Inorganic materials 0.000 claims description 29
- 239000010949 copper Substances 0.000 claims description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- -1 copper nitride Chemical class 0.000 claims description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 230000003667 anti-reflective effect Effects 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 9
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 230000002829 reductive effect Effects 0.000 claims description 7
- 239000002194 amorphous carbon material Substances 0.000 claims description 5
- 239000003989 dielectric material Substances 0.000 claims description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 140
- 238000001259 photo etching Methods 0.000 description 22
- 239000003795 chemical substances by application Substances 0.000 description 15
- 230000000670 limiting effect Effects 0.000 description 11
- 238000001459 lithography Methods 0.000 description 11
- 238000000231 atomic layer deposition Methods 0.000 description 10
- 239000011159 matrix material Substances 0.000 description 8
- 125000006850 spacer group Chemical group 0.000 description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a method for forming a semiconductor device. The method comprises the steps of providing a substrate which comprises a dielectric layer; forming a hard mask layer on the dielectric layer; forming a strip-shaped opening in the hard mask layer; forming more than two columnar structures distributed in the length direction of the strip-shaped opening on the strip-shaped opening; forming side walls located on the hard mask layer on the sides of the columnar structures, enabling twice the thickness of the side walls in the length direction of the same strip-shaped opening to be smaller than the distance of the two adjacent columnar structures on the same strip-shaped opening; removing the columnar structures; utilizing the side walls and the hard mask layer to serve as masks, and forming through holes or grooves in the dielectric layer. According to the method for forming the semiconductor device, the through holes or the grooves are formed at the position occupied by the columnar structures on the same strip-shaped opening and at the position between the two adjacent side walls, so that one more through hole or groove is formed between the two adjacent columnar structures on the same strip-shaped opening, and accordingly a densely arranged through hole or groove array is formed.
Description
Technical field
The present invention relates to field of semiconductor technology, particularly a kind of formation method of semiconductor device.
Background technology
In semi-conductor industry, conventionally need to adopt photoetching technique, photoetching technique is utilized optics-chemical principle and chemical, physical etchings method, and circuitous pattern is delivered on single-crystal surface or dielectric layer, forms effective graphical window or functional graphic.
Traditional photoetching process resolution has arrived theoretical value, in order to cross the restriction of conventional lithography process theoretical resolution, improve the integration density of semiconductor device and form the structure with nano-grade size, high-resolution photoetching process has been developed and has been used, for example version-Ke-version-Ke (litho-etch-litho-etch, LELE) and version-version-Ke (LLE) photoetching technique.But while utilizing these fabrication techniques through holes (via), groove (trench), metal plug (metal plug) or metal interconnecting wires, formed through hole, groove, metal plug or metal interconnecting wires cannot reach required dense arrangement conventionally.
For this reason, need a kind of formation method of new semiconductor device, the problem existing to solve prior art.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor device, to improve the arranging density of through hole, groove, metal plug or metal interconnecting wires.
For addressing the above problem, the invention provides a kind of formation method of semiconductor device, comprising:
Substrate is provided, on described substrate, comprises dielectric layer;
On described dielectric layer, form hard mask layer;
In described hard mask layer, form one or more strip opening that runs through described hard mask layer thickness;
On described strip opening, form the column structure more than two distributing along described strip opening length direction, the upper surface of described column structure is higher than the upper surface of described hard mask layer;
In the side of described column structure, form and be positioned at the side wall on described hard mask layer, described side wall is less than the distance between adjacent two described column structures on same described strip opening along the double thickness on same described strip opening length direction;
Remove described column structure;
Take described side wall and described hard mask layer is mask, forms through hole or groove in described dielectric layer.
Optionally, also comprise: in described through hole or groove, form metal level, the upper surface of described metal level and the upper surface flush of described dielectric layer.
Optionally, described hard mask layer is metal hard mask layer, before forming described metal hard mask layer, also comprises: on described dielectric layer, form etching stop layer on described dielectric layer.
Optionally, the material of described metal hard mask layer comprises titanium nitride or copper nitride, and thickness is
the material of described etching stop layer comprises one or more combination in any of silica, silicon nitride, silicon oxynitride, carborundum and carbonitride of silicium.
Optionally, the material of described side wall comprises at least one or the multiple combination in any in silica, silicon nitride, silicon oxynitride, carborundum, carbonitride of silicium, titanium nitride and copper nitride.
Optionally, the material of described column structure comprises one or more combination in any of photoresist material, siliceous bottom anti-reflective layer material, amorphous carbon material and silicon nitride material, is highly 5nm～100nm.
Optionally, the width of described strip opening is 5nm～200nm.
Optionally, described strip opening is more than two, and the distance between two adjacent described strip openings is less than or equal to the twice of described side wall thicknesses.
Optionally, the shape of cross section of described column structure is circle, ellipse, rectangle or rhombus.
The present invention also provides the formation method of another semiconductor device, comprising:
Substrate is provided;
On described substrate, form one or more the first list structures;
In the side of described the first list structure, form and be positioned at the first side wall on described substrate;
Remove described the first list structure;
Form the sacrifice layer that covers described the first side wall and described substrate;
On described sacrifice layer, form one or more the second list structures, the length direction of the length direction of described the second list structure and described the first side wall is the angle that is more than or equal to 45 ° and is less than or equal to 90 °;
In the side of described the second list structure, form and be positioned at the second side wall on described sacrifice layer;
Described the second side wall of take is mask, sacrifice layer and described the first side wall described in etching, and remove described sacrifice layer, form a plurality of columns that matrix is arranged.
Optionally, the material of described the first list structure comprises one or more combination in any of photoresist material, siliceous bottom anti-reflective layer material, amorphous carbon material and silicon nitride material.
Optionally, the making material of described the first side wall comprises copper nitride, after forming described a plurality of columns, is also included in hydrogen atmosphere described a plurality of columns are carried out to annealing in process, makes described copper nitride be reduced into copper.
Optionally, also comprise the super low k dielectric materials of formation between described column.
Optionally, the making material of described the first side wall or described the second side wall comprises at least one or the multiple combination in any in silica, silicon nitride, silicon oxynitride, carborundum, carbonitride of silicium, titanium nitride and copper nitride.
Compared with prior art, technical scheme of the present invention has the following advantages:
In the formation method of a kind of semiconductor device provided by the present invention, first in the hard mask layer on dielectric layer, form one or more strip opening that runs through described hard mask layer thickness, then on described strip opening, form the column structure more than two distributing along described strip opening length direction, in the side of described column structure, form and be positioned at the side wall on described hard mask layer afterwards, thereby the occupied position of column structure and the position between adjacent two side walls all form through hole or groove on same strip opening, make increases between adjacent two column structures and forms a through hole or groove on same described strip opening, thereby form through hole or the groove array of dense arrangement, distance between adjacent through-holes or groove can be less than conventional lithography process limiting value.
In the formation method of another semiconductor device provided by the present invention, on substrate, form the first side wall, and form sacrifice layer and cover described the first side wall and described substrate, on described sacrifice layer, form the second side wall, then take described the second side wall as the first side wall described in mask etching, and then the position corresponding with the second side wall forms a plurality of columns that matrix is arranged in the first side wall, because the distance between the first side wall can be less than conventional lithography process limiting value, distance between the second side wall can be less than conventional lithography process limiting value, thereby in formed column array, distance between adjacent upright posts can be less than conventional lithography process limiting value, and column arrayed is regular, dense degree is high.
Accompanying drawing explanation
The schematic diagram of the formation method of the semiconductor device that Fig. 1 to Figure 13 provides for the embodiment of the present invention one;
The schematic diagram of the formation method of the semiconductor device that Figure 14 to Figure 23 provides for the embodiment of the present invention two.
Embodiment
As described in background, while utilizing the photoetching technique making through holes (via) such as version-Ke-version-Ke or version-version-Ke, groove (trench), metal plug (metal plug) or metal interconnecting wires, need to use mask plate twice, and formed through hole, groove, metal plug or metal interconnecting wires cannot reach required dense arrangement conventionally, be difficult to form through hole, groove, metal plug or the metal interconnecting wires of matrix distribution.
For this reason, the invention provides a kind of formation method of semiconductor device, first in the hard mask layer on dielectric layer, form one or more strip opening that runs through described hard mask layer thickness, then on described strip opening, form the column structure more than two distributing along described strip opening length direction, in the side of described column structure, form and be positioned at the side wall on described hard mask layer afterwards, thereby in the occupied position of column structure and same list structure, the position between adjacent two side walls all forms through hole or groove on same strip opening, make increases between adjacent two column structures and forms a through hole or groove on same described strip opening, thereby form through hole or the groove array of dense arrangement, owing to increasing between adjacent two side walls and forming an opening in same list structure, therefore final adjacent two through holes that form or the distance between groove can be less than conventional lithography process limiting value.
In the formation method of another semiconductor device provided by the invention, first on substrate, form the first list structure, then at the first strip texture edge, form the first side wall, and form sacrifice layer and cover described the first side wall and described substrate, on described sacrifice layer, form the second side wall, then take described the second side wall as the first side wall described in mask etching, form a plurality of columns that matrix is arranged, because the distance between the first side wall can be less than conventional lithography process limiting value, distance between the second side wall also can be less than conventional lithography process limiting value, thereby utilize in the formed column array in lap position between them, distance between adjacent upright posts can be less than conventional lithography process limiting value, and can form the metal plug of matrix distribution.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
The embodiment of the present invention one provides a kind of formation method of semiconductor device, below in conjunction with Fig. 1 to Figure 13, the present embodiment is illustrated.
Please refer to Fig. 1, substrate (not shown) is provided, on substrate, comprise dielectric layer 100.
The present invention does not limit substrate, concrete, the material of described substrate can be silicon or the SiGe of mono-crystalline structures or non crystalline structure, can be also silicon-on-insulator (SOI) or germanium on insulator (GOI), and can comprise other material, such as compounds such as undoped gallium arsenides.It is example that the present embodiment be take the silicon substrate of mono-crystalline structures.
The dielectric layer 100 forming on substrate can be interlayer dielectric layer, can be also top layer dielectric layer.The material of dielectric layer 100 can be silica material, can be also low k or super low-k materials.Please continue to refer to Fig. 1, on dielectric layer 100, form hard mask layer 120.
In the present embodiment, described hard mask layer 120 is metal hard mask layer, and its material can be titanium nitride or copper nitride.Adopt metal hard mask to make described hard mask layer 120, follow-up when etching media layer 100, have higher selection ratio, i.e. during etching, can carry out abundant etching and metal hard mask layer is not etched to dielectric layer 100.For reaching good masking effect, in the present embodiment, the thickness of hard mask layer 120 can be set to
when the hard mask layer 120 of described thickness range can guarantee etching on the one hand, bring into play the effect of mask, be unlikely to again on the other hand too thick, so that follow-up, can by modes such as planarizations, remove as early as possible.
In the present embodiment, because described hard mask layer 120 is metal hard mask layer, thereby when follow-up formation strip opening 121, easily dielectric layer 100 is also carried out to etching.Therefore,, before the present embodiment forms hard mask layer 120 on dielectric layer 100, etching stop layer 110 can first be formed on dielectric layer 100, as shown in Figure 1.So just can when etching hard mask layer 120, take etching stop layer 110 as etching end point, thus protective dielectric layer 100.The material of described etching stop layer 110 can be one or more combination in any of silica, silicon nitride, silicon oxynitride, carborundum and carbonitride of silicium.The thickness range of etching stop layer 110 can be
Incorporated by reference to reference to figure 1 and Fig. 2, in hard mask layer 120, form one or more strip opening 121 that runs through hard mask layer 120 thickness.
Fig. 2 is the schematic top plan view of structure shown in Fig. 1, and Fig. 1 cuts along A-A direction in Fig. 2 the cutaway view obtaining open.As can be seen from Figure 2, the present embodiment arranges three strip openings 121 that are parallel to each other, the width W 1 of described strip opening 121 can be 5nm～200nm, the length L 1 of strip opening 121 is at least twice pitch (Pitch, refer to the distance between two unit on chip or wafer, in the present embodiment, distance between two strip openings 121 i.e. a pitch), so that follow-up, on a strip opening 121, form at least two column structure 131(and please refer to Fig. 5), in the present embodiment, the length L 1 of strip opening 121 is three times more than pitch, so that three column structure 131(refer step four of follow-up formation).It should be noted that, in other embodiments of the invention, strip opening 121 can be one, more than two or four.When strip opening 121 is many, they are not yet defined as and are parallel to each other each other, but can be separately at an angle, such as being such as 30 °, 45 ° or 60 ° etc.
Incorporated by reference to reference to figure 5 and Fig. 6, on each strip opening 121, form three column structures 131 that distribute along strip opening 121 length directions, the upper surface of column structure 131 is higher than the upper surface of hard mask layer 120.
The forming process of described column structure 131 is incorporated by reference to reference to figure 3, Fig. 4, Fig. 5 and Fig. 6.As shown in Figure 3, first on hard mask layer 120 and etching stop layer 110, form mask material layer 130, then on mask material layer 130, form a plurality of photoetching agent patterns 141.In the present embodiment, photoetching agent pattern 141 is positioned at directly over strip opening 121, as shown in Figure 3.
Fig. 3 dissects along A-A direction in Fig. 4 the cutaway view obtaining.Fig. 4 is the vertical view of structure shown in Fig. 3, and as can be seen from Figure 4, the photoetching agent pattern 141 of patterning is matrix distribution on mask material layer 130.In the present embodiment, the width W 2 of photoetching agent pattern 141 is more than or equal to the width W 1 of described strip opening 121, and the length L 2 of photoetching agent pattern 141 is less than the length L 1 of strip opening 121.As shown in Figure 4, the length L 2 of photoetching agent pattern 141, much smaller than the length L 1 of strip opening 121, is arranged so that at least three photoetching agent patterns 141 can be set on a strip gab 121 like this.After forming the photoetching agent pattern 141 of patterning in Fig. 4, the described photoetching agent pattern 141 of take is mask, and etching mask material layer 130 forms column structure 131, as shown in Figure 5.Fig. 5 dissects along A-A direction in Fig. 4 the cutaway view obtaining, Fig. 6 is the vertical view of structure shown in Fig. 5, as can see from Figure 6, each column structure 131 is uniformly distributed in each strip opening 121, and this mode that is uniformly distributed can make the structure of formation more regular.
In the present embodiment, resulting column structure 131 is wide at the top and narrow at the bottom two sections, and wherein hypomere is just filled in strip gab 121.This be because, mask material layer 130 had originally been filled strip gab 121, thereby the hypomere width of column structure 131 (not mark) equates with the width W 1 of strip gab 121, and column structure 131 is shifted by photoetching agent pattern 141 and obtains, thereby the length L 3 of column structure 131 epimeres and width W 3 equate respectively with length L 2 and the width W 2 of photoetching agent pattern 141.In other embodiments of the invention, column structure 131 also can be made into wide (can be positioned at directly over strip gab 121 by photoetching agent pattern 141 is set, and photoetching agent pattern 141 equating to realize with strip gab 121 width) up and down.Described column structure 131 can be highly 5nm～100nm, as: 5nm, 50nm or 100nm, it is highly greater than the height of hard mask layer 120.
In the present embodiment, mask material layer 130 can be bottom anti-reflective layer material, and for example amorphous carbon material, can be also siliceous bottom anti-reflective layer material, can also be silicon nitride material, can also be the combination in any in them simultaneously.
It should be noted that, in other embodiments of the invention, described mask material layer 130 can be directly to be made by photoresist material, in this all situation, whole step needn't form photoetching agent pattern 141, only need to utilize exposure imaging technology directly mask material layer 130 to be formed to described column structure 131.
In the present embodiment, the cross section of column structure 131 is oval, but, in other embodiment of the present invention, the cross section of described column structure 131 can also be circle, rectangle or rhombus etc., these cross sections are that the column structure 131 of regular shape contributes to follow-up side wall 150(to please refer to Fig. 7) growth, but the present invention does not limit the shape of cross section of column structure 131.
Incorporated by reference to reference to figure 7 and Fig. 8, in the side of column structure 131 shown in Fig. 5 and Fig. 6, form side wall 150, side wall 150 is positioned on hard mask layer 120 simultaneously.Fig. 7 dissects along A-A direction in Fig. 8 the cutaway view obtaining, and Fig. 8 is the vertical view of structure shown in Fig. 7.
Please refer to Fig. 7, side wall 150 is formed on the side of column structure 131, and be positioned at hard mask layer 120 upper surfaces, side wall 150 can form by atomic layer deposition method (ALD), and the material of side wall 150 comprises at least one or the multiple combination in any in silica, silicon nitride, silicon oxynitride, carborundum, carbonitride of silicium, titanium nitride and copper nitride.The thickness of side wall 150 can be 2nm～100nm.
In the present embodiment, the thickness of side wall 150 is T, and the range mark on same strip opening 121 between adjacent two column structures 131 is S, and the range mark on same strip opening 121 between adjacent two side walls 150 is Δ H, has S=2T+ Δ H.The present embodiment is follow-up forms opening in the occupied position of column structure 131, and further form through hole or groove, and the position on same strip opening 121 between adjacent two side walls 150 can increase and form an opening, same through hole or the groove of further forming of opening increasing, thereby the distance that makes to be positioned at adjacent two through holes on same strip opening 121 or groove is less than pitch, little arriving is only the thickness T of side wall 150, thereby the through hole of producing or the dense degree of groove on strip opening 121 length directions high, can form through hole or groove that dense degree is high.
In the present embodiment, preferably, Δ H is set and please refer to Fig. 8 with the length L 3(of column structure 131) equate, so that follow-up, no matter be the column structure formed through hole of 131 correspondence position or groove, or the formed through hole of correspondence position or groove between adjacent two side walls 150 on same strip opening 121, size all equates.
The opening of strip described in the present embodiment 121 is three, and the column structure 131 on each strip opening 121 is also three.But in other embodiments of the invention, the number of the column structure 131 comprising on the number of strip opening 121 and each strip opening 121 can be other numerical value, two strip openings are for example set, four column structures are set on each strip opening, five strip openings are for example set again, five column structures are set on each strip opening, in a word, can be according to the number respective settings strip opening of the through hole that will form or groove and the number of column structure.
Distance in the present embodiment between adjacent two described strip openings 121 is less than or equal to the double thickness (2T) of side wall 150, be adjacent two strip opening 121 close together, same three column structures 131 in a lateral direction (for example wherein three column structures 131 are arranged in the A-A direction of Fig. 8) on same straight line, thereby side wall 150 simultaneously interconnect along the Width of strip opening 121.But in other embodiments of the invention, side wall 150 can not link together, for example, while only having a strip opening 121, or the distance of the column structure 131 between different strip openings 121 is while being greater than the double thickness (2T) of side wall 150.In fact, whether side wall 150 between different strip openings 121 interconnects, do not affect the present embodiment and form gap between the adjacent side wall 150 of same strip opening 121, thereby do not affect the realization of the present embodiment technical scheme, so the present embodiment can not considered side wall 150 connectivity problems between different strip openings 121.But the present embodiment is arranged in same three column structures 131 in a lateral direction on same straight line, this set not only can make the aperture array of follow-up formation more regular, and can, so that the distance between different strip opening 121 arranges littlely, the aperture array dense degree of follow-up formation be improved.
It should be noted that, it is thicker that in the present embodiment, side wall 150 is slightly tip, left and right, the shape that top and the bottom are thinner, as shown in Figure 8.This be because, the cross section ovalize of the column structure 131 of deposition side wall 150, thereby when deposition forms side wall 150, the material of side wall 150 is along the shape of cross section growth of column structure 131, and the cross section of the side wall 150 finally obtaining presents the flat structure similar to column structure 131 cross sections.
Incorporated by reference to reference to figure 7, Fig. 8 and Fig. 9, remove column structure 131.
Fig. 7 and Fig. 8 have shown at column structure 131 sides formation side walls 150, after this, have removed column structure 131, as shown in Figure 9.When column structure 131 is directly formed by photoresist or organic bottom antireflective layer, can adopt cineration technics to remove column structure 131, and when column structure 131 is made by silicon nitride, can adopt phosphoric acid solution to remove.
After removing column structure 131, originally column structure 131 positions have formed opening 122, and the position of the strip opening 121 on same strip opening 121 between two adjacent side walls 150 forms opening 123, as shown in Figure 9.Like this, originally on a strip opening 121, only form three photoetching agent patterns 141 and three column structures 131, but finally but can on a strip opening 121, form five openings (being respectively three openings 122 and two openings 123).
Please refer to Fig. 9 to Figure 13, take side wall 150 and hard mask layer 120 is mask, and in dielectric layer 100, etching vias 101.After the present embodiment has formed above-mentioned three openings 122 and two openings 123 on a strip opening 121, take side wall 150 and hard mask layer 120 is mask, by the dielectric layer 100 of the above-mentioned opening 122 of etching and opening 123 belows, form and be positioned at the through hole 101 on dielectric layer 100.It should be noted that, in the shown structure of Fig. 9, middle body is interconnection structure region, and periphery is non-interconnection structure region, the present embodiment is in interconnection structure region, to make corresponding through hole or groove, thereby, take side wall 150 before mask carries out etching, can cover by mask layer (not shown) is set the non-interconnection structure region of periphery, and then carry out etching, remove afterwards mask layer.
Please refer to Figure 10, Figure 10 is that structure shown in Fig. 9 is cut the schematic cross-section obtaining along B-B line, from Figure 10, can more be clear that three openings 122 and two openings 123 that same strip opening 121 distributes, between each opening only across side wall 150, distance between opening is little, so their close-packed density is high.
Please refer to Figure 11, Figure 11 is that structure shown in Fig. 9 is cut the schematic cross-section obtaining along C-C line, on same strip opening 121, between adjacent side wall 150, increase as can see from Figure 11 the opening 123 forming, owing to increasing, form opening 123, the density of opening is increased, space availability ratio improves, can within the scope of small size, produce a fairly large number of opening, follow-up these openings are used to form through hole or groove, thereby can within the scope of small size, produce a fairly large number of through hole or groove.
Please refer to Figure 12, Figure 12 is that structure shown in Fig. 9 is cut the schematic cross-section obtaining along D-D line, as can see from Figure 12, the position originally being occupied by column structure 131 has formed opening 122 after column structure 131 is removed, and opening 122 is for follow-up further formation through hole or groove.
Take side wall 150 and hard mask layer 120 in the process of mask etch through hole 101, and side wall 150 is removed by etching simultaneously.When hard mask layer 120 is metal hard mask layer, between dielectric layer 100 and hard mask layer 120, also comprise etching stop layer 110, therefore, also etching etching stop layer 110 in the lump in described process.
The dense degree of the through hole 101 that the present embodiment forms in dielectric layer 100 is high, this be because, except the strip opening 121(that occupies at original column structure 131 is with reference to figure 9) position (being Fig. 9 split shed 122 positions) formed through hole, on original same strip opening 121, between adjacent two side walls 150, position has also formed through hole 101.In Figure 13, refer to the direction of B-B shown in Fig. 9 or the direction parallel with B-B direction having formed three row through hole 101(row place directions), every row include five through holes 101, in these five through holes 101, in Figure 13, second of number and the 4th through hole 101 corresponding opening 122 etchings and increasing in original Fig. 9 from top to bottom of every row form, like this, from original row, only can form three through holes 101 and become five through holes 101 of formation, improve the density of through hole 101.
By step described above, the present embodiment forms through hole 101 arrays that adjacent spacing is less than conventional lithography process limiting value on same strip opening 121, and formed through hole 101 arrayed are regular, and dense degree is high.
It should be noted that, what the present embodiment formed in dielectric layer 100 is through hole 101, in other embodiments of the invention, can be also to form groove in dielectric layer 100.
After completing above-mentioned steps, the present embodiment can also continue to form metal level (not shown) in through hole 101, and remove metal level higher than part, hard mask layer 120 and the etching stop layer 110 of the upper surface of dielectric layer 100 by flatening process, make the upper surface flush of upper surface and the dielectric layer 100 of metal level.
The present embodiment is by above-mentioned steps process, in three strip openings 121, first form respectively three column structures 131, then in these nine column structures, 131 positions, form nine openings 123, if by existing technique, only can be according to corresponding nine through holes or the groove of forming of these nine openings 123.But the present embodiment is by the formation side wall 150 in column structure 131 sides, by controlling the thickness of side wall 150, on same strip opening 121, between adjacent two side walls 150, increase and formed an opening 122, thereby make a strip opening 121 form altogether five openings (being respectively three openings 122 and two openings 123), 15 openings in three strip openings 121, have been formed altogether, finally form 15 through holes 101, made the density of the through hole 101 of formation on strip opening 121 improve (15-9)/9=66.7%.
In other embodiments of the invention, suppose to have N bar strip opening 121, M column structure 131 of corresponding formation on each strip opening 121, like this, if only form opening in this M * N column structure 131 positions, only can form M * N opening, finally only can form M * N through hole or groove, but by the formation method of semiconductor device provided by the present invention, can in same strip opening 121, between adjacent two column structures 131, increase and form an opening, like this, just can form altogether (2M-1) * N opening, finally can form (2M-1) * N through hole or groove, can increase formation (M-1) * N opening, therefore the density of formed through hole or groove has improved (M-1)/M%.When M is 100, the density of formed through hole or groove has improved 99%, and M is larger, and density improves more.
The embodiment of the present invention two provides the formation method of another semiconductor device, and the formation method of semiconductor device the present embodiment being provided below in conjunction with Figure 14 to Figure 23 is illustrated.
In the present embodiment, for convenience of description, define a 3-D walls and floor, described 3-D walls and floor comprises that tri-of X, Y and Z are axially, and they are mutually vertical, the coordinate arrow of lower right-hand corner from each schematic diagram place of Figure 14 to Figure 23 axially can reference diagram, for example Figure 14 is X-Z schematic cross-section, and Figure 15 is X-Y schematic cross-section.
Please refer to Figure 14, substrate 200 is provided.
The material of substrate 200 can be silicon or the SiGe of monocrystalline or non crystalline structure, also can be silicon-on-insulator (SOI) or germanium on insulator (GOI), and can comprise other material, such as compounds such as undoped gallium arsenides, the present embodiment does not limit substrate 200.
Incorporated by reference to reference to Figure 14 and Figure 15, on substrate 200, form the first list structure 211.
In the present embodiment, the material of the first list structure 211 can be one or more combination in any of photoresist material, bottom anti-reflective layer material (for example amorphous carbon), siliceous bottom anti-reflective layer material and silicon nitride material.The forming process of the first list structure 211 can adopt technology well known to those skilled in the art, does not repeat them here.
Figure 15 is the schematic top plan view of structure shown in Figure 14, in the present embodiment, is provided with three the first list structures 211 that are parallel to each other, as shown in figure 15.In other embodiments of the invention, the first list structure 211 numbers can be also one, more than two or four, and the present invention does not limit the number of the first list structure 211.In the present embodiment, the width of the first list structure 211 can be 2nm～200nm, and the first list structure 211 of this width range is follow-up can form required column array.
Incorporated by reference to reference to Figure 16, in the first list structure 211 sides shown in Figure 14 and Figure 15, form and be positioned at the first side wall 221 on substrate 200.
The present embodiment can adopt atomic layer deposition method (ALD) to form the first side wall 221, concrete, adopt atomic layer deposition method to deposit the first spacer material layer (not shown) at the upper surface of upper surface, side and the substrate 200 of the first list structure 211, then by existing side wall, form technique and form the first side wall 221.The material of the first side wall 221 is copper nitride, and in the present embodiment, the width of the first side wall 221 can be 2nm～200nm.The present embodiment adopts copper nitride to make the first side wall 221, after final formation column, is also included in hydrogen atmosphere a plurality of columns are carried out to annealing in process, makes copper nitride be reduced into copper, forms copper column.
Please continue to refer to Figure 17, remove the first list structure 211 in Figure 16.
The present embodiment, after forming the first side wall 221, is removed the first list structure 211, retains the first side wall 221, as shown in figure 17.The first list structure 211 for different materials, can remove with distinct methods, for example, when the first list structure 211 is formed by photoresist or organic bottom antireflective layer, can adopt cineration technics to remove described the first list structure 211, and when the first list structure 211 is made by silicon nitride, can adopt phosphoric acid solution to remove.
Incorporated by reference to reference to Figure 18 and Figure 19, form sacrifice layer 230 and cover the first side wall 221 and substrate 200.
In the present embodiment, after removing the first list structure 211, form sacrifice layer 230 and cover the first side wall 221, the formation of sacrifice layer 230 can form smooth layer structure above the first side wall 221, so that follow-up continuation forms other each layer.In the X-Z cross section shown in Figure 18, can see, described sacrifice layer 230 is filled between the first side wall 221, and exceed 221 1 sections of height of the first side wall, in the Y-Z cross section shown in Figure 19, can see that equally described sacrifice layer 230 forms smooth layer structure above the first side wall 221.
Incorporated by reference to reference to Figure 18 and Figure 19, on sacrifice layer 230, form the second list structure 241, wherein the length direction of the length direction of the second list structure 241 and the first side wall 221 is the angle of 90 °.
It should be noted that, in other embodiments of the invention, the length direction of the length direction of the second list structure 241 and the first side wall 221 also can be other any angle that is more than or equal to 45 ° and is less than 90 °, such as 45 °, 60 ° or 75 ° etc.When being, the length direction of the second list structure 241 and the length direction of the first side wall 221 be more than or equal to 45 ° and while being less than the angular range of 90 °, the first side wall 221 be please refer to the present embodiment subsequent step by follow-up the second side wall 251() in overlapping part, the cross section of described lap can be the larger shape of odds ratio of area and girth.For example, in the present embodiment, the cross section of overlapping part can be rectangular.The cross section of conventionally wishing the column 222 of made has larger area girth ratio equally, thereby for forming the column 222 of required form, provides assurance in above-mentioned angular range.
In the present embodiment, known in conjunction with Figure 18 and Figure 19, the second list structure 241 has three, is strip, is distributed in sacrifice layer 230 tops.In other embodiments of the invention, the second list structure 241 numbers can be also one, more than two or four, and the present invention does not limit the number of the second list structure 241.Simultaneously, the width of the second list structure 241 can be 2nm～200nm, the second list structure 241 and the width range of above-mentioned the first list structure 211 of this width range match, and the width that the first list structure 211 can be further set equates with the width of the second list structure 241, thereby makes the column 222(of follow-up formation with reference to this specification subsequent step) cross section for square.
Incorporated by reference to referring to figures 20 through Figure 22, in the second list structure 241 sides shown in Figure 18 and Figure 19, form and be positioned at the second side wall 251 on sacrifice layer 230.
The present embodiment forms the second spacer material layer (not shown) above sacrifice layer 230, and the second spacer material layer is formed on the upper surface of top, side and the sacrifice layer 230 of the second list structure 241.The present embodiment can adopt atomic layer deposition method (ALD) to form described the second spacer material layer, its material can be at least one or the multiple combination in any in silica, silicon nitride, silicon oxynitride, carborundum, carbonitride of silicium and titanium nitride, but the material that need to guarantee the second spacer material layer is all different from the material of sacrifice layer 230 and the first side wall 221, and, preferably select with sacrifice layer 230 and compare the material with higher etching selection ratio with the material of the first side wall 221.
After forming the second spacer material layer, proceed side wall etch process and make the second spacer material layer form the second side wall 251, as shown in figure 22.In the present embodiment, the thickness of the second side wall 251 can be 2nm～200nm equally.
Please refer to Figure 22, the second side wall 251 is positioned at the upper surface of sacrifice layer 230, and, known according to foregoing description, the length direction of the first side wall 221 is mutually vertical with the length direction of the second side wall 251, although between the first side wall 221 and the second side wall 251 across sacrifice layer 230, but between two side walls, have correspondence position (between the upper and lower overlapping position), the projection of the correspondence position of the projection of the correspondence position of the first side wall 221 on sacrifice layer 230 and the second side wall 251 on sacrifice layer 230 overlaps.
Incorporated by reference to reference to Figure 22 and Figure 23, second side wall 251 of take is mask, etch sacrificial layer 230 and the first side wall 221, and remove sacrifice layer 230, form a plurality of columns 222 that matrix is arranged.
In the present embodiment, can adopt the plasma of halogen to come sacrifice layer 230 and described the second side wall 251 described in etching.When etching, the first side wall 221 only has the part of above-mentioned corresponding position to be retained, and after etching completes, the first side wall 221 is etched into column 222.Formed column 222 is the column 222 of copper nitride material.Then, can in hydrogen atmosphere, carry out annealing in process by column 222, make copper nitride be reduced into copper, form the column 222 of copper, concrete, can under the temperature conditions of 100 ° of C～400 ° C, anneal, form copper column 222.
The present embodiment adopts copper nitride to make described the first side wall 221, copper nitride is a kind of metallic compound, it can use Atomic layer deposition method to form, therefore can be used for forming the first side wall 221 that thickness is less, thereby guarantee the column 222 of follow-up formation dense arrangement, and copper nitride is easily reduced into copper, follow-uply easily column 222 is reduced into metal plug, thereby is particularly suitable for technical scheme of the present invention.
Through above-mentioned steps, the present embodiment has formed the closely spaced array of column 222, described column 222 is on the first side wall 221, and column 222 is to form in the corresponding position of above-mentioned the first side wall 221, and the vertically superposed part that this correspondence position is the first side wall 221 and the second side wall 251 is determined, due to the first side wall 221 and the second side wall 251 separately distance each other can be less than the limiting value of photoetching process, therefore in the array of the formed column 222 of the present embodiment, distance between adjacent upright posts 222 can be less than conventional lithography process limiting value, column 222 arrayed that form are regular, dense degree is high.
Although do not show in figure, after completing above-mentioned steps, the column 222(that the present embodiment can also continue in formation is the copper column of column 222 after can being to be reduced now) between form low k or super low k dielectric materials.Before this, first to remove sacrifice layer residual in said process 230, can adopt the plasma of oxygen base (O-) that residual sacrifice layer 230 and the second side wall 251 are removed, then can take physical vaporous deposition (PVD), chemical vapour deposition technique (CVD) or atomic layer deposition method (ALD) on the substrate 200 between column 222, to form low k or super low k dielectric materials.After forming low k or super low k dielectric materials, column 222 is converted into metal plug.
The formation method of two kinds of semiconductor device provided by the present invention adopts respectively the setting of strip opening and list structure, coordinate simultaneously and adopt side wall form technique and using side wall as mask, carry out etching method, the through hole that matrix is arranged, groove or metal plug have been formed, formed through hole, groove or metal plug are arranged regular, and dense degree is high.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with claim limited range.
Claims (14)
1. a formation method for semiconductor device, is characterized in that, comprising:
Substrate is provided, on described substrate, comprises dielectric layer;
On described dielectric layer, form hard mask layer;
In described hard mask layer, form one or more strip opening that runs through described hard mask layer thickness;
In described strip opening, form the column structure more than two distributing along described strip opening length direction, the upper surface of described column structure is higher than the upper surface of described hard mask layer;
In the side of described column structure, form and be positioned at the side wall on described hard mask layer, described side wall is less than the distance between adjacent two described column structures on same described strip opening along the double thickness on same described strip opening length direction;
Remove described column structure;
Take described side wall and described hard mask layer is mask, forms through hole or groove in described dielectric layer.
2. formation method as claimed in claim 1, is characterized in that, also comprises: in described through hole or groove, form metal level, the upper surface of described metal level and the upper surface flush of described dielectric layer.
3. formation method as claimed in claim 1, is characterized in that, described hard mask layer is metal hard mask layer, before forming described metal hard mask layer, also comprises: on described dielectric layer, form etching stop layer on described dielectric layer.
4. formation method as claimed in claim 3, is characterized in that, the material of described metal hard mask layer comprises titanium nitride or copper nitride, and thickness is
the material of described etching stop layer comprises one or more combination in any of silica, silicon nitride, silicon oxynitride, carborundum and carbonitride of silicium.
5. formation method as claimed in claim 3, is characterized in that, the material of described side wall comprises one or more the combination in any in silica, silicon nitride, silicon oxynitride, carborundum, carbonitride of silicium, titanium nitride and copper nitride.
6. formation method as claimed in claim 1, it is characterized in that, the material of described column structure comprises one or more combination in any of photoresist material, siliceous bottom anti-reflective layer material, amorphous carbon material and silicon nitride material, is highly 5nm～100nm.
7. formation method as claimed in claim 1, is characterized in that, the width of described strip opening is 5nm～200nm.
8. formation method as claimed in claim 1, is characterized in that, described strip opening is more than two, and the distance between two adjacent described strip openings is less than or equal to the twice of described side wall thicknesses.
9. formation method as claimed in claim 1, is characterized in that, the shape of cross section of described column structure is circle, ellipse, rectangle or rhombus.
10. a formation method for semiconductor device, is characterized in that, comprising:
Substrate is provided;
On described substrate, form one or more the first list structures;
In the side of described the first list structure, form and be positioned at the first side wall on described substrate;
Remove described the first list structure;
Form the sacrifice layer that covers described the first side wall and described substrate;
On described sacrifice layer, form one or more the second list structures, the length direction of the length direction of described the second list structure and described the first side wall is the angle that is more than or equal to 45 ° and is less than or equal to 90 °;
In the side of described the second list structure, form and be positioned at the second side wall on described sacrifice layer;
Described the second side wall of take is mask, sacrifice layer and described the first side wall described in etching, and remove described sacrifice layer, form column.
11. formation methods as claimed in claim 10, it is characterized in that, the material of described the first list structure and the second list structure comprises one or more combination in any of photoresist material, siliceous bottom anti-reflective layer material, amorphous carbon material and silicon nitride material.
12. formation methods as claimed in claim 11, it is characterized in that, the making material of described the first side wall comprises copper nitride, after forming described a plurality of columns, also be included in hydrogen atmosphere described a plurality of columns are carried out to annealing in process, make described copper nitride be reduced into copper.
13. formation methods as claimed in claim 10, is characterized in that, also comprise: on the substrate between described column, form super low k dielectric materials.
14. formation methods as claimed in claim 10, is characterized in that, the material of described the second side wall comprises one or more the combination in any in silica, silicon nitride, silicon oxynitride, carborundum, carbonitride of silicium, titanium nitride and copper nitride.
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| CN110364478A (en) * | 2018-03-26 | 2019-10-22 | 中芯国际集成电路制造(上海)有限公司 | The forming method of metal connecting structure |
| CN112382607A (en) * | 2020-10-28 | 2021-02-19 | 上海华力集成电路制造有限公司 | Method for manufacturing metal trench in copper process |
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| CN110233097B (en) * | 2018-03-06 | 2021-11-23 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN110349909B (en) * | 2018-04-03 | 2021-07-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| US10529570B1 (en) * | 2018-11-20 | 2020-01-07 | Nanya Technology Corporation | Method for preparing a semiconductor structure |
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| TW400605B (en) * | 1999-01-16 | 2000-08-01 | United Microelectronics Corp | The manufacturing method of the Shallow Trench Isolation (STI) |
| CN100499037C (en) * | 2006-09-04 | 2009-06-10 | 中芯国际集成电路制造(上海)有限公司 | Through-hole etching method |
| US7863655B2 (en) * | 2006-10-24 | 2011-01-04 | Macronix International Co., Ltd. | Phase change memory cells with dual access devices |
| CN101295643B (en) * | 2007-04-24 | 2010-05-19 | 中芯国际集成电路制造(上海)有限公司 | Through hole etching method and through hole mask |
| KR101061316B1 (en) * | 2007-09-28 | 2011-08-31 | 주식회사 하이닉스반도체 | Method of forming fine pattern of semiconductor device |
| CN101963755B (en) * | 2009-06-26 | 2012-12-19 | 罗门哈斯电子材料有限公司 | Self-aligned spacer multiple patterning methods |
| CN101847655B (en) * | 2010-04-22 | 2014-10-22 | 上海华虹宏力半导体制造有限公司 | Trench grate capable of improving trench grate MOS device performance and manufacture method thereof |
| CN102446703A (en) * | 2010-10-14 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Dual patterning method |
| CN102522370B (en) * | 2011-12-22 | 2015-12-02 | 上海华虹宏力半导体制造有限公司 | The formation method of contact hole |
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| CN110364478A (en) * | 2018-03-26 | 2019-10-22 | 中芯国际集成电路制造(上海)有限公司 | The forming method of metal connecting structure |
| CN112382607A (en) * | 2020-10-28 | 2021-02-19 | 上海华力集成电路制造有限公司 | Method for manufacturing metal trench in copper process |
| CN112382607B (en) * | 2020-10-28 | 2023-08-11 | 上海华力集成电路制造有限公司 | Method for manufacturing metal groove in copper process |
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