CN112368852A - 晶体管阵列 - Google Patents
晶体管阵列 Download PDFInfo
- Publication number
- CN112368852A CN112368852A CN201980043977.2A CN201980043977A CN112368852A CN 112368852 A CN112368852 A CN 112368852A CN 201980043977 A CN201980043977 A CN 201980043977A CN 112368852 A CN112368852 A CN 112368852A
- Authority
- CN
- China
- Prior art keywords
- pattern
- conductor
- source
- drain
- sub
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 195
- 239000010410 layer Substances 0.000 claims abstract description 62
- 238000000034 method Methods 0.000 claims abstract description 21
- 239000011529 conductive interlayer Substances 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims description 44
- 239000004065 semiconductor Substances 0.000 claims description 32
- 239000007789 gas Substances 0.000 claims description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 13
- 229910052760 oxygen Inorganic materials 0.000 claims description 13
- 239000001301 oxygen Substances 0.000 claims description 13
- 230000002093 peripheral effect Effects 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 8
- 229910052756 noble gas Inorganic materials 0.000 claims description 4
- 150000002835 noble gases Chemical class 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 21
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 229920000620 organic polymer Polymers 0.000 description 6
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 3
- 238000003491 array Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910018503 SF6 Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 235000006408 oxalic acid Nutrition 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000002985 plastic film Substances 0.000 description 1
- 229920006255 plastic film Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 239000002094 self assembled monolayer Substances 0.000 description 1
- 239000013545 self-assembled monolayer Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/80—Constructional details
- H10K10/82—Electrodes
- H10K10/84—Ohmic electrodes, e.g. source or drain electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/464—Lateral top-gate IGFETs comprising only a single gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
- H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/125—Active-matrix OLED [AMOLED] displays including organic TFTs [OTFT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
- H10K71/231—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/621—Providing a shape to conductive layers, e.g. patterning or selective deposition
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/13629—Multilayer wirings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Geometry (AREA)
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
一种生产器件的技术,该器件包括限定晶体管阵列的各层的堆叠并且包含一个或多个导电层间连接,其中该方法包括:形成源极‑漏极导体图案,该源极‑漏极导体图案限定源极导体阵列和漏极导体阵列,每个源极导体为晶体管阵列的相应晶体管集合提供寻址线,并且每个漏极导体与晶体管阵列的相应晶体管相关联;其中形成所述源极‑漏极导体图案包括形成第一导体子图案,并且此后形成第二导体子图案,其中所述第一导体子图案在其中要形成与源极‑漏极导体图案的导电层间连接的一个或多个互连区域中提供源极‑漏极导体图案的导电表面,并且第二导体子图案至少在源极导体和漏极导体最接近的区域中提供源极‑漏极导体图案的导电表面。
Description
晶体管阵列可以由包括导体层、半导体层和绝缘体层的各层的堆叠来限定。
堆叠的一个重要部分是限定晶体管阵列的源极和漏极导体的源极-漏极导体图案,并且本申请的发明人已经进行了以下研究:(i)改善半导体沟道与源极/漏极导体之间的电荷载流子传输,以及(ii)改善该源极-漏极导体图案与堆叠中一个或多个其它层级的导体之间的导电连接。
由此,提供了一种制造器件的方法,该器件包括限定晶体管阵列的各层的堆叠并且包含一个或多个导电层间连接,其中该方法包括:形成源极-漏极导体图案,该源极-漏极导体图案限定源极导体阵列和漏极导体阵列,每个源极导体为晶体管阵列的相应晶体管集合提供寻址线,并且每个漏极导体与晶体管阵列的相应晶体管相关联;其中形成所述源极-漏极导体图案包括形成第一导体子图案,并且此后形成第二导体子图案,其中所述第一导体子图案在其中要形成与源极-漏极导体图案的导电层间连接的一个或多个互连区域中提供源极-漏极导体图案的导电表面,并且第二导体子图案至少在源极导体和漏极导体最接近的区域中提供源极-漏极导体图案的导电表面。
根据一个实施例,该方法还包括:在基本上限于所述一个或多个互连区域的区域和所述一个或多个互连区域中的每个互连区域周围的外围区域中形成所述第一导体子图案;以及所述第二导体子图案在所述外围区域中与所述第一导体子图案重叠。
根据一个实施例,该方法还包括:在所述源极-漏极导体图案上方形成一层或多层,并且此后使用由包含氧的气体产生的等离子体在所述一个或多个互连区域中形成通孔,并在互连区域中沉积导体材料;其中第一导体子图案的材料在形成通孔的条件下比第二导体子图案的材料表现出更小的电导率降低。
根据一个实施例,第一导体图案的材料在暴露于所述等离子体时基本上不表现出电导率降低。
根据一个实施例,该方法还包括在源极-漏极导体图案上方形成半导体沟道材料层,以提供用于晶体管阵列的半导体沟道;以及使用由基本上不包括氧的气体产生的等离子体对有机半导体沟道材料层构图。
根据一个实施例,等离子体由基本上由一种或多种稀有气体构成的气体产生。
根据一个实施例,该方法还包括:在所述源极-漏极导体图案上方形成一层或多层;此后在所述一个或多个互连区域中形成通孔;在所述一层或多层上方形成上导体图案,该上导体图案通过所述一个或多个互连区域中的通孔与第一导体子图案接触;以及其中上导体图案和第一导体子图案之间的接触是不同导体材料之间的接触。
由此,还提供了一种方法,包括:使用由基本上不包括氧的气体产生的等离子体来对有机半导体沟道材料层构图,该有机半导体沟道材料层在限定晶体管阵列的各层的堆叠中提供半导体沟道。
根据一个实施例,等离子体由基本上由一种或多种稀有气体构成的气体产生。
由此,还提供了一种器件,该器件包括限定晶体管阵列的各层的堆叠并且包含一个或多个导电层间连接,其中该器件包括:源极-漏极导体图案,其限定源极导体阵列和漏极导体阵列,每个源极导体为晶体管阵列的相应晶体管集合提供寻址线,并且每个漏极导体与晶体管阵列的相应晶体管相关联;其中所述源极-漏极导体图案包括第一导体子图案和在第一导体子图案上方的第二导体子图案,其中所述第一导体子图案在其中要形成与源极-漏极导体图案的导电层间连接的一个或多个互连区域中提供源极-漏极导体图案的导电表面,并且第二导体子图案至少在源极导体和漏极导体最接近的区域中提供源极-漏极导体图案的导电表面。
根据一个实施例,所述第一导体子图案形成在基本上限于所述一个或多个互连区域的区域以及所述一个或多个互连区域中的每个互连区域周围的外围区域中,以及所述第二导体子图案在所述外围区域中与所述第一导体子图案重叠。
根据一个实施例,该器件还包括:在所述源极-漏极导体图案上方形成的一层或多层;以及在所述一个或多个互连区域中经由通孔与所述源极-漏极导体图案接触的另一个导体图案;其中第一导体子图案的材料在活性氧气氛中比第二导体子图案的材料不易氧化。
根据一个实施例,该器件还包括:在所述源极-漏极导体图案上方形成的一层或多层;以及在所述一个或多个互连区域中通过通孔与第一导体子图案接触的上导体图案;其中上导体图案和第一导体子图案之间的接触是不同导体材料之间的接触。
下面仅通过示例的方式,参考附图详细描述本发明的实施例,其中:
图1至图8图示了根据本发明的技术的示例实施例的处理流程,其中图3b和图5b分别是沿着图3a和图5a中的虚线A-A的横截面。
为了简明起见,附图集中于薄膜晶体管(TFT)/多像素阵列中的单个晶体管区域/单个像素。产品器件通常将包括大量这样的晶体管区域/像素。
下面描述的实施例是用于顶栅晶体管阵列的示例,但是该技术也适用于其它类型的晶体管阵列,诸如底栅晶体管阵列。
出于本文档的目的,术语“源极导体”是指驱动器芯片端子和半导体沟道之间电气串联的导体,术语“漏极导体”是指经由半导体沟道与驱动器芯片端子电气串联的导体。
半导体沟道材料可以包括一种或多种有机半导体材料(诸如,例如有机聚合物半导体)和/或一种或多种无机半导体材料。
下面描述的实施例使用银合金作为源极-漏极导体图案的主要部分。银合金的相对高的功函数(work-function)非常适合于发明人进行的研究工作中使用的特定半导体沟道材料,但是其它导体材料(也包括具有相对低功函数的导体材料)可能更适合于不同的半导体沟道材料。
下面描述的实施例将导电金属氧化物(铟锡氧化物(ITO))用作源极-漏极导体图案的次要部分,该导电金属氧化物对于用于对本发明人进行的研究工作中使用的特定半导体沟道材料的层构图的蚀刻剂和用于对下面讨论的银合金层构图的蚀刻剂都具有足够低的相对蚀刻速率。可以使用其它导体材料,并且其它导体材料可能更适合与其它半导体沟道材料和/或其它主要源极-漏极导体材料组合使用。
第一步涉及通过气相沉积处理用ITO涂覆基板2的工作表面。在这个示例中,基板包括有机聚合物支撑膜(自支撑塑料膜)、在产品器件中提供遮光功能的构图导体层,以及在表面处的绝缘平面化层。
通过光刻和蚀刻(例如,使用草酸或盐酸(HCl))对ITO涂层进行构图。在这个示例中,ITO的构图涉及形成包括ITO的岛4的ITO子图案,每个岛4占据整个相应的互连区域和互连区域周围的外围区域。附图示出了在将在较高层级的像素导体22与漏极导体之间建立导电层间连接的区域中和周围形成ITO的岛4的示例。
在该ITO构图之后,通过在工件上方,包括在ITO岛4上方的蒸气沉积,形成银合金层6(例如,包含0.5%铟的银合金)。在沉积银合金层6之前,可以沉积一层或多层,诸如用于改善银合金对工件的附着力的一层或多层导体层,从而形成子层的堆叠,这些子层然后被一起构图。在下文中,术语“银合金层”用于表示在上表面具有银合金的单层或两层或多层的堆叠。然后,通过光刻和蚀刻(例如,使用磷酸、乙酸和硝酸的混合物)对银合金层6进行构图。ITO子图案4在利用用于对银合金层构图的蚀刻剂的情况下表现出相对低的蚀刻速率。
所得的源极-漏极导体图案(包括银合金子图案6和ITO子图案4)至少限定(i)源极导体的阵列,每个源极导体与晶体管的相应列相关联并且延伸超出阵列的边缘以连接到驱动器芯片的相应端子(未示出),以及(ii)漏极导体阵列,每个漏极导体与相应的晶体管相关联。每个源极导体包括延伸超出阵列的边缘以连接到驱动器芯片的相应端子的寻址线8d、以及用于每个晶体管的一个或多个源导体指状物8a,该导体指状物8a从寻址线8d分支出。源极极导体指状物8a是源极导体中最靠近漏极导体的部分。漏极导体包括一个或多个漏极导体指状物8b,其平行于源极导体指状物8a延伸(例如,与源极导体指状物8a指状交叉),并且是漏极导体中最靠近源极导体的部分。每个漏极导体还包括由ITO和银合金子图案4、6限定的漏极焊盘8c。漏极焊盘8c连接到银合金子图案6内的(一个或多个)漏极导体指状物8b。
银合金子图案6在互连区域周围的外围区域中与ITO子图案4重叠,以与ITO子图案4电接触。银合金子图案6与ITO子图案4的良好对准是通过使用相同的对准标记(未示出)来实现的,该对准标记用于固定在对ITO和银合金层构图的过程中用于对光致抗蚀剂构图的掩模的位置。例如,对准标记可以由形成基板的一部分的上述遮光的导体层限定。
半导体沟道材料(或其前体)的溶液膜被沉积(例如,通过旋涂)在工件上方。在此之前,可以在银合金子图案6的表面上形成改善银合金子图案6与半导体沟道材料之间的电荷传输的一层或多层,诸如,例如合适的有机材料的自组装单层。
在干燥等之后,对所得的半导体沟道材料10的层进行构图以形成半导体沟道材料的隔离岛12阵列,每个岛12为阵列的相应晶体管提供半导体沟道。常规上使用由包含氧的气体产生的等离子体来对有机半导体沟道材料的各层进行构图,这涉及等离子体物质与半导体沟道材料的暴露(未掩蔽)区域的化学反应。本申请的发明人已经发现,由基本上由氩气构成的气体(基本上不包括氧)产生的等离子体也可以用于对有机聚合物半导体沟道材料构图,并且对于包括在半导体沟道材料下方的易于氧化的导体(例如,源极-漏极导体)的TFT阵列,使用100%氩气等离子体的构图可以在产品TFT阵列的性能方面优于使用氧等离子体进行构图。不希望受到理论的束缚,本申请的发明人将这种改进归因于利用100%的氩气等离子体的物理蚀刻机制的优势(即,涉及有机聚合物半导体沟道材料层与高能等离子体物质之间的物理(非化学)相互作用)。
工件的进一步加工继续依次形成:(例如,有机聚合物)栅极介电层(或栅极介电层的堆叠)14;构图的导体层(或导体层的堆叠)16,其至少限定栅极导体阵列,每个栅极导体与相应的晶体管行相关联,并且每个都延伸超出TFT阵列的边缘以电连接到驱动器芯片的相应端子;在构图的导体层上方的(例如,有机聚合物)绝缘体层(或绝缘体层的堆叠)18。每个晶体管都与栅极和源极导体的唯一组合相关联,从而可以独立于所有其它像素来控制每个像素。
由包含氧O2的气体(例如,O2和六氟化硫SF6的气体混合物)产生的等离子体用于在要形成导电层间连接的区域(包括向下要将导电层间连接形成到每个漏极导体的区域)中产生穿过(一个或多个)绝缘层18和(一个或多个)栅极介电层14的通孔20。如上所述,仅ITO子图案4位于要形成这种层间连接的区域中,并且通孔20使ITO子图案4的部分暴露而不暴露银合金子图案6。
然后在工件上方形成另一个导体图案,该另一个导体图案限定像素导体阵列22,每个像素导体经由相应的通孔20连接到相应的漏极导体。在一个实施例中,另一个导体图案包括ITO以提供高度透明的像素导体,例如,使用背光的透射OLCD设备。在另一个实施例中,另一个导体图案包括金属或金属合金层,诸如钼(Mo)或银合金,或金属和/或金属合金层的堆叠,诸如包括夹在两个钼(Mo)子层之间的铝(Al)子层的堆叠。由于使用ITO子图案而产生的上述改进适用于(i)情况(i)其中另一个导体图案和ITO子图案之间的接触是不同导体材料之间的接触,以及还有(ii)情况(ii)其中另一个导体图案和ITO子图案之间的接触是相同导体材料之间的接触。
不希望受到理论的束缚,ITO子图案4被认为通过在使用氧等离子体创建通孔20的过程期间更好地避免形成非导体(金属氧化物绝缘体)来改善产品器件的性能。
除了上面明确提到的任何修改之外,对于本领域技术人员显而易见的是,可以在本发明的范围内对所描述的实施例进行各种其它修改。
申请人在此单独公开了本文描述的每个单独的特征以及两个或更多个这样的特征的任意组合,其程度是使得能够根据本领域技术人员的共同一般知识基于本说明书整体来执行这些特征或组合,不论这些特征或特征组合是否解决本文公开的任何问题,并且不限制请求保护的范围。申请人指出,本发明的各方面可以包括任何这样的单独的特征或特征的组合。
Claims (13)
1.一种制造器件的方法,该器件包括限定晶体管阵列的各层的堆叠并且包含一个或多个导电层间连接,其中该方法包括:形成源极-漏极导体图案,该源极-漏极导体图案限定源极导体阵列和漏极导体阵列,每个源极导体为晶体管阵列的相应晶体管集合提供寻址线,每个漏极导体与晶体管阵列的相应晶体管相关联;其中形成所述源极-漏极导体图案包括形成第一导体子图案,并且此后形成第二导体子图案,其中所述第一导体子图案在其中要形成与源极-漏极导体图案的导电层间连接的一个或多个互连区域中提供源极-漏极导体图案的导电表面,并且第二导体子图案至少在源极导体和漏极导体最接近的区域中提供源极-漏极导体图案的导电表面。
2.根据权利要求1所述的方法,还包括:在基本上限于所述一个或多个互连区域的区域和所述一个或多个互连区域中的每个互连区域周围的外围区域中形成所述第一导体子图案;以及所述第二导体子图案在所述外围区域中与所述第一导体子图案重叠。
3.根据权利要求1或权利要求2所述的方法,其中所述方法还包括:在所述源极-漏极导体图案上方形成一层或多层,并且此后使用由包含氧的气体产生的等离子体在所述一个或多个互连区域中形成通孔,以及在互连区域中沉积导体材料;其中第一导体子图案的材料在形成通孔的条件下比第二导体子图案的材料表现出更小的电导率降低。
4.根据权利要求3所述的方法,其中第一导体图案的材料在暴露于所述等离子体时基本上不表现出电导率降低。
5.根据前述权利要求中的任一项所述的方法,包括:在源极-漏极导体图案上方形成半导体沟道材料层,以提供用于晶体管阵列的半导体沟道;以及使用由基本上不包括氧的气体产生的等离子体对有机半导体沟道材料层构图。
6.根据权利要求5所述的方法,其中等离子体由基本上由一种或多种稀有气体构成的气体产生。
7.根据前述权利要求中的任一项所述的方法,还包括:在所述源极-漏极导体图案上方形成一层或多层;此后在所述一个或多个互连区域中形成通孔;在所述一层或多层上方形成上导体图案,该上导体图案通过所述一个或多个互连区域中的通孔与第一导体子图案接触;以及其中上导体图案和第一导体子图案之间的接触是不同导体材料之间的接触。
8.一种方法,包括:使用由基本上不包括氧的气体产生的等离子体来对有机半导体沟道材料层构图,该有机半导体沟道材料层在限定晶体管阵列的各层的堆叠中提供半导体沟道。
9.根据权利要求8所述的方法,其中等离子体由基本上由一种或多种稀有气体构成的气体产生。
10.一种器件,包括限定晶体管阵列的各层的堆叠并且包含一个或多个导电层间连接,其中所述器件包括:源极-漏极导体图案,其限定源极导体阵列和漏极导体阵列,每个源极导体为晶体管阵列的相应晶体管集合提供寻址线,每个漏极导体与晶体管阵列的相应晶体管相关联;其中所述源极-漏极导体图案包括第一导体子图案和在第一导体子图案上方的第二导体子图案,其中所述第一导体子图案在其中要形成与源极-漏极导体图案的导电层间连接的一个或多个互连区域中提供源极-漏极导体图案的导电表面,并且第二导体子图案至少在源极导体和漏极导体最接近的区域中提供源极-漏极导体图案的导电表面。
11.根据权利要求10所述的器件,其中所述第一导体子图案形成在基本上限于所述一个或多个互连区域的区域和所述一个或多个互连区域中的每个互连区域周围的外围区域中;以及所述第二导体子图案在所述外围区域中与所述第一导体子图案重叠。
12.根据权利要求10或权利要求11所述的器件,还包括:在所述源极-漏极导体图案上方形成的一层或多层;以及在所述一个或多个互连区域中经由通孔与所述源极-漏极导体图案接触的另一个导体图案;其中第一导体子图案的材料在活性氧气氛中比第二导体子图案的材料更不易氧化。
13.根据权利要求10至12中的任一项所述的器件,还包括:在所述源极-漏极导体图案上方的一层或多层;以及在所述一个或多个互连区域中通过通孔与第一导体子图案接触的上导体图案;并且其中上导体图案和第一导体子图案之间的接触是不同导体材料之间的接触。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1809031.6A GB2574266A (en) | 2018-06-01 | 2018-06-01 | Transistor Arrays |
GB1809031.6 | 2018-06-01 | ||
PCT/EP2019/064220 WO2019229254A1 (en) | 2018-06-01 | 2019-05-31 | Transistor array |
Publications (1)
Publication Number | Publication Date |
---|---|
CN112368852A true CN112368852A (zh) | 2021-02-12 |
Family
ID=62872827
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201980043977.2A Pending CN112368852A (zh) | 2018-06-01 | 2019-05-31 | 晶体管阵列 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20210217978A1 (zh) |
CN (1) | CN112368852A (zh) |
DE (1) | DE112019002792T5 (zh) |
GB (1) | GB2574266A (zh) |
WO (1) | WO2019229254A1 (zh) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11352515A (ja) * | 1998-06-09 | 1999-12-24 | Mitsubishi Electric Corp | 液晶表示装置およびその製造方法 |
CN101006588B (zh) * | 2004-08-31 | 2010-07-28 | 株式会社半导体能源研究所 | 半导体装置的生产方法 |
JP2010157493A (ja) * | 2008-12-02 | 2010-07-15 | Sony Corp | 表示装置およびその製造方法 |
US9224869B2 (en) * | 2012-09-12 | 2015-12-29 | Sharp Kabushiki Kaisha | Semiconductor device and method for manufacturing same |
-
2018
- 2018-06-01 GB GB1809031.6A patent/GB2574266A/en not_active Withdrawn
-
2019
- 2019-05-31 WO PCT/EP2019/064220 patent/WO2019229254A1/en active Application Filing
- 2019-05-31 CN CN201980043977.2A patent/CN112368852A/zh active Pending
- 2019-05-31 US US15/734,119 patent/US20210217978A1/en not_active Abandoned
- 2019-05-31 DE DE112019002792.1T patent/DE112019002792T5/de not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
GB2574266A (en) | 2019-12-04 |
US20210217978A1 (en) | 2021-07-15 |
GB2574266A8 (en) | 2019-12-18 |
DE112019002792T5 (de) | 2021-02-25 |
GB201809031D0 (en) | 2018-07-18 |
WO2019229254A1 (en) | 2019-12-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI396885B (zh) | 線路結構,製造線路之方法,薄膜電晶體基板,以及製造薄膜電晶體基板之方法 | |
TWI311815B (en) | Thin film transistor array panel and manufacturing method thereof | |
JP5253674B2 (ja) | 半導体装置およびその製造方法 | |
US7435629B2 (en) | Thin film transistor array panel and a manufacturing method thereof | |
TWI532186B (zh) | 薄膜電晶體及其形成方法 | |
US20150214249A1 (en) | Array Substrate, Display Device and Manufacturing Method | |
US20130234124A1 (en) | Thin-film transistor substrate, method of manufacturing the same, and display device including the same | |
CN103456793A (zh) | 薄膜晶体管、薄膜晶体管阵列面板及其制造方法 | |
KR102080484B1 (ko) | 액정표시장치용 어레이기판 및 그의 제조방법 | |
WO2016115824A1 (zh) | 薄膜晶体管、阵列基板及其制作方法 | |
US20060160282A1 (en) | Thin film transistor array panel and manufacturing method thereof | |
US9911854B2 (en) | Source/drain conductors for transistor devices | |
WO2016123979A1 (zh) | 薄膜晶体管及其制备方法、阵列基板和显示装置 | |
CN109148535B (zh) | 阵列基板及其制造方法、显示面板 | |
US20230335624A1 (en) | Display substrate and manufacturing method thereof, display device | |
WO2017088272A1 (zh) | 像素结构、阵列基板、液晶显示面板及像素结构制造方法 | |
US20150069401A1 (en) | Thin film transistor substrate and method of manufacturing the thin film transistor substrate | |
CN112368852A (zh) | 晶体管阵列 | |
CN112335048A (zh) | 晶体管阵列 | |
US8647980B2 (en) | Method of forming wiring and method of manufacturing semiconductor substrates | |
US20210183907A1 (en) | Semiconductor devices | |
KR20070095549A (ko) | 박막 트랜지스터 어레이 기판의 제조 방법 | |
KR100986907B1 (ko) | 액정 디스플레이 패널 제조방법 및 그에 의해 제조된 액정 디스플레이 패널 | |
KR100878264B1 (ko) | 액정 표시 장치용 박막 트랜지스터 기판의 제조 방법 | |
KR20040024993A (ko) | 박막 트랜지스터 기판 및 그의 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20230525 Address after: Britain Camb Applicant after: Fleck Innabur Technology Co.,Ltd. Address before: Britain Camb Applicant before: PLASTIC LOGIC LTD. |
|
TA01 | Transfer of patent application right |