CN112368822B - 利用选择性双层电介质再生的全自对准过孔 - Google Patents
利用选择性双层电介质再生的全自对准过孔 Download PDFInfo
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- CN112368822B CN112368822B CN201980042746.XA CN201980042746A CN112368822B CN 112368822 B CN112368822 B CN 112368822B CN 201980042746 A CN201980042746 A CN 201980042746A CN 112368822 B CN112368822 B CN 112368822B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201862690838P | 2018-06-27 | 2018-06-27 | |
| US62/690,838 | 2018-06-27 | ||
| PCT/US2019/039260 WO2020006087A1 (en) | 2018-06-27 | 2019-06-26 | Fully self-aligned via with selective bilayer dielectric regrowth |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112368822A CN112368822A (zh) | 2021-02-12 |
| CN112368822B true CN112368822B (zh) | 2023-09-22 |
Family
ID=68987240
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201980042746.XA Active CN112368822B (zh) | 2018-06-27 | 2019-06-26 | 利用选择性双层电介质再生的全自对准过孔 |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US11031287B2 (enExample) |
| JP (1) | JP7339481B2 (enExample) |
| KR (1) | KR102726634B1 (enExample) |
| CN (1) | CN112368822B (enExample) |
| TW (1) | TWI816819B (enExample) |
| WO (1) | WO2020006087A1 (enExample) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112074940A (zh) * | 2018-03-20 | 2020-12-11 | 东京毅力科创株式会社 | 结合有集成半导体加工模块的自感知校正异构平台及其使用方法 |
| US11121025B2 (en) * | 2018-09-27 | 2021-09-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Layer for side wall passivation |
| US11515203B2 (en) * | 2020-02-05 | 2022-11-29 | Tokyo Electron Limited | Selective deposition of conductive cap for fully-aligned-via (FAV) |
| US11508572B2 (en) | 2020-04-01 | 2022-11-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US20220238323A1 (en) * | 2021-01-28 | 2022-07-28 | Tokyo Electron Limited | Method for selective deposition of dielectric on dielectric |
| US11929314B2 (en) * | 2021-03-12 | 2024-03-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures including a fin structure and a metal cap |
| US20230352343A1 (en) * | 2022-04-27 | 2023-11-02 | Tokyo Electron Limited | Top-down self-alignment of vias in a semiconductor device for sub-22nm pitch metals |
| US12308310B2 (en) | 2022-05-05 | 2025-05-20 | Nanya Technology Corporation | Method for forming semiconductor interconnection structure against stress migration |
| TWI833263B (zh) * | 2022-05-25 | 2024-02-21 | 南亞科技股份有限公司 | 具有插塞結構的半導體元件 |
| US12283518B2 (en) | 2022-05-25 | 2025-04-22 | Nanya Technology Corporation | Method for fabricating semiconductor device with contact structure |
| US12417982B2 (en) | 2022-05-25 | 2025-09-16 | Nanya Technology Corporation | Semiconductor device with contact structure |
| US20250054809A1 (en) * | 2023-08-07 | 2025-02-13 | Tokyo Electron Limited | Fully self-aligned via with graphene cap |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI220774B (en) * | 2003-11-03 | 2004-09-01 | Univ Nat Sun Yat Sen | Method for patterning low dielectric constant film and method for manufacturing dual damascene structure |
| KR20050073890A (ko) * | 2004-01-12 | 2005-07-18 | 삼성전자주식회사 | 반도체 장치의 배선 구조체 및 그 형성 방법 |
| CN102468267A (zh) * | 2010-10-28 | 2012-05-23 | 旺宏电子股份有限公司 | 半导体结构及其制造方法 |
| CN106571305A (zh) * | 2015-08-28 | 2017-04-19 | 英飞凌科技德累斯顿有限公司 | 具有通过夹层延伸的接触结构的半导体器件及其制造方法 |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6287961B1 (en) * | 1999-01-04 | 2001-09-11 | Taiwan Semiconductor Manufacturing Company | Dual damascene patterned conductor layer formation method without etch stop layer |
| JP4910231B2 (ja) * | 2000-10-25 | 2012-04-04 | ソニー株式会社 | 半導体装置の製造方法 |
| US20030148618A1 (en) | 2002-02-07 | 2003-08-07 | Applied Materials, Inc. | Selective metal passivated copper interconnect with zero etch stops |
| US20050082089A1 (en) * | 2003-10-18 | 2005-04-21 | Stephan Grunow | Stacked interconnect structure between copper lines of a semiconductor circuit |
| US7259463B2 (en) * | 2004-12-03 | 2007-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Damascene interconnect structure with cap layer |
| US20070228571A1 (en) * | 2006-04-04 | 2007-10-04 | Chen-Hua Yu | Interconnect structure having a silicide/germanide cap layer |
| KR100790452B1 (ko) * | 2006-12-28 | 2008-01-03 | 주식회사 하이닉스반도체 | 다마신 공정을 이용한 반도체 소자의 다층 금속배선형성방법 |
| US7776743B2 (en) * | 2008-07-30 | 2010-08-17 | Tel Epion Inc. | Method of forming semiconductor devices containing metal cap layers |
| KR100953736B1 (ko) * | 2009-07-27 | 2010-04-19 | 주식회사 아토 | 증착 장치 및 반도체 소자의 제조 방법 |
| JP5665557B2 (ja) * | 2011-01-14 | 2015-02-04 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
| US9269612B2 (en) * | 2011-11-22 | 2016-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms of forming damascene interconnect structures |
| US8803321B2 (en) * | 2012-06-07 | 2014-08-12 | International Business Machines Corporation | Dual damascene dual alignment interconnect scheme |
| US8652962B2 (en) * | 2012-06-19 | 2014-02-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Etch damage and ESL free dual damascene metal interconnect |
| US9583429B2 (en) * | 2013-11-14 | 2017-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and method of forming same |
| US9659857B2 (en) * | 2013-12-13 | 2017-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and method making the same |
| US9553017B2 (en) * | 2015-01-23 | 2017-01-24 | GlobalFoundries, Inc. | Methods for fabricating integrated circuits including back-end-of-the-line interconnect structures |
| US9659864B2 (en) | 2015-10-20 | 2017-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for forming self-aligned via with selectively deposited etching stop layer |
| KR102616823B1 (ko) * | 2015-12-16 | 2023-12-22 | 삼성전자주식회사 | 반도체 장치 |
| US9530691B1 (en) * | 2016-02-19 | 2016-12-27 | Globalfoundries Inc. | Methods, apparatus and system for forming a dielectric field for dual orientation self aligned vias |
| US10068764B2 (en) * | 2016-09-13 | 2018-09-04 | Tokyo Electron Limited | Selective metal oxide deposition using a self-assembled monolayer surface pretreatment |
| KR102449200B1 (ko) * | 2017-07-04 | 2022-09-30 | 삼성디스플레이 주식회사 | 클럭 배선을 포함하는 표시 장치 |
| CN112074940A (zh) * | 2018-03-20 | 2020-12-11 | 东京毅力科创株式会社 | 结合有集成半导体加工模块的自感知校正异构平台及其使用方法 |
-
2019
- 2019-06-26 WO PCT/US2019/039260 patent/WO2020006087A1/en not_active Ceased
- 2019-06-26 JP JP2020571839A patent/JP7339481B2/ja active Active
- 2019-06-26 CN CN201980042746.XA patent/CN112368822B/zh active Active
- 2019-06-26 US US16/453,473 patent/US11031287B2/en active Active
- 2019-06-26 KR KR1020207036487A patent/KR102726634B1/ko active Active
- 2019-06-27 TW TW108122579A patent/TWI816819B/zh active
-
2021
- 2021-04-06 US US17/223,831 patent/US11705369B2/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI220774B (en) * | 2003-11-03 | 2004-09-01 | Univ Nat Sun Yat Sen | Method for patterning low dielectric constant film and method for manufacturing dual damascene structure |
| KR20050073890A (ko) * | 2004-01-12 | 2005-07-18 | 삼성전자주식회사 | 반도체 장치의 배선 구조체 및 그 형성 방법 |
| CN102468267A (zh) * | 2010-10-28 | 2012-05-23 | 旺宏电子股份有限公司 | 半导体结构及其制造方法 |
| CN106571305A (zh) * | 2015-08-28 | 2017-04-19 | 英飞凌科技德累斯顿有限公司 | 具有通过夹层延伸的接触结构的半导体器件及其制造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI816819B (zh) | 2023-10-01 |
| JP7339481B2 (ja) | 2023-09-06 |
| TW202006886A (zh) | 2020-02-01 |
| CN112368822A (zh) | 2021-02-12 |
| KR20210014127A (ko) | 2021-02-08 |
| KR102726634B1 (ko) | 2024-11-05 |
| US20200006140A1 (en) | 2020-01-02 |
| US11705369B2 (en) | 2023-07-18 |
| WO2020006087A1 (en) | 2020-01-02 |
| US11031287B2 (en) | 2021-06-08 |
| US20210249305A1 (en) | 2021-08-12 |
| JP2021530101A (ja) | 2021-11-04 |
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