CN112331556A - 非晶硅薄膜成膜方法 - Google Patents

非晶硅薄膜成膜方法 Download PDF

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CN112331556A
CN112331556A CN202011202115.0A CN202011202115A CN112331556A CN 112331556 A CN112331556 A CN 112331556A CN 202011202115 A CN202011202115 A CN 202011202115A CN 112331556 A CN112331556 A CN 112331556A
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amorphous silicon
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王剑敏
葛哲玮
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Abstract

本发明公开了一种非晶硅薄膜成膜方法，在非晶硅薄膜成膜之前，先淀积一层采用低淀积速率形成的一层等离子增强氧化膜层，然后再淀积非晶硅薄膜层，此方法形成的非晶硅薄膜表面粗糙度低，平整度好，大幅改善非晶硅成膜质量。

Description

非晶硅薄膜成膜方法
技术领域
本发明涉及半导体集成电路制造领域，特别是指一种非晶硅薄膜成膜方法。
背景技术
在MEMS工艺过程中，非晶硅是一种常用材料。非晶硅是硅的同素异形体形式，能够以薄膜形式沉积在各种基板上，为各种电子应用提供某些独特的功能。非晶硅被用在大规模生产的微机电系统(MEMS)和纳米机电系统(NEMS)、太阳能电池、微晶硅和微非晶硅、甚至对于各种基板上的滚压工艺技术都有应用。非晶体硅材料被广泛运用在半导体的各个领域，当非晶硅被使用在金属后的工艺中时，需要使用温度较低的工艺以避免金属线的熔化，等离子体增强化学气相淀积(PECVD)制备方法几乎是首选的方案。
目前在后道淀积非晶硅薄膜前会使用基于硅烷SiH4的生长一层普通PE-SiO2层，然后再淀积一层非晶硅薄膜。淀积非晶硅薄膜后会发现表面粗糙度较差，图1是对生长的非晶硅薄膜进行表面缺陷测试的结果，测试结果已超测试仪器的测量范围上限(＞10000个)，显示满片异常。图2是SEM结果显示表面较粗糙布满小鼓包，图3是SEM断面显示非晶硅薄膜在部分区域异常生长过快，形成鼓包。
发明内容
本发明所要解决的技术问题在于提供一种非晶硅薄膜成膜方法，形成高平坦度的无鼓包的非晶硅薄膜。
为解决上述问题，本发明所述的非晶硅薄膜成膜方法，是在非晶硅薄膜成膜之前，先淀积一层采用低淀积速率形成的氧化硅膜，然后再淀积形成非晶硅薄膜。
进一步的改进是，所述氧化硅膜层采用基于硅烷材料形成氧化硅的工艺。
进一步的改进是，所述采用低淀积速率形成的氧化硅膜，其淀积速率为
Figure BDA0002755640100000011
Figure BDA0002755640100000012
进一步的改进是，所述低淀积速率形成的氧化硅膜,在工艺腔内，其淀积温度为350～450℃，淀积压力为2～4Torr，高频功率为100～500W，硅烷流量为10～150sccm，N2O的流量为3000～5000sccm。
本发明所述的非晶硅薄膜成膜方法，通过在非晶硅薄膜淀积之前先形成一层等离子增强氧化膜层，且该等离子增强氧化膜层采用低速率淀积方法淀积形成，然后再淀积非晶硅薄膜层，此方法形成的非晶硅薄膜表面粗糙度低，平整度好，大幅改善非晶硅成膜质量。
附图说明
图1是现有工艺形成非晶硅薄膜，对其表面进行缺陷检测的测试结果。
图2是对现有工艺形成的非晶硅薄膜的表面显微图。
图3是对现有工艺形成的非晶硅薄膜的断面显微图。
图4是采用本发明工艺形成的非晶硅薄膜的表面缺陷检测测试结果。
图5是采用本发明方法淀积的同批次多片晶圆进行检测的示意图。
图6是采用本发明工艺淀积的非晶硅薄膜的表面显微图。
图7是采用本发明工艺淀积的非晶硅薄膜的断面显微图。
图8是本发明方法示意图。
具体实施方式
本发明所述的非晶硅薄膜成膜方法，通过将非晶硅衬底普通氧化硅改为低淀积速率的氧化硅，可以改善非晶硅成长表面的粗糙度。具体是在非晶硅薄膜成膜之前，先淀积一层采用低淀积速率形成的氧化硅膜，然后再淀积形成非晶硅薄膜。
首先采用硅烷SiH4作为淀积氧化硅的原材料，在工艺腔内，采用等离子增强淀积工艺，淀积温度为350～450℃，淀积压力为2～4Torr，高频功率为100～500W，硅烷流量为10～150sccm，N2O的流量为3000～5000sccm。
利用上述参数在工艺腔内先淀积氧化硅层，淀积速率控制在
Figure BDA0002755640100000021
传统工艺一般为
Figure BDA0002755640100000023
本发明实施例采用
Figure BDA0002755640100000022
的工艺速率，形成氧化膜后，再在上述氧化膜上淀积形成非晶硅薄膜层。
需要注意的是，本发明所涉及的是后道(金属后)非晶硅淀积工艺，为避免对已形成的金属的影响，所述的非晶硅薄膜为低温非晶硅薄膜，其淀积温度为350～450℃，与前道的高温的非晶硅工艺不同，因此，其前面所述的低速率淀积的衬底上的氧化硅层必须为低温工艺的氧化硅层，淀积温度为350～450℃。
通过上述工艺形成的非晶硅薄膜层能大幅改善非晶硅薄膜的表面形貌，使其粗糙度、平坦度都有较大的提升。
借助缺陷测量仪器对于＞0.2um的缺陷进行测量，如图4所示，非晶硅薄膜表面的缺陷由＞10000个可下降到的＜30个(29个，图中每一个黑点表示一个缺陷)。图5的同批次多片晶圆重复测试结果也显示改善明显且较稳定，缺陷每片均＜30个(最高数据27个)。
如图6及图7所示，是本发明工艺淀积的非晶硅薄膜的表面显微图及断面显微图，将图6与图2进行对比，本发明工艺形成的非晶硅薄膜的表面粗糙度明显降低，颗粒感有明显改善，而将图7与图3进行对比，局部鼓包也基本消失。
本发明通过大幅降低成膜反应气体中SiH4的流量，同时微调相关的压力HF、N2O，维持良好的面内均匀性,降低氧化硅淀积速率，改善了非晶硅薄膜的表面粗糙度。
以上仅为本发明的优选实施例，并不用于限定本发明。对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (6)

1.一种非晶硅薄膜成膜方法，其特征在于：在非晶硅薄膜成膜之前，先淀积一层采用低淀积速率形成的氧化硅膜，然后再淀积形成非晶硅薄膜。
2.如权利要求1所述的非晶硅薄膜成膜方法，其特征在于：所述氧化硅膜层采用基于硅烷材料形成氧化硅的工艺。
3.如权利要求1所述的非晶硅薄膜成膜方法，其特征在于：所述低淀积速率形成的氧化硅膜,在工艺腔内，其淀积温度为350～450℃，淀积压力为2～4Torr，高频功率为100～500W，硅烷流量为10～150sccm，N2O的流量为3000～5000sccm。
4.如权利要求3所述的非晶硅薄膜成膜方法，其特征在于：所述采用低淀积速率形成的氧化硅膜，其淀积速率为
Figure FDA0002755640090000011
5.如权利要求2所述的非晶硅薄膜成膜方法，其特征在于：所述的氧化膜采用等离子增强淀积工艺淀积而成。
6.如权利要求1所述的非晶硅薄膜成膜方法，其特征在于：所述的非晶硅薄膜为低温非晶硅薄膜，其淀积温度为350～450℃。
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CN113506721A (zh) * 2021-06-25 2021-10-15 上海华虹宏力半导体制造有限公司 非晶硅薄膜形成方法
CN113921379A (zh) * 2021-09-29 2022-01-11 上海华虹宏力半导体制造有限公司 谐振器腔体薄膜的形成方法

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US5242855A (en) * 1991-09-30 1993-09-07 Nec Corporation Method of fabricating a polycrystalline silicon film having a reduced resistivity
JPH06318701A (ja) * 1993-03-12 1994-11-15 Semiconductor Energy Lab Co Ltd 半導体回路およびその作製方法
US6391784B1 (en) * 1999-07-21 2002-05-21 Advanced Micro Devices, Inc. Spacer-assisted ultranarrow shallow trench isolation formation
US20040058080A1 (en) * 2001-12-06 2004-03-25 Masahiro Kawasaki Method for creating silicon dioxide film
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* Cited by examiner, † Cited by third party
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CN113506721A (zh) * 2021-06-25 2021-10-15 上海华虹宏力半导体制造有限公司 非晶硅薄膜形成方法
CN113921379A (zh) * 2021-09-29 2022-01-11 上海华虹宏力半导体制造有限公司 谐振器腔体薄膜的形成方法

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