CN112289816B - 芯片 - Google Patents
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- 239000010409 thin film Substances 0.000 claims abstract description 90
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000004642 Polyimide Substances 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000005336 cracking Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q23/00—Antennas with active circuits or circuit elements integrated within them or attached to them
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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Abstract
本发明提供了一种芯片。芯片包括可挠基板、薄膜晶体管、重布线层、第一电力轨线层及第二电力轨线层。薄膜晶体管设置于可挠基板上。重布线层设置于薄膜晶体管上方。第一电力轨线层设置于重布线层上方,第一电力轨线层用以提供第一电压至薄膜晶体管。第二电力轨线层设置于第一电力轨线层上方,第二电力轨线层用以提供第二电压至薄膜晶体管,其中第二电力轨线层以网格形状设置。
Description
技术领域
本发明涉及一种芯片,且特别涉及一种具有可挠基板的芯片。
背景技术
现有技术中,应用于可挠基板的芯片为了避免芯片在重复挠曲的过程中产生崩裂,芯片中无法设置多层的金属走线结构。在此情况下,较少层的金属走线导致芯片中的晶体管密度下降,以及芯片的制造成本上升。
发明内容
本发明提供一种芯片,应用于可挠基板。芯片中可设置多层金属走线结构,且同时避免因为多层金属走线结构所产生的崩裂风险。
本发明的一种芯片包括可挠基板、薄膜晶体管、重布线层、第一电力轨线层及第二电力轨线层。薄膜晶体管设置于可挠基板上。重布线层设置于薄膜晶体管上方。第一电力轨线层设置于重布线层上方,第一电力轨线层用以提供第一电压至薄膜晶体管。第二电力轨线层设置于第一电力轨线层上方,第二电力轨线层用以提供第二电压至薄膜晶体管,其中第二电力轨线层以网格形状设置。
基于上述,芯片中通过网格形状设置多层金属走线结构,使芯片可有效降低崩裂风险,因此进一步提升芯片中的晶体管密度,并降低芯片的制造成本。
附图说明
图1A为本发明实施例一芯片的剖面示意图。
图1B为本发明另一实施例一芯片的剖面示意图。
图2A~2D为本发明实施例的电力轨线层由垂直方向上向下看的俯视示意图。
图3A~3D为本发明实施例电力轨线层的设置示意图。
图4A为本发明一实施例电力轨线层的设置示意图。
图4B为本发明一实施例电力轨线层的设置示意图。
图4C为本发明一实施例电力轨线层的设置示意图。
附图标记说明:
1a、1b:芯片
10:可挠基板
11、11a、11b:薄膜晶体管
12:重布线层
12v、13v、14v、15v:通孔
13、13i~13k、13’、14、14a~14k:电力轨线层
15:天线
具体实施方式
图1A为本发明实施例一芯片1a的剖面示意图。芯片1a包含有可挠基板10、薄膜晶体管(Thin Film Transistor,TFT)11、重布线层12及电力轨线层13、14。图1A中所示出的芯片1a中,薄膜晶体管11的数量及配置关系可依据不同的设计需求调整,本发明不以此限。薄膜晶体管11设置于可挠基板10上。重布线层12设置于薄膜晶体管11上。电力轨线层13设置于重布线层12上。电力轨线层14设置于电力轨线层13上。整体而言,通过将电力轨线层13、14设置于重布线层12上,芯片1a可有效的提高芯片1a中的晶体管密度,且降低芯片1a所需求的面积,故芯片1a可有效降低制造成本。
详细而言,可挠基板10具有可弯折的特性,可挠基板10可由例如为聚酰亚胺(Polyimide,PI)的材料所制成。可挠基板10的可弯曲率半径小于一预设曲率半径。在一实施例中,可挠基板10的可弯曲率半径可小于25毫米(millimeter,mm)。由于在芯片1a中,可挠基板10的成本占了芯片1a的大部分制造成本,因此降低芯片1a中可挠基板10的面积,即可有效改善芯片1a的制造成本。
薄膜晶体管11设置于可挠基板上。薄膜晶体管11可用来实现芯片1a中的运算或其他操作功能。重布线层12设置于薄膜晶体管11的上方,重布线层12与薄膜晶体管11之间可设置有通孔12v,通孔12v可为导电结构,因此,通孔12v可提供重布线层12电性连接至薄膜晶体管11。重布线层12经图案化配置以设置有走线结构,故依据重布线层12及通孔12v所提供的连接关系,薄膜晶体管11可被用来进行预先程序化的运算操作。在一实施例中,重布线层12可由金、银、铜、镍、氧化铟锡(Indium Tin Oxide,ITO)或其他适合的材料及其组合所制成。
电力轨线层13设置于重布线层12上方。电力轨线层13可连接至芯片1a的外接垫片或电源电路以取得第一电压(例如为接地电压)。电力轨线层13与薄膜晶体管11之间可设置有通孔13v,通孔13v可为导电结构,因此,通孔13v可提供电力轨线层13至薄膜晶体管11的电性连接。电力轨线层13上经图案化配置以设置有走线结构,因此,通过电力轨线层13及通孔13v,薄膜晶体管11可接收操作所需的第一电压(例如为接地电压)。在一实施例中,电力轨线层13可由金、银、铜、镍、氧化铟锡或其他适合的材料及其组合所制成。
电力轨线层14设置于电力轨线层13上方。电力轨线层14可连接至芯片1a的外接垫片或电源电路以取得第二电压(例如为操作电压)。电力轨线层14与薄膜晶体管11之间可设置有通孔14v,通孔14v可为导电结构,因此,通孔14v可提供电力轨线层14至薄膜晶体管11的电性连接。电力轨线层14上经图案化配置具有图案化的走线结构,因此,通过电力轨线层14及通孔14v,薄膜晶体管11可接收操作所需的第二电压(例如为操作电压)。在一实施例中,电力轨线层14可由金、银、铜、镍、氧化铟锡或其他适合的材料及其组合所制成。
进一步,由于芯片1a具有柔性且具有多层结构,为了改善芯片1a的柔性,芯片1a中的电力轨线层14是通过网格形状而设置。如此一来,芯片1a在工艺的均匀度以及表面平整度上,都会具有更好的一致性。换言之,网格形状的电力轨线层14可提供芯片1a更佳的挠曲性,避免芯片1a中产生崩裂(Crack)。
虽然在图1A中示出的剖面示意图中,通孔12v、13v、14v为互相重叠,但本领域具通常知识者可知,通孔12v、13v、14v在芯片1a的垂直方向由上向下观察时可为互相分离的结构。因此,重布线层12、电力轨线层13、14可通过通孔12v、13v、14v所具有的互相独立的路径,进而电性连接至薄膜晶体管11。
因此,通过在重布线层11上额外设置电力轨线层13、14,通过将电力轨线层13、14以垂直分层的结构设置,可有效避免将电力轨线设置在重布线层12中,所导致的重布线层12面积过大的问题。也就是说,芯片1a通过额外设置电力轨线层13、14可有效降低芯片1a中的薄膜晶体管11中的间隔距离,增加芯片1a中薄膜晶体管11的密度,同时降低芯片1a所需的可挠基板11面积。故芯片1a的制造成本可有效地被降低。
图1B为本发明另一实施例一芯片1b的剖面示意图。图1B所示出的芯片1b相似于图1A所示出的芯片1a,故相同元件沿用相同符号标示,且相同元件的叙述请参考上方的相关段落,于此不再赘述。芯片1b与芯片1a的差别在于,芯片1b在电力轨线层14上方还设置有天线15。
详细而言,在某些实施例中,芯片1b必须设置天线结构来满足特定系统需求。在本实施例中,天线15设置于电力轨线层14的上方。天线15与薄膜晶体管11之间可设置有通孔15v,通孔15v可为导电结构,因此,通孔15v可提供天线15至薄膜晶体管11的电性连接。天线15上经图案化配置具有图案化的天线结构,因此,天线15上的天线结构可用来提供薄膜晶体管11进行接收及发送信号。在一实施例中,天线15可由金、银、铜、镍、氧化铟锡或其他适合的材料及其组合所制成。
进一步,天线15可用于提供芯片1b进行无线信号的接收或发送,故天线15上所收发的信号频率相较于大部分薄膜晶体管11所操作的信号为高频。而在芯片1b中,由于设置有重布线层12、电力轨线层13、14,天线15与薄膜晶体管11之间的距离可以被有效地拉大,在一实施例中,天线15至薄膜晶体管11的距离大于13微米(micrometer,um),故可有效降低天线15的高频信号对薄膜晶体管11操作信号的干扰。另一方面,由于电力轨线层13、14上分别被提供了直流的第一电压(例如为接地电压)及第二电压(例如为操作电压),电力轨线层13、14可提供天线15与薄膜晶体管11之间良好的信号屏蔽,故芯片1b可有效抵抗天线15耦合至薄膜晶体管11的高频噪声。
简言之,芯片1b中通过薄膜晶体管11、重布线层12、电力轨线层13、14及天线15的结构设置,可有效改善芯片1b的信号完整性(Signal Integrity)。故芯片1b除了可有效地降低制造成本之外,还可显着地改善信号完整性。
图2A~2D为本发明多个实施例的电力轨线层14a~14d由垂直方向上向下看的俯视示意图。详细而言,电力轨线层14a~14d可应用于图1A、1B所示出的芯片1a、1b。电力轨线层14a~14d可具有较大的面积。且因应不同芯片的设计需求,电力轨线层14a~14d可具有不同的网格形状。
如图2A所示,电力轨线层14a的网格形状具有矩形的外轮廓,而外轮廓内则是铺设有直行交错的电力轨线,并于内侧形成多个矩形状的网格孔洞,形成网格形状的电力轨线14a。
如图2B所示,电力轨线层14b可在矩形轮廓的电力轨线中以第一间隔设置平行于第一方向(例如为横向方向)的多条电力轨线,且在矩形轮廓的电力轨线中的第二方向(例如为直向方向)可设置有一个或多个的矩形电力轨线,贯穿出整体的矩形轮廓,进而形成网格形状的电力轨线14b。
如图2C所示,电力轨线层14c可具有多个矩形的电力轨线,而矩形轮廓的电力轨线彼此互相交错设置,形成网格形状的电力轨线14c。
如图2D所示,电力轨线层14d可在第一方向(例如为横向方向)以第一间隔规律地设置多条具有较大宽度的电力轨线,且在第二方向上(例如为直向方向)以第二间隔规律地设置具有较小宽度的矩形电力轨线,进而形成网格形状的电力轨线14d。
因此,在芯片1a/1b中通过网格形状来设置电力轨线层14a~14d,可改善芯片1a/1b的工艺均匀度以及表面平整度,使芯片1a/1b具有较佳的可挠曲性。另一方面,通过网格形状设置的电力轨线层14a~14d,电力轨线的设置密度且电力轨线的电容性可被加大,进而有效地降低芯片1a/1b中第二电压(例如为操作电压)的扰动,改善芯片1a/1b的信号品质。简言之,通过电力轨线层14a~14d上以网格形状设置电力轨线,可在增加电力轨线层14a~14d的铺设密度且改善芯片1a/1b的信号品质的情况下,提供芯片1a/1b适应于不同设计需求,增加芯片1a/1b的设计弹性。
图3A为本发明实施例一电力轨线层14e的设置示意图。图3A中省略了芯片1a/1b中的部分构件,以方便理解电力轨线层14e的设置。在此实施例中,薄膜晶体管11可形成电路区域B1~B4。在电路区域B1上方的电力轨线层14e可为封闭平面。另外,在电路区域B2上方的电力轨线层14e可具有开口,以暴露电路区域B2。在电路区域B3、B4上方的电力轨线层14e可具有网格形状,以部分遮盖电路区域B3、B4。也就是说,由电力轨线层14e的垂直上方向下观察时,电路区域B1可完全被电力轨线层14e所覆盖,电路区域B2可被显露,电路区域B3、B4则可部分地被电力轨线层14e所遮盖。因此,因应于不同的设计考量,例如说电路区域B1的结构需要被遮盖以较佳地保护电路结构的实施方式,或者电路区域B2的结构需要较低的噪声干扰,不欲被电力轨线层14e遮盖。在上述情况下,电力轨线层14e可弹性地依据电力区域B1~B4的不同需求来进行多样化地设置。
图3B、3C为本发明实施例电力轨线层14f、14g的设置示意图。图3B、3C中省略了芯片1a/1b中的部分构件,以方便理解电力轨线层14f、14g的设置。在图3B、3C中,薄膜晶体管11可被分为薄膜晶体管11a及薄膜晶体管11b,且薄膜晶体管11a及薄膜晶体管11b分别具有不同的第一导电型态及第二导电型态。举例而言,薄膜晶体管11a可为N型薄膜晶体管,且具有低电压导通的导电型态。薄膜晶体管11b可为P型薄膜晶体管,且具有高电压导通的导电型态。因此,薄膜晶体管11a、11b的导电型态互补。薄膜晶体管11a、11b的导电型态为不同。图3B中所示出的电力轨线层14f的结构相似于图2B所示出的电力轨线层14b。图3C中所示出的电力轨线层14g的结构相似于图2C所示出的电力轨线层14c。在此实施例中,电力轨线层14f、14g可部分遮盖于薄膜晶体管11a、11b上。更精确而言,电力轨线层14f、14g可遮盖于薄膜晶体管11a、11b的漏极(Drain)区及源极(Source)区上方,并暴露薄膜晶体管11a、11b的栅极(Gate)区。如此一来,电力轨线层14f、14g在保护电路结构的同时,亦可避免薄膜晶体管11a、11b的栅极分别与电力轨线层14f、14g之间产生过大的寄生电容,进而影响薄膜晶体管11a、11b的信号品质。
图3D为本发明实施例一电力轨线层14h的设置示意图。图3D中所示出的电力轨线层14h的结构相似于图2D所示出的电力轨线层14d。在此实施例中,电力轨线层14h可完全遮盖薄膜晶体管11a、11b上,因此电力轨线层14h对于芯片1a/1b中的电路结构可达到更佳的保护效果。
虽然图2A~2D及3A~3D仅针对电力轨线层14a~14h进行说明,但本发明不限于此。也就是说,芯片1a/1b中的电力轨线层13亦可以网格形状而设置,进而实现与电力轨线层14a~14h相似的技术效果。
图4A为本发明一实施例电力轨线层13i、14i的设置示意图。电力轨线层13i可用来传递第一电压(例如为接地电压)至芯片1a/1b,电力轨线层14i可用来传递第二电压(例如为操作电压)至芯片1a/1b。在图4A所示出的实施例中,电力轨线层13i、14i由垂直上方向下观察时,电力轨线层13i、14i可为互相交错设置。电力轨线层13i覆盖于具有第一导电型态的薄膜晶体管11a(未示出于图4A中)上方,电力轨线层13i可通过通孔13v将第一电压传递至具有第一导电型态的薄膜晶体管11a。电力轨线层14i覆盖于具有第二导电型态的薄膜晶体管11b(未示出于图4A中)上方,电力轨线层14i可通过通孔14v将第二电压传递至具有第二导电型态的薄膜晶体管11b。
图4B为本发明一实施例电力轨线层13j、14j的设置示意图。在图4B所示出的实施例中,电力轨线层13j覆盖于具有第一导电型态的薄膜晶体管11a上方,电力轨线层13j可通过通孔13v将第一电压传递至具有第一导电型态的薄膜晶体管11a(未示出于图4B中)。电力轨线层14j覆盖于所有的薄膜晶体管11a、11b(未示出于图4B中)上方,电力轨线层14j可通过通孔14j将第二电压传递至具有第二导电型态的薄膜晶体管11b。
图4C为本发明一实施例电力轨线层13k、14k的设置示意图。图4C所示出的电力轨线层13k、14k分别相似于图4B所示出的电力轨线层13j、14j,只是在图4C中,电力轨线层14k在通过通孔14v将第二电压传递至薄膜晶体管11b的路径上,可额外设置有电力轨线层13’。电力轨线层13’可与电力轨线层13k设置于相同结构层上,但电力轨线层13’不会电性连接至电力轨线层13k。因此,在图4C所示出的实施例中,电力轨线层13k覆盖于具有第一导电型态的薄膜晶体管11a上方,电力轨线层13k可通过通孔13v将第一电压传递至具有第一导电型态的薄膜晶体管11a(未示出于图4C中)。电力轨线层13’覆盖于具有第二导电型态的薄膜晶体管11b上方。电力轨线层14k覆盖于所有的薄膜晶体管11a、11b(未示出于图4B中)上方,电力轨线层14j可通过通孔14j及电力轨线层13’将第二电压传递至具有第二导电型态的薄膜晶体管11b。
综上所述,本发明的芯片中通过网格形状设置多层金属走线结构,使芯片可有效降低崩裂风险,因此进一步提升芯片中的晶体管密度,并降低芯片的制造成本。
Claims (13)
1.一种芯片,包括:
一可挠基板;
多个薄膜晶体管,设置于该可挠基板上;
一重布线层,设置于该些薄膜晶体管上方;
一第一电力轨线层,设置于该重布线层上方,用以提供一第一电压至该些薄膜晶体管的多个第一导电型态的第一薄膜晶体管;以及
一第二电力轨线层,设置于该第一电力轨线层上方,用以提供一第二电压至该些薄膜晶体管的多个第二导电型态的第二薄膜晶体管,其中该第二电力轨线层以网格形状设置。
2.如权利要求1所述的芯片,还包含一天线,设置于该第二电力轨线层上方,其中该天线耦接至该些薄膜晶体管。
3.如权利要求2所述的芯片,其中该天线至该些薄膜晶体管的距离大于13微米。
4.如权利要求1所述的芯片,其中该可挠基板的可弯曲率半径小于一预设曲率半径。
5.如权利要求1所述的芯片,其中该可挠基板包含聚酰亚胺。
6.如权利要求1所述的芯片,其中在该芯片的一垂直投影中,该第二电力轨线层至少部分覆盖于该些薄膜晶体管。
7.如权利要求6所述的芯片,其中该第二电力轨线层覆盖该些薄膜晶体管的漏极区及源极区。
8.如权利要求6所述的芯片,其中该些薄膜晶体管形成多个电路区域,该第二电力轨线层覆盖该些电路区域中的一第一电路区域。
9.如权利要求6所述的芯片,其中该些薄膜晶体管中可被区分为多个第一薄膜晶体管及多个第二薄膜晶体管,该些第一薄膜晶体管具有一第一导电型态,该些第二薄膜晶体管具有一第二导电型态,该第一导电型态与该第二导电型态不同。
10.如权利要求9所述的芯片,其中该第一电力轨线层覆盖该些第一薄膜晶体管,该第二电力轨线层覆盖该些第二薄膜晶体管。
11.如权利要求10所述的芯片,其中该第一电力轨线层及该第二电力轨线层交错设置。
12.如权利要求9所述的芯片,其中该第一电力轨线层覆盖该些第一薄膜晶体管,该第二电力轨线层覆盖所有的该些薄膜晶体管。
13.如权利要求6所述的芯片,其中该第一电力轨线层覆盖所有的该些薄膜晶体管,该第二电力轨线层覆盖所有的该些薄膜晶体管。
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