CN112259467A - 一种系统封装芯片引线键合方法 - Google Patents

一种系统封装芯片引线键合方法 Download PDF

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CN112259467A
CN112259467A CN202011109856.4A CN202011109856A CN112259467A CN 112259467 A CN112259467 A CN 112259467A CN 202011109856 A CN202011109856 A CN 202011109856A CN 112259467 A CN112259467 A CN 112259467A
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徐艺轩
朱天成
张楠
候俊马
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Tianjin Jinhang Computing Technology Research Institute
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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Abstract

本发明公开了一种系统封装芯片引线键合方法,其包括以下步骤:S1:确定键合焊接流程:在芯片表面形成第一焊点,形成线弧,最后在芯片基板形成第二焊点;S2:选择键合方式:以热超声键合方式进行焊接;S3:引线材料改进加固:引线选用镀钯铜线,在铜线的表面通过电镀的方法包覆一层金属钯,使金属钯覆盖在铜线周围。本发明封装可靠性高,解决了芯片易被污染的问题,对封装工程领域有很高的参考价值。

Description

一种系统封装芯片引线键合方法
技术领域
本发明属于系统封装芯片关键工艺技术领域,涉及一种系统封装芯片引线键合方法。
背景技术
随着集成电路尺寸不断缩小以及集成度的指数性增长,系统封装芯片的可靠性测试和失效分析逐渐成为一个相当重要的环节。众所周知,系统封装芯片是由各种功率器件、有源无源器件经过封装集成后形成,所以它的性能表现和质量不仅取决于所使用电子元器件的优劣,还与整个封装过程息息相关。因此如何利用先进检测手段和微分析技术,快速确定失效芯片失效位置及模式,提供有效而及时的关于可靠性提升及改进加固措施方面的反馈,已成为当前乃至今后SiP设计及制造领域的热门课题。
封装的作用是为芯片提供电气性能连接、散热通道和机械支撑,使器件免遭受外界的理化腐蚀。通常情况下,封装可分为双列直插式(DIP)、倒装芯片(FC)、塑料方型扁平式(QFP)、塑料扁平组件式(PFP)、芯片尺寸(CSP)以及多芯片模块封装(MCM)等。而随着上世纪九十年代后集成电路技术的进步、设备的改进和亚微米技术的使用,LSI、VLSI、ULSI相继出现,硅单芯片的集成度不断提高,I/O引脚的数量急剧增加,功耗也随之大幅增大,因此,在原有封装基础上,如图1所示的球栅阵列封装技术(BGA)就逐渐成为当今主流的封装模式。而引线键合工艺作为封装中重要的一环,引线材料的好坏以及键合强度的大小对芯片性能是否能优异表现起着至关重要的作用。但由于现阶段的封装为了节约成本,采用铜线进行键合而且不能严格把控封装环境,这样极易引起键合及其他工艺出现污染,导致芯片的封装可靠性大幅降低,甚至出现功能失效。因此,如何通过现代微分析手段,找到芯片的失效机理从而实现系统封装芯片引线键合的优化设计方法就变得至关重要。
发明内容
(一)发明目的
鉴于以上所述系统封装芯片所暴露出的可靠性的问题,本发明提供一种优化的系统封装芯片引线键合方法。
(二)技术方案
为了解决上述技术问题,本发明提供一种一种系统封装芯片引线键合方法,其包括以下步骤:
S1:确定键合焊接流程
在芯片表面形成第一焊点,形成线弧,最后在芯片基板形成第二焊点;
S2:选择键合方式
以热超声键合方式进行焊接;
S3:引线材料改进加固
引线选用镀钯铜线,在铜线的表面通过电镀的方法包覆一层金属钯,使金属钯覆盖在铜线周围。
步骤S1中,引线键合有两种焊接方式:球形键合和楔形键合,球形键合在每次循环的开始会形成一个焊球,然后把这个焊球焊接在芯片基板上形成第一焊点;楔形键合则是将引线在热超声焊下用楔形劈刀直接进行焊接。
步骤S1中,球形键合时,第一焊点为球形,第二焊点为楔形;球形键合的过程为:
第一步:高电压离子化空气,高能熔化焊线顶端,形成熔融金属球;
第二步:将劈刀往下移动,将烧好的熔化金属球挤压在芯片的Pad上面,此时机台给劈刀一个超声波,然后使劈刀左右进行移动对烧球进行摩擦,同时让机台的底座持续给芯片加热,通过劈刀的超声波振动和底座给芯片加热的相互作用,使引线与芯片的铝Pad焊点的原子间能够相互扩散形成IMC合金,最后将劈刀向上提,从而形成第一焊点;
第三步:劈刀升高到引线弧度的顶端位置,根据要求移动形成所需要的线弧形式,到达第二焊点所在的位置;
第四步:在到达第二焊点也就是外管脚焊点时,通过给芯片的不断加热,再利用超声波将引线按压在铝Pad焊盘上,用压力形成楔形焊;
第五步:劈刀垂直向上移动,使引线抬起至线尾的长度,然后利用劈刀不断向上的拉力自动断线;最后重复第一步,形成一个球形键合循环。
球形键合的第二步中,超声波频率为120kHz-140kHz。
步骤S2中,在125~250℃下,利用变幅杆传递125kHz到135kHz的超声振动,使焊球与焊盘来回摩擦相互结合。
(三)有益效果
上述技术方案所提供的系统封装芯片引线键合方法,封装可靠性高,解决了芯片易被污染的问题,对封装工程领域有很高的参考价值。
附图说明
图1 BGA封装芯片示意图。
图2球形键合工艺图。
图3镀钯铜线键合面钯层分布图。
具体实施方式
为使本发明的目的、内容、和优点更加清楚,下面结合附图和实施例,对本发明的具体实施方式作进一步详细描述。
本发明系统封装芯片引线键合方法包括以下步骤:
S1:确定键合焊接流程
引线键合有两种焊接的方式:球形键合和楔形键合。
基本步骤包括:在芯片表面形成第一焊点,形成线弧,最后在芯片基板形成第二焊点。两种键合不相同在于:球形键合在每次循环的开始会形成一个焊球,然后把这个焊球焊接在芯片基板上形成第一焊点;楔形键合则是将引线在热超声焊下用楔形劈刀直接进行焊接。
在对失效样品进行失效分析时发现,其采用的焊接流程是球形键合。那么在对其引线材料、键合工艺及参数进行改进加固措施研究时,有必要应用“控制变量法”,即对加固改进的芯片应当采用同样的球形键合焊接及封装工艺。
下面对球形键合焊接流程进行分析,见附图2,第一焊点为球形,第二焊点为楔形:
第一步:高电压离子化空气,高能熔化焊线顶端,形成熔融金属球;
第二步:将劈刀往下移动,将烧好的熔化金属球挤压在芯片的Pad上面,此时机台会给劈刀一个超声波(频率处于120kHz-140kHz),然后使劈刀快速的左右进行移动对烧球进行摩擦,同时让机台的底座不断给芯片加热,通过劈刀的超声波振动和底座给芯片加热的相互作用,使引线与芯片的铝Pad焊点的原子间能够相互扩散形成IMC合金,最后将劈刀向上提,从而形成第一焊点;
第三步:劈刀升高到引线弧度的顶端位置根据要求移动形成所需要的线弧形式,到达第二焊点所在的位置;
第四步:在到达第二焊点也就是外管脚焊点时,通过给芯片的不断加热,再利用超声波将引线按压在铝Pad焊盘上,用压力形成楔形焊;
第五步:劈刀垂直向上移动,使引线抬起至线尾的长度,然后利用劈刀不断向上的拉力自动断线。最后重复第一步,形成一个球形键合循环。
S2:选择键合方式
热超声键合所需压力低,具备了热压焊和超声焊的优点,在125~250℃下,利用变幅杆传递125kHz到135kHz的超声振动,最终使焊球与焊盘来回摩擦相互结合。超声和热能的配合,降低超声波频率和焊接压力,避免晶粒受到压力损坏。
S3:引线材料改进加固
镀钯铜线就是在铜线的表面通过电镀的方法包覆一层很薄的金属钯,使金属钯覆盖在铜线周围。钯是一种极其不活泼的金属,化学性质稳定,常温时在空气和潮湿环境中不易发生氧化反应,可作为抗氧化层,有效改善铜线被氧化的问题。而且由于镀钯层覆盖在铜线和键合球的外部,有效阻挡了外界卤族元素和硫元素对键合IMC的污染。若钯完全包覆在铜线周围,当键合工艺及金属间化合物的形成稳定后,主要以被钯包覆的Cu9Al4为主,在键合区附近钯的含量最大,距离键合区域越远的铜线IMC钯含量逐渐降低,如图3所示。
由上述技术方案可以看出,本发明针对键合腐蚀失效的样品进行了改进加固措施的研究,首先对失效样品的改进芯片应当采用的球形焊接和超声焊键合进行了详细地分析;接着对失效样品的键合引线进行改进,并应用于改进后的同类型芯片当中去,改进芯片引线材料分别采用了镀钯铜线和金线,封装形式都采用引线键合互连的BGA封装,键合流程及方式都采用热超声焊球形键合,在对两种芯片封装好并进行可靠性测试后开封,分别选取10条键合线进行IMC覆盖率测试,20条键合线进行剪切测试:镀钯铜线的IMC覆盖率均值为88.07%,键合强度提升16%,金线为85.38%(≥85%),强度提升12%;剪切测试均值超过国际标准14gF,因此可分析得到引线改进措施的正确性与可行性;最后针对键合参数进行改进加固,并对键合工艺和封装材料的改进提出了一些建设性的改良措施,解决了芯片易被污染的问题,对封装工程领域有很高的参考价值。
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明技术原理的前提下,还可以做出若干改进和变形,这些改进和变形也应视为本发明的保护范围。

Claims (6)

1.一种系统封装芯片引线键合方法,其特征在于,包括以下步骤:
S1:确定键合焊接流程
在芯片表面形成第一焊点,形成线弧,最后在芯片基板形成第二焊点;
S2:选择键合方式
以热超声键合方式进行焊接;
S3:引线材料改进加固
引线选用镀钯铜线,在铜线的表面通过电镀的方法包覆一层金属钯,使金属钯覆盖在铜线周围。
2.如权利要求1所述的系统封装芯片引线键合方法,其特征在于,步骤S1中,引线键合有两种焊接方式:球形键合和楔形键合,球形键合在每次循环的开始会形成一个焊球,然后把这个焊球焊接在芯片基板上形成第一焊点;楔形键合则是将引线在热超声焊下用楔形劈刀直接进行焊接。
3.如权利要求2所述的系统封装芯片引线键合方法,其特征在于,步骤S1中,球形键合时,第一焊点为球形,第二焊点为楔形;球形键合的过程为:
第一步:高电压离子化空气,高能熔化焊线顶端,形成熔融金属球;
第二步:将劈刀往下移动,将烧好的熔化金属球挤压在芯片的Pad上面,此时机台给劈刀一个超声波,然后使劈刀左右进行移动对烧球进行摩擦,同时让机台的底座持续给芯片加热,通过劈刀的超声波振动和底座给芯片加热的相互作用,使引线与芯片的铝Pad焊点的原子间能够相互扩散形成IMC合金,最后将劈刀向上提,从而形成第一焊点;
第三步:劈刀升高到引线弧度的顶端位置,根据要求移动形成所需要的线弧形式,到达第二焊点所在的位置;
第四步:在到达第二焊点也就是外管脚焊点时,通过给芯片的不断加热,再利用超声波将引线按压在铝Pad焊盘上,用压力形成楔形焊;
第五步:劈刀垂直向上移动,使引线抬起至线尾的长度,然后利用劈刀不断向上的拉力自动断线;最后重复第一步,形成一个球形键合循环。
4.如权利要求3所述的系统封装芯片引线键合方法,其特征在于,球形键合的第二步中,超声波频率为120kHz-140kHz。
5.如权利要求4所述的系统封装芯片引线键合方法,其特征在于,步骤S2中,在125~250℃下,利用变幅杆传递125kHz到135kHz的超声振动,使焊球与焊盘来回摩擦相互结合。
6.一种如权利要求1-5中任一项系统封装芯片引线键合方法在系统封装芯片领域的应用。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101383304A (zh) * 2008-10-17 2009-03-11 深圳市晶导电子有限公司 沟槽式金属氧化物半导体场效应晶体管及其制造方法
CN105140201A (zh) * 2015-06-30 2015-12-09 南通富士通微电子股份有限公司 一种具有万用型封装金属片的半导体封装件及打线工艺
CN107256834A (zh) * 2017-07-05 2017-10-17 廖伟春 一种基于钯铜线的半导体键合工艺
CN107293500A (zh) * 2017-06-28 2017-10-24 华进半导体封装先导技术研发中心有限公司 一种系统级封装打线方法及装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101383304A (zh) * 2008-10-17 2009-03-11 深圳市晶导电子有限公司 沟槽式金属氧化物半导体场效应晶体管及其制造方法
CN105140201A (zh) * 2015-06-30 2015-12-09 南通富士通微电子股份有限公司 一种具有万用型封装金属片的半导体封装件及打线工艺
CN107293500A (zh) * 2017-06-28 2017-10-24 华进半导体封装先导技术研发中心有限公司 一种系统级封装打线方法及装置
CN107256834A (zh) * 2017-07-05 2017-10-17 廖伟春 一种基于钯铜线的半导体键合工艺

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