CN112242355A - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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Publication number
CN112242355A
CN112242355A CN201910645338.5A CN201910645338A CN112242355A CN 112242355 A CN112242355 A CN 112242355A CN 201910645338 A CN201910645338 A CN 201910645338A CN 112242355 A CN112242355 A CN 112242355A
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China
Prior art keywords
oxide layer
gate oxide
semiconductor device
substrate
forming
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CN201910645338.5A
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王虎
王珊珊
仇峰
张炜虎
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201910645338.5A priority Critical patent/CN112242355A/zh
Priority to US16/930,878 priority patent/US11201088B2/en
Publication of CN112242355A publication Critical patent/CN112242355A/zh
Priority to US17/450,483 priority patent/US11817355B2/en
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种半导体器件及其形成方法，其中，所述形成方法包括：提供衬底；在所述衬底上形成氧化层；刻蚀所述氧化层，形成第一栅氧层，所述第一栅氧层侧壁呈倾斜状；在相邻所述第一栅氧层之间形成第二栅氧层，所述第二栅氧层的厚度小于所述第一栅氧层；在所述第一栅氧层和所述第二栅氧层上形成多晶硅层；刻蚀所述第一栅氧层、所述多晶硅层及所述第二栅氧层至露出所述衬底，形成栅极结构。本发明形成了有倾斜状侧壁的所述第一栅氧层，以及厚度小于所述第一栅氧层的所述第二栅氧层，在半导体器件电压高处厚度较厚，在电压低处厚度较薄，在提高半导体器件击穿电压的同时，能保持较小的导通电阻，提高半导体器件的性能。

Description

半导体器件及其形成方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体器件及其形成方法。
背景技术
随着半导体技术的发展，功率集成电路(Power Integrated Circuit，简称PIC)不断在多个领域中使用，横向双扩散金属氧化物半导体晶体管(Laterally Double-diffusedMetal Oxide Semiconductor，LDMOS)具有工作电压高、工艺简单、易于同互补金属氧化物半导体(Complementary Metal Oxide Semiconductors，CMOS)在工艺上兼容等特点而作为功率器件被广泛应用于功率集成电路中。
功率器件的源漏击穿电压(BVdss)和导通电阻(Ron)特性对于高效功率电路设计至关重要，一般而言，LDMOS器件在使用上需要较高的源漏击穿电压和低的导通电阻，以提高器件的效能。但是，LDMOS器件的导通电阻和击穿电压是矛盾的指标，如果导通电阻减小，击穿电压可能降低，反之亦然。
因此，如何通过合理的设计，在满足一定击穿电压的条件下，获得尽可能低的导通电阻以降低导通损耗是目前亟待解决的问题。
发明内容
本发明解决的技术问题是提供一种半导体器件及其形成方法，使半导体器件在具有较高击穿电压的同时保持较低的导通电阻。
为解决上述技术问题，本发明实施例提供一种半导体器件的形成方法，包括：提供衬底；在所述衬底上形成氧化层；刻蚀所述氧化层，形成第一栅氧层，所述第一栅氧层侧壁呈倾斜状；在相邻所述第一栅氧层之间形成第二栅氧层，所述第二栅氧层的厚度小于所述第一栅氧层；在所述第一栅氧层和所述第二栅氧层上形成多晶硅层；刻蚀所述第一栅氧层、所述多晶硅层及所述第二栅氧层至露出所述衬底，形成栅极结构。
可选的，刻蚀所述氧化层的步骤包括：采用干法刻蚀工艺刻蚀所述氧化层，形成呈倾斜状的侧壁，所述侧壁两侧的所述衬底上剩余一定厚度的所述氧化层；采用湿法腐蚀工艺去除剩余一定厚度的所述氧化层，形成第一栅氧层。
可选的，所述干法刻蚀的刻蚀气体为C4F8、CF4和CHF3的混合气体，所述混合气体的体积比例为2:1:3。
可选的，所述第一栅氧层侧壁与所述衬底的夹角为30°至60°。
可选的，形成所述氧化层的方法为化学气相沉积法。
可选的，刻蚀所述第一栅氧层的步骤包括：采用干法刻蚀工艺，使所述第一栅氧层一侧的侧壁呈竖直状，保留另一侧呈倾斜状的侧壁，在所述呈竖直状侧壁一侧的所述衬底上剩余一定厚度的所述第一栅氧层；采用湿法腐蚀工艺去除剩余一定厚度的所述第一栅氧层。
可选的，所述干法刻蚀的刻蚀气体为CF4和CHF3的混合气体。
可选的，所述湿法腐蚀的腐蚀液为氢氟酸。
可选的，刻蚀所述多晶硅层和所述第二栅氧层的步骤包括：采用干法刻蚀工艺刻蚀所述多晶硅层至露出所述第二栅氧层；采用干法刻蚀工艺刻蚀所述第二栅氧层至露出所述衬底。
可选的，干法刻蚀所述多晶硅层的刻蚀气体为溴化氢和氯气。
可选的，干法刻蚀所述第二栅氧层的刻蚀气体为溴化氢和氦气。
可选的，在形成栅极结构后，在所述栅极结构两侧的所述衬底内形成源区和漏区，所述源区靠近所述第一栅氧层呈倾斜状的侧壁，所述漏区靠近所述第一栅氧层呈竖直状的侧壁。
利用上述方法形成的一种半导体器件，包括：衬底；栅极结构，位于所述衬底上，所述栅极结构包括第一栅氧层、第二栅氧层和多晶硅层，其中：所述第一栅氧层位于所述衬底上，且所述第一栅氧层一侧的侧壁呈倾斜状，另一侧的侧壁呈竖直状；所述第二栅氧层位于所述第一栅氧层呈倾斜状侧壁一侧的所述衬底上，且所述第二栅氧层厚度小于所述第一栅氧层；所述多晶硅层位于所述第一栅氧层和所述第二栅氧层表面。
可选的，所述半导体器件还包括：源区和漏区，所述源区和漏区位于所述栅极结构两侧的所述衬底内，所述源区靠近所述第一栅氧层呈倾斜状的侧壁，所述漏区靠近所述第一栅氧层呈竖直状的侧壁。
与现有技术相比，本发明实施例的技术方案具有以下有益效果：
所述第一栅氧层侧壁呈倾斜状，所述第一栅氧层的厚度由中间向倾斜处逐渐减小，形成的第二栅氧层厚度小于所述第一栅氧层，所述第一栅氧层和所述第二栅氧层结合形成厚度不一、阶梯状的栅氧层。若完全采用所述第一栅氧层，能达到耐压要求，但是半导体器件在后续工作过程中，形成反型层时，过厚的栅氧层电容小，会导致器件开启相对困难，响应速度慢。若完全采用所述第二栅氧层，又由于栅氧层厚度不够达不到耐压要求。采用所述第一栅氧层和所述第二栅氧层结合，既能提高击穿电压，又能降低导通电阻。
进一步，形成所述源区和所述漏区，且所述源区靠近所述第一栅氧层呈倾斜状的侧壁，所述漏区靠近所述第一栅氧层呈竖直状的侧壁。半导体器件在后续工作时，电场强度在靠近所述漏区最大，从所述漏区向所述源区逐渐减小，所以在靠近所述源区时，不需要栅氧层的厚度太厚，通过使所述第一栅氧层侧壁呈倾斜状和所述第二栅氧层来降低厚度。半导体器件在后续工作时，在所述第一栅氧层的倾斜处和所述第二栅氧层下方的所述衬底表面形成反型层时，由于栅氧层厚度降低，使器件更容易开启，提高响应速度。
附图说明
图1至图8是本发明半导体器件的形成方法一实施例中各步骤对应的结构示意图。
具体实施方式
由背景技术可知，LDMOS器件在使用上需要较高的源漏击穿电压和低的导通电阻，以提高器件的效能。但是，LDMOS器件的导通电阻和击穿电压是矛盾的指标，如果导通电阻减小，击穿电压可能降低，反之亦然。
传统的提高LDMOS击穿电压的方法是形成场氧化层(Field Oxide)，场氧化层的形成通常采用硅的局部氧化法，用氮化物作为掩膜层，对硅进行热氧化处理形成氧化层。由于氧化层比消耗的硅更厚，所以在氮化物掩膜下的氧化生长将抬高氮化物的边缘，产生“鸟嘴效应”，形成漏电通道，不利于半导体器件的耐压性。并且，如果通过提高栅氧层的厚度来提高击穿电压，又会导致器件导通电阻变大，响应速度变慢。
为了解决上述技术问题，发明人经过研究，提供了一种半导体器件的形成方法，在半导体衬底上先形成氧化层，再刻蚀所述氧化层形成第一栅氧层，所述第一栅氧层侧壁呈倾斜状，在相邻所述第一栅氧层之间形成第二栅氧层，所述第二栅氧层厚度小于所述第一栅氧层。所述第一栅氧层由于侧壁的倾斜，中间向侧壁厚度逐渐减小，与所述第二栅氧层结合，形成阶梯状栅氧化层。一方面，不采用通过消耗硅的方式来生长氧化层，而是直接在衬底上形成所述氧化层，避免发生“鸟嘴效应”；另一方面，所述半导体器件在后续工作过程中，电压值从所述第一栅氧层倾斜拐角处至倾斜侧壁方向逐渐减小，因此所述第一栅氧层在中间至倾斜拐角处的厚度较厚，不容易被击穿，可以提高半导体器件的击穿电压，在电压值较小的地方不需要栅氧层厚度太厚，因此使所述栅氧层厚度从所述第一栅氧层中间向侧壁、向第二栅氧层方向下降，可以使器件保持较低的导通电阻。
为使本发明的上述目的、特征和有益效果能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1至图8是本发明半导体器件的形成方法一实施例中各步骤对应的结构示意图。
参考图1，提供衬底10。
本实施例中，所述衬底10为硅衬底；其他实施例中，所述衬底10还可以是以下所提到的材料中的至少一种：锗(Ge)、硅锗(GeSi)、碳化硅(SiC)、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等等。
需要说明的是，提供衬底10的步骤中，还包括：在所述衬底10中形成浅沟槽隔离结构11。
继续参考图1，在所述衬底10上形成氧化层20。所述氧化层20的材料为氧化硅。
本实施例中，形成所述氧化层20的方法为化学气相沉积法。所述化学气相沉积法的工艺参数包括：采用正硅酸乙脂气体作为反应气体，反应压力为0.3-0.5托，温度为600-700℃。
采用化学气相沉积法直接在所述衬底10表面生成所述氧化层20，而不是采用消耗衬底的方法来形成所述氧化层20，可以避免发生“鸟嘴效应”，有利于半导体器件的耐压性。
形成所述氧化层20后，再通过高温热处理使所述氧化层20致密化。致密化有利于提高所述氧化层20的质量，有利于后续工艺的进行。
参考图2，刻蚀所述氧化层20，使所述氧化层20形成呈倾斜状的侧壁201。
本实施例中，刻蚀所述氧化层20，形成呈倾斜状的侧壁201的工艺为各向异性的干法刻蚀。所述干法刻蚀的工艺参数包括：刻蚀气体为C4F8、CF4和CHF3的混合气体，其中，所述混合气体的体积比例为2:1:3，刻蚀压强为0.05-0.15托。
刻蚀气体采用C4F8、CF4等氟碳比高的气体，刻蚀过程中会在所述侧壁201上形成副产物，所述副产物覆盖所述侧壁201，可以起到保护作用，导致越靠近所述衬底10的表面刻蚀速率越慢，从而使所述侧壁201呈倾斜状。
继续参考图2，形成呈倾斜状的所述侧壁201后，停止干法刻蚀，在所述侧壁201两侧的所述衬底上保留一定厚度的所述氧化层20。
这样做的原因在于，干法刻蚀的速率较快，如果不先保留一定厚度的所述氧化层20，直接使用干法刻蚀去除，易造成所述衬底10表面的破坏，不利于半导体器件的性能。
参考图3，采用湿法腐蚀工艺去除所述侧壁201两侧所述衬底10上的所述氧化层20，形成第一栅氧层30，所述第一栅氧层30的侧壁呈倾斜状。
具体而言，所述第一栅氧层30呈正梯形，为了方便后续说明，将所述第一栅氧层30分为矩形区域301和倾斜区域302、303，所述矩形区域301和所述倾斜区域302、303的两个拐角分别为A处和A’处。
所述第一栅氧层30的侧壁201与所述衬底10表面的夹角为30°至60°。如果所述夹角小于30°，所述第一栅氧层30厚度变化较缓，导致半导体器件开启电压大，响应速度慢；如果所述夹角大于60°，所述第一栅氧层30的厚度骤减，容易导致所述第一栅氧层30被击穿。
本实施例中，同时形成两个所述第一栅氧层30，后续工艺中直接在两个所述第一栅氧层30的基础上形成两个栅极结构，两个栅极结构之间形成共用源区，一方面可以减少工艺步骤，另一方面共用源区可以减少器件需要的面积。
其他实施例中，也可以只形成一个所述第一栅氧层30或数量大于两个的所述第一栅氧层30。
需要说明的是，形成的所述两个第一栅氧层30位于所述浅沟槽隔离结构11之间的所述衬底10上。其中，靠近所述浅沟槽隔离结构11的为所述第一栅氧层30的倾斜区域303，远离所述浅沟槽隔离结构11的为所述第一栅氧层30的倾斜区域302。
本实施例中，所述湿法腐蚀的工艺参数包括：腐蚀液为氢氟酸，所述氢氟酸的浓度为1:100。
需要说明的是，在干法刻蚀所述氧化层20的步骤前，还需要在所述氧化层20上形成一层光刻胶层(图未示)，刻蚀所述光刻胶层形成光刻胶图形，以所述光刻胶图形为掩膜刻蚀所述氧化层20。对所述氧化层20进行湿法腐蚀，形成所述第一栅氧层30后，去除所述光刻胶图形。
参考图4，在形成所述第一栅氧层30后，在所述衬底10中形成漂移区12。半导体器件在后续工作过程中，所述漂移区12用于降压。
本实施例中，所述漂移区12一侧与所述浅沟槽隔离结构11相接，另一侧不超过所述第一栅氧层30的拐角A处。
本实施例中，形成的LDMOS为N型的LDMOS，所述衬底10为P型衬底，所述漂移区12中掺杂N型的杂质离子，所述N型杂质离子为磷离子、砷离子、锑离子中的一种或几种；其他实施例中，当形成的LDMOS为P型的LDMOS时，所述衬底10为N型衬底，所述漂移区12中掺杂P型的杂质离子，所述P型杂质离子为硼离子、铟离子、镓离子中的一种或几种。
继续参考图4，在相邻所述第一栅氧层30之间形成第二栅氧层40，所述第二栅氧层40的厚度小于所述第一栅氧层30。
所述第一栅氧层30和所述第二栅氧层40的厚度的比值范围为4:1至5:1。
所述半导体器件在后续工作过程中，电压值从所述第一栅氧层30的拐角A处至所述第二栅氧层40逐渐减小，因此所述第二栅氧层40厚度不需要太厚，小于所述第一栅氧层30的厚度，可以降低半导体器件的导通电阻。
本实施例中，形成所述第二栅氧层40的方法为炉管热氧化法。所述第二栅氧层40材料为氧化硅。
参考图5，在所述第一栅氧层30和所述第二栅氧层40上形成多晶硅层50。
本实施例中，形成所述多晶硅层50的方法为化学气相沉积法。
本实施例中，所述多晶硅层50覆盖全部或者部分所述第一栅氧层30的矩形区域301以及倾斜区域302，以及所述第二栅氧层40。
需要说明的是，形成所述多晶硅层50的方法还包括：在所述多晶硅层50上形成掩膜层(图未示)，以所述掩膜层为掩膜刻蚀所述多晶硅层50，去除倾斜区域303上方或者倾斜区域303上方以及部分矩形区域301上方的所述多晶硅层50。
这样做的原因在于，所述多晶硅层50用于后续形成栅极结构，去除所述倾斜区域303上方的所述多晶硅层50，为后续在栅极结构和浅沟槽隔离结构之间形成漏区预留空间。
本实施例中，刻蚀所述多晶硅层50的工艺为干法刻蚀。
参考图6，刻蚀所述第一栅氧层30，去除所述第一栅氧层30靠近所述浅沟槽隔离结构11的所述倾斜区域303。
这样做的原因在于，为后续形成漏区预留空间，后续形成的漏区在所述浅沟槽隔离结构11以及后续形成的栅极结构之间。因此，电子从漏区向后续形成的源区传输时，不需要绕过所述浅沟槽隔离结构，电子迁移路径短，使所述半导体的导通电阻减小，提高响应速度。
本实施例中，刻蚀所述第一栅氧层30的步骤包括：采用干法刻蚀工艺去除所述倾斜区域303，形成呈竖直状的侧壁，所述倾斜区域303的所述衬底10上剩余少量所述第一栅氧层30时停止干法刻蚀。
在所述衬底10上剩余少量所述第一栅氧层30时停止干法刻蚀，可以避免干法刻蚀速率太快损坏所述衬底10，有利于后续工艺的进行。
本实施例中，所述干法刻蚀的工艺参数包括：刻蚀气体为CF4和CHF3的混合气体，其中，所述混合气体的比例为1:1-1:2，刻蚀压强为0.05-0.15托。
干法刻蚀后，再采用湿法腐蚀工艺去除剩余少量所述第一栅氧层30，形成第一栅氧层30’。所述第一栅氧层30’远离所述浅沟槽隔离结构11一侧的侧壁呈倾斜状，靠近所述浅沟槽隔离结构11一侧的侧壁呈竖直状，且所述呈竖直状侧壁与所述多晶硅层50的侧壁在竖直方向上对齐。
本实施例中，所述湿法腐蚀的工艺参数包括：腐蚀液为氢氟酸，所述氢氟酸的浓度为1:100。
参考图7，刻蚀所述多晶硅层50至露出所述第二栅氧层40。具体的，是刻蚀相邻所述第一栅氧层30’之间的所述多晶硅层50。
本实施例中，刻蚀所述多晶硅层50的方法为干法刻蚀，所述干法刻蚀的刻蚀气体为溴化氢和氯气。
参考图8，刻蚀所述第二栅氧层40至露出所述衬底10，形成栅极结构60。
本实施例中，刻蚀所述第二栅氧层40的方法为干法刻蚀，所述干法刻蚀的刻蚀气体为溴化氢和氦气。
刻蚀所述第二栅氧层40时，刻蚀气体更换为溴化氢和氦气，可以降低刻蚀速率，避免刻蚀速度太快损伤所述衬底10。
继续参考图8，形成所述栅极结构60后，在所述栅极结构60两侧的所述衬底10中形成源区101和漏区102。其中，所述源区101位于相邻两个栅极结构60之间，靠近所述第一栅氧层30’呈倾斜状的侧壁，相邻两个栅极结构60共用一个源区101，可以减小面积，有利于半导体器件的集成化。所述漏区102位于所述漂移区12内，且所述漏区102位于所述浅沟槽隔离结构11和所述栅极结构60之间，靠近所述第一栅氧层30’呈竖直状的侧壁。
形成所述源区101和所述漏区102后，再在所述源区101和所述漏区102上引出电极，形成源极和漏极。
通过本发明实施例方法形成的半导体器件，在栅源之间加上正向电压时，会在所述栅极结构60附近的所述衬底10表面形成反型层(图未示)。具体而言，所述反型层在所述倾斜区域302至所述第二栅氧层40下方的衬底10表面，因此在所述倾斜区域302，所述第一栅氧层30’的厚度逐渐降低，可以使半导体器件开启容易，提高响应速度。另外，半导体器件在工作过程中，电场强度从靠近所述漏区102至所述源区101逐渐减小，并通过漂移区降压，因此在靠近所述漏区102处，表面电场最大处，栅氧层最容易击穿，需要设置较厚的栅氧层。但是相对的，栅氧层厚度越厚，导通电阻越大，在靠近所述源区101处不需要太厚的栅氧层，为了能保持较低的导通电阻，可以将栅氧层的厚度逐渐减小。因此，本发明实施例方法形成具有呈倾斜状侧壁的所述第一栅氧层30’，厚度从所述拐角A处至倾斜侧壁逐渐减小，形成的所述第二栅氧层40厚度远小于所述第一栅氧层30，源漏极之间不需要额外的浅沟槽隔离结构，既能使半导体器件有较高的耐压性，又能保持较小的导通电阻。
另外，形成的所述源区101和所述漏区102之间没有所述浅沟槽隔离结构11，电子传输可以直接从漏极传向源极，传输路径短，可以进一步降低导通电阻，提高半导体器件的响应速度。
本发明还提供一种通过上述方法形成的半导体器件。
参考图8，所述半导体器件包括：衬底10；栅极结构60，位于所述衬底10上，所述栅极结构60包括第一栅氧层30’、第二栅氧层40和多晶硅层50，其中：所述第一栅氧层30’位于所述衬底10上，且所述第一栅氧层30’一侧的侧壁呈倾斜状，另一侧的侧壁呈竖直状；所述第二栅氧层40位于所述第一栅氧层30’呈倾斜状侧壁一侧的所述衬底10上，且所述第二栅氧层40厚度小于所述第一栅氧层30’；所述多晶硅层50位于所述第一栅氧层30’和所述第二栅氧层40表面。
所述第一栅氧层30’和所述第二栅氧层40的厚度的比值范围为4:1至5:1。
本实施例中，所述衬底10内还具有浅沟槽隔离结构11和漂移区12，所述漂移区12位于所述浅沟槽隔离结构11的一侧。
本实施例中，所述半导体器件还包括：源区101和漏区102，所述源区101和所述漏区102位于所述栅极结构60两侧的所述衬底10内。
本实施例中，所述源区101位于相邻所述栅极结构60之间，靠近所述第一栅氧层30’呈倾斜状的侧壁，相邻所述栅极结构60共用一个源极，可以提高半导体器件的集成度；所述漏区102位于所述漂移区12内，靠近所述第一栅氧层30’呈竖直状的侧壁。
半导体器件在后续工作时，表面电场在靠近所述漏区102最大，从所述漏区102到所述源区101逐渐减小，并通过所述漂移区12降压。所述第二栅氧层40厚度远小于所述第一栅氧层30’，一方面，使所述漏区102和所述源区101之间不需要额外的隔离结构，电子可以直接从所述漏区102流向所述源区101，不需要绕过隔离结构，减小电子传输路径，从而使导通电阻变小，提高半导体器件的响应速度；另一方面，在电压较大处使所述第一栅氧层30’厚度较大，在电压较小处使第一栅氧层30’呈倾斜状，再设置所述第二栅氧层40，厚度逐渐减小，既能提高半导体器件的击穿电压，又能提高半导体器件的响应速度。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (14)

1.一种半导体器件的形成方法，其特征在于，包括：
提供衬底；
在所述衬底上形成氧化层；
刻蚀所述氧化层，形成第一栅氧层，所述第一栅氧层侧壁呈倾斜状；
在相邻所述第一栅氧层之间形成第二栅氧层，所述第二栅氧层的厚度小于所述第一栅氧层；
在所述第一栅氧层和所述第二栅氧层上形成多晶硅层；
刻蚀所述第一栅氧层、所述多晶硅层及所述第二栅氧层至露出所述衬底，形成栅极结构。
2.如权利要求1所述的半导体器件的形成方法，其特征在于，刻蚀所述氧化层的步骤包括：
采用干法刻蚀工艺刻蚀所述氧化层，形成呈倾斜状的侧壁，所述侧壁两侧的所述衬底上剩余一定厚度的所述氧化层；
采用湿法腐蚀工艺去除剩余一定厚度的所述氧化层，形成第一栅氧层。
3.如权利要求2所述的半导体器件的形成方法，其特征在于，所述干法刻蚀的刻蚀气体为C4F8、CF4和CHF3的混合气体，所述混合气体的体积比例为2:1:3。
4.如权利要求1所述的半导体器件的形成方法，其特征在于，所述第一栅氧层侧壁与所述衬底的夹角为30°至60°。
5.如权利要求1所述的半导体器件的形成方法，其特征在于，形成所述氧化层的方法为化学气相沉积法。
6.如权利要求1所述的半导体器件的形成方法，其特征在于，刻蚀所述第一栅氧层的步骤包括：
采用干法刻蚀工艺，使所述第一栅氧层一侧的侧壁呈竖直状，保留另一侧呈倾斜状的侧壁，在所述呈竖直状侧壁一侧的所述衬底上剩余一定厚度的所述第一栅氧层；
采用湿法腐蚀工艺去除剩余一定厚度的所述第一栅氧层。
7.如权利要求6所述的半导体器件的形成方法，其特征在于，所述干法刻蚀的刻蚀气体为CF4和CHF3的混合气体。
8.如权利要求2或6所述的半导体器件的形成方法，其特征在于，所述湿法腐蚀的腐蚀液为氢氟酸。
9.如权利要求1所述的半导体器件的形成方法，其特征在于，刻蚀所述多晶硅层和所述第二栅氧层的步骤包括：
采用干法刻蚀工艺刻蚀所述多晶硅层至露出所述第二栅氧层；
采用干法刻蚀工艺刻蚀所述第二栅氧层至露出所述衬底。
10.如权利要求9所述的半导体器件的形成方法，其特征在于，干法刻蚀所述多晶硅层的刻蚀气体为溴化氢和氯气。
11.如权利要求9所述的半导体器件的形成方法，其特征在于，干法刻蚀所述第二栅氧层的刻蚀气体为溴化氢和氦气。
12.如权利要求6所述的半导体器件的形成方法，其特征在于，在形成栅极结构后，在所述栅极结构两侧的所述衬底内形成源区和漏区，所述源区靠近所述第一栅氧层呈倾斜状的侧壁，所述漏区靠近所述第一栅氧层呈竖直状的侧壁。
13.一种半导体器件，其特征在于，包括：
衬底；
栅极结构，位于所述衬底上，所述栅极结构包括第一栅氧层、第二栅氧层和多晶硅层，其中：
所述第一栅氧层位于所述衬底上，且所述第一栅氧层一侧的侧壁呈倾斜状，另一侧的侧壁呈竖直状；
所述第二栅氧层位于所述第一栅氧层呈倾斜状侧壁一侧的所述衬底上，且所述第二栅氧层厚度小于所述第一栅氧层；
所述多晶硅层位于所述第一栅氧层和所述第二栅氧层表面。
14.如权利要求13所述的半导体器件，其特征在于，还包括：源区和漏区，所述源区和漏区位于所述栅极结构两侧的所述衬底内，所述源区靠近所述第一栅氧层呈倾斜状的侧壁，所述漏区靠近所述第一栅氧层呈竖直状的侧壁。
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