TWI686903B - 斷閘極金氧半場效電晶體的閘極結構及其製造方法 - Google Patents

斷閘極金氧半場效電晶體的閘極結構及其製造方法 Download PDF

Info

Publication number
TWI686903B
TWI686903B TW108104022A TW108104022A TWI686903B TW I686903 B TWI686903 B TW I686903B TW 108104022 A TW108104022 A TW 108104022A TW 108104022 A TW108104022 A TW 108104022A TW I686903 B TWI686903 B TW I686903B
Authority
TW
Taiwan
Prior art keywords
trench
gate
metal oxide
effect transistor
dielectric layer
Prior art date
Application number
TW108104022A
Other languages
English (en)
Other versions
TW202030841A (zh
Inventor
蘇烱光
陳韶華
周鴻文
Original Assignee
綠星電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 綠星電子股份有限公司 filed Critical 綠星電子股份有限公司
Priority to TW108104022A priority Critical patent/TWI686903B/zh
Priority to CN201910233122.8A priority patent/CN111524969A/zh
Priority to US16/532,504 priority patent/US20200251565A1/en
Application granted granted Critical
Publication of TWI686903B publication Critical patent/TWI686903B/zh
Publication of TW202030841A publication Critical patent/TW202030841A/zh

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • H01L29/4236Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • H01L29/407Recessed field plates, e.g. trench field plates, buried field plates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66719With a step of forming an insulating sidewall spacer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • H01L29/0696Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一種斷閘極金氧半場效電晶體的閘極結構及其製造方法。所述閘極結構包括基板、磊晶層、第一閘極、第二閘極、底層介電層、閘極介電層以及閘極間介電層。磊晶層形成於基板上,並且具有延伸方向不同的第一溝渠與第二溝渠,其中第一溝渠與第二溝渠具有一重疊區域,第一溝渠的寬度大於第二溝渠的寬度,且第一溝渠的深度大於第二溝渠的深度。第一閘極位於第一溝渠內。第二閘極位於第一閘極上的第一溝渠內以及第二溝渠內。底層介電層位於第一閘極與磊晶層之間。閘極介電層位於第二閘極與磊晶層之間。閘極間介電層位於第一閘極與第二閘極之間。

Description

斷閘極金氧半場效電晶體的閘極結構及其製造方法
本發明是有關於一種溝渠式金氧半場效電晶體,且特別是有關於一種斷閘極金氧半場效電晶體的閘極結構及其製造方法。
斷閘極金氧半場效電晶體(split-gate MOSFET)也可稱為遮蔽閘極金氧半場效電晶體(shielded-gate MOSFET),其結構是將溝渠式金氧半場效電晶體內的閘極結構分為控制閘極與遮蔽閘極。而且,斷閘極金氧半場效電晶體相較於單閘極(single gate)金氧半場效電晶體擁有低導通電阻與低密勒(miller)電容的優點。
斷閘極金氧半場效電晶體需要利用溝渠(trench)的底層製作厚介電層(dielectric),所以溝渠的尺寸無法縮減。因此,當製作低崩潰電壓元件時,由於無法有效降低溝渠關鍵寬度(critical dimension, CD)來增加其元件通道(channel)密度,因此無法有效地降低導通電阻內的通道電阻(channel resistance),而對低崩潰電壓元件而言,其導通電阻大部分由通道電阻所組成,因此於相同低崩潰電壓的基礎上,斷閘極金氧半場效電晶體相較於單閘極金氧半電晶體無法有效降低導通電阻。
本發明提供一種斷閘極金氧半場效電晶體的閘極結構,能有效增加元件通道密度進而降低整體的通道電阻同時兼具斷閘極功率金氧半導體場效電晶體的效能。
本發明另提供一種斷閘極金氧半場效電晶體的閘極結構的製造方法,能製作出具有大面積的控制閘極的閘極結構,以降低通道電阻並兼具斷閘極功率金氧半導體場效電晶體的效能。
本發明的斷閘極金氧半場效電晶體的閘極結構,包括基板、磊晶層、第一閘極、第二閘極、底層介電層、閘極介電層以及閘極間介電層。磊晶層形成於基板上,並且具有延伸方向不同的第一溝渠與第二溝渠,其中第一溝渠與第二溝渠具有一重疊區域,第一溝渠的寬度大於第二溝渠的寬度,且第一溝渠的深度大於第二溝渠的深度。第一閘極位於第一溝渠內。第二閘極位於第一閘極上的第一溝渠內以及第二溝渠內。底層介電層位於第一閘極與磊晶層之間。閘極介電層位於第二閘極與磊晶層之間。閘極間介電層位於第一閘極與第二閘極之間。
在本發明的一實施例中,上述第二溝渠的寬度與第一溝渠的寬度之比小於或等於0.7。
在本發明的一實施例中,上述第二溝渠的深度與第一溝渠的深度之比小於或等於0.8。
在本發明的一實施例中,上述第一閘極還可包括一延伸部位,自第一溝渠內延伸至第二溝渠內。
在本發明的一實施例中,上述閘極間介電層還可包括位於延伸部位與第二閘極之間。
在本發明的一實施例中,上述第一溝渠與第二溝渠為井形排列。
在本發明的一實施例中,上述述第一溝渠與第二溝渠為T形排列
在本發明的一實施例中,上述第一閘極與第二閘極的材料包括多晶矽。
在本發明的一實施例中,上述磊晶層包括N型摻雜磊晶層或P型摻雜磊晶層。
本發明的斷閘極金氧半場效電晶體的閘極結構的製造方法包括於基板上形成磊晶層,再於磊晶層上形成一圖案化光罩,所述圖案化光罩具有延伸方向不同的第一開口與第二開口,其中第一開口與第二開口具有一重疊區域,且第一開口的寬度大於第二開口的寬度。接著,利用圖案化光罩作為罩幕蝕刻磊晶層,以於磊晶層中形成第一溝渠與第二溝渠,其中第一溝渠與第二溝渠具有一重疊區域,第一溝渠的寬度大於第二溝渠的寬度,且第一溝渠的深度大於第二溝渠的深度。再於第一溝渠與第二溝渠的表面形成底層介電層,於第一溝渠與第二溝渠內形成導體材料後,回蝕刻導體材料,以形成第一閘極並露出部分底層介電層。接著,移除露出的底層介電層,進行熱氧化法於第一溝渠內與第二溝渠內的側壁形成閘極介電層並同時於第一閘極上形成閘極間介電層。然後,於第一溝渠內以及第二溝渠內形成第二閘極。
在本發明的另一實施例中,上述形成底層介電層的方法包括沉積法或熱氧化法。
在本發明的另一實施例中,上述第二開口的寬度與第一開口的寬度之比小於或等於0.7。
在本發明的另一實施例中,上述第二溝渠的深度與第一溝渠的深度之比小於或等於0.8。
在本發明的另一實施例中,上述形成閘極間介電層的方法包括完全熱氧化第二溝渠內的導體材料。
在本發明的另一實施例中,上述形成閘極間介電層的方法包括部分熱氧化第二溝渠內的導體材料,以形成第一閘極的一延伸部位,自第一溝渠內延伸至第二溝渠內。
在本發明的另一實施例中,上述第一閘極與第二閘極的材料包括多晶矽。
在本發明的另一實施例中,上述磊晶層包括N型摻雜磊晶層或P型摻雜磊晶層。
基於上述,根據本發明的斷閘極金氧半場效電晶體的閘極結構,能藉由不同延伸方向的第一溝渠與第二溝渠來增加控制閘極的面積以及元件通道密度,所以能有效降低導通電阻內的通道電阻。而且,根據本發明的製造方法,藉由形成具有不同寬度的開口的光罩,能同時蝕刻形成具有不同深度與寬度的溝渠,因此本發明的製程能整合於現有製程內,無需額外黃光顯影製程,即可製作出具有大面積的控制閘極之斷閘極金氧半場效電晶體。
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
以下將參考圖式來全面地描述本發明的例示性實施例,但本發明還可按照多種不同形式來實施,且不應解釋為限於本文所述的實施例。在圖式中,為了清楚起見,各區域、部位及層的大小與厚度可不按實際比例繪製。另外,在各圖式中使用相似或相同的元件符號傾向於標示相似或相同元件或特徵的存在。圖式中的相似元件符號標示相似的元件並且將省略其贅述。
另外,關於文中所使用「包含」、「包括」、「具有」等等用語,均為開放性的用語;也就是指包含但不限於。而且,文中所提到的方向性用語,例如:「上」、「下」、「左」、「右」等,僅是用以參考圖式的方向。因此,使用的方向性用語是用來說明,而並非用來限制本發明。
圖1A是依照本發明的一實施例的一種斷閘極金氧半場效電晶體的閘極結構的截面示意圖。
請參照圖1A,本實施例的斷閘極金氧半場效電晶體的閘極結構10至少包括一基板100、一磊晶層102、一第一閘極104、一第二閘極106、一底層介電層108、一閘極介電層110以及一閘極間介電層112。在本實施例中,基板100並沒有特別地限制,如矽基板。
在本實施例中,磊晶層102形成於基板100上,基板100可為N型基板或P型基板,磊晶層102也可為N型摻雜磊晶層或P型摻雜磊晶層。較佳地,磊晶層102例如N型摻雜磊晶層。其中,磊晶層102具有延伸方向不同的第一溝渠102a與第二溝渠102b。第一溝渠102a與第二溝渠102b具有一重疊區域114,其中第一溝渠102a的寬度W1大於第二溝渠102b的寬度W2,且第一溝渠102a的深度D1大於第二溝渠102b的深度D2。在本實施例中,第二溝渠102b的寬度W2與第一溝渠102a的寬度W1之比例如小於等於0.7。當W2/W1小於等於0.7,則有利於僅用一道黃光顯影製程,即完成具有不同深度的第一溝渠102a與第二溝渠102b。
請繼續參照圖1A,第一閘極104位於第一溝渠102a。第二閘106位於第一閘極上104的第一溝渠102a內與第二溝渠102b內。其中,第一閘極104及第二閘極106的材料例如多晶矽或其它適當的導電材料,且其形成的方法例如化學氣相沉積(Chemical Vapor Deposition, CVD)、物理氣相沉積(Physical vapor deposition, PVD)或其他適當的製程。在本實施例中,第一閘極104可作為遮蔽閘極,第二閘極106可作為控制閘極,用以控制斷閘極金氧半場效電晶體的導通與斷路。此外,在本實施例中,第二溝渠102b的深度D2與第一溝渠102a的深度D1之比例如小於等於0.8。當D2/D1小於等於0.8,則有利於第一閘極104僅形成於第一溝渠102a內。
請繼續參照圖1A,底層介電層108位於第一閘極104與磊晶層102之間。在本實施例中,底層介電層108形成的方法例如沉積法(Deposition)或熱氧化法(Thermal Oxidation),但本發明不限於此。舉例來說,使用熱氧化法製作的底層介電層108在製作時例如採取較高的製程溫度(例如900℃~1200℃),因此所形成的二氧化矽具有較高的緻密性,可以作為製程前期(即,在形成第一閘極104與第二閘極106之前)的表面保護。
在本實施例中,閘極介電層110位於第二閘極106與磊晶層102之間;也就是說,閘極介電層110是形成在第一溝渠102a與第二溝渠102b的側壁。在一實施例中,閘極介電層110的形成方法例如是熱氧化法。
請繼續參照圖1A,閘極間介電層112位於第一閘極104與第二閘極106之間,其中閘極間介電層112的材料例如是氧化矽、氧化矽複合層、或其他氧化矽的材料。另外,由於製程的緣故,閘極間介電層112亦可位於第二溝渠102a中的底層介電層108與第二閘極106之間(未繪示)。在一實施例中,閘極間介電層112例如是單層結構或多層結構。在本實施例中,閘極間介電層112是以單層結構為例。而且,在另一實施例中,閘極間介電層112可藉由製程設計而與閘極介電層110同時形成,但本發明並不限於此。
由於本實施例的第一溝渠102a的寬度W1大於第二溝渠102b的寬度W2,且控制前述寬度之比(W1/W2)小於等於0.7時,可以在增加第二閘極106(控制閘極)的面積的同時僅用一道光罩即完成不同深度的溝渠,因此可以在不大幅變更現有製程的情況下,有效增加元件通道密度,並降低通道電阻。
圖1B是圖1A的另一種變形例的截面示意圖,其中使用與圖1A相同的元件符號來表示相同或近似的部份,並且其相關描述在此不予贅述。
請參照圖1B。圖1B與圖1A的結構差異在於,第一閘極104還可包括一延伸部位116,自第一溝渠102a內延伸至第二溝渠102b內,且延伸部位116位於磊晶層102與閘極間介電層112之間。其中,延伸部位116是第一閘極104的一部分,因此其材料與第一閘極104相同,例如是多晶矽,在本實施例中,由於延伸部位116與第一閘極104具有相同的電位,所以可增進第一閘極104在降低閘極-汲極電容(C gd)方面以及提高崩潰電壓方面的功效。而且,第一閘極104的結構能依照需求作變更,不限於圖1A或者圖1B所示的內容。
另外,本發明的斷閘極金氧半場效電晶體的閘極結構10除了上述圖1A與圖1B的實施例,還可有其它變形例。
圖2A是依照本發明的另一實施例的一種斷閘極金氧半場效電晶體的閘極結構的俯視圖。圖2B是圖2A的另一種變形例的俯視圖。
以下,將藉由圖2A來說明本發明實施例中的斷閘極金氧半場效電晶體的閘極結構20的俯視圖,其中相同或相似元件使用相同或相似標號,其材料、製程及功效於上述實施例已進行詳盡地描述,故不再重複贅述。
請參照圖2A,在本實施例中,第一溝渠202a與第二溝渠202b為十字形排列,其中第二閘極206設置在第一溝渠202a與第二溝渠202b內,且第一溝渠202a與第二溝渠202b具有重疊區域214。在另一實施中,第一溝渠202a與第二溝渠202b為T字形排列(如圖2B所示),但本發明不以此為限,第一溝渠202a與第二溝渠202b的相對配置位置能依照需求進行調整。
圖3A至圖3I是沿圖2A的A-A'線的製造流程剖面示意圖。
請先參照圖3A,於基板200上形成磊晶層202。在本實施例中,基板200並沒有特別地限制。磊晶層202例如是N型摻雜磊晶層。之後,於磊晶層202上形成圖案化光罩300,以暴露出部分磊晶層202;也就是說,於磊晶層202上的圖案化光罩300具有延伸方向不同的第一開口302a與第二開口302b,其中第一開口302a與第二開口302b具有一重疊區域,且第一開口302a的寬度W5大於第二開口302b的寬度W6,其中第二開口302b的寬度W6與第一開口302a的寬度W5之比譬如小於等於0.7。當W6/W5小於等於0.7,則有利於後續用一道黃光顯影製程即形成具有不同深度的溝渠。
接著,請參照圖3B,利用圖案化光罩300作為罩幕蝕刻磊晶層202,以形成第一溝渠202a與第二溝渠202b,然後移除圖案化光罩300。其中,第一溝渠202a與第二溝渠202b具有一重疊區域214(如圖2A所示),且第一溝渠202a的寬度W3大於第二溝渠202b的寬度W4。詳細地說,由於圖案化光罩300的第一開口302a與第二開口302b的寬度不同,於蝕刻製程後所形成的第一溝渠202a與第二溝渠202b的深度也會不同;也就是說,較寬的第一溝渠202a的深度D3會大於較窄的第二溝渠202b的深度D4。
在本實施例中,第二溝渠202b的寬度W4與第一溝渠202a的寬度W3之比小於等於0.7。此外,在本實施例中,第二溝渠202b的深度D4與第一溝渠202a的深度D3之比可小於等於0.8。
然後,請參照圖3C,於第一溝渠202a與第二溝渠202b的表面形成底層介電層208。形成底層介電層208的方法例如沉積法或熱氧化法。舉例來說,使用熱氧化法製作底層介電層208時,可採取較高的製程溫度(例如900℃~1200℃),因此所形成的底層介電層208的材料(例如是二氧化矽)具有較高的緻密性。
接著,請參照圖3D,於第一溝渠202a與第二溝渠202b內形成導體材料304,其中導體材料304例如是多晶矽。在本實施例中,形成導體材料304的步驟如下:首先,藉由化學氣相沉積、物理氣相沉積或其他適當的成膜製程於第一溝渠202a與第二溝渠202b內形成導體材料304,之後以化學機械研磨方式或蝕刻的方式將第一溝渠202a與第二溝渠202b以外的導體材料304去除。
再來,請參照圖3E,可對所述導體材料304進行回蝕刻,於第一溝渠202a內形成第一閘極204,並暴露出第一溝渠202a與第二溝渠202b內的部分底層介電層208。另外,在其他實施例中,還可在回蝕刻先進行化學機械研磨(Chemical Mechanical Polishing, CMP)製程,先去除第一溝渠202a之外的導體材料304。
接著,請參照圖3F,移除露出的底層介電層208。在本實施例中,移除露出的底層介電層206的方法例如是進行濕式蝕刻製程去除第一溝渠202a內與第二溝渠202b內的部分底層介電層208。持續移除底層介電層208的製程,使部分第一閘極204與部分導體材料304露出,以利後續進行熱氧化。
而後,請參照圖3G,進行熱氧化法,以於第一溝渠202a內與第二溝渠202b內的側壁形成閘極介電層210,並同時於第一閘極204上形成閘極間介電層212,而且第一閘極204上的閘極間介電層212相較於第一溝渠202a內的閘極介電層210厚。也就是說,在圖3G顯示閘極介電層210大部分是在第一溝渠202a與第二溝渠202b的側壁,而且閘極間介電層212位於第一閘極204上。特別一提的是,在本實施例中,露出的部分第一閘極204會氧化成閘極間介電層212,而且位於第二溝渠202b內的導體材料304經由熱氧化法完全氧化成閘極間介電層212。
此外,在本實施例中,於第二溝渠202b內形成閘極間介電層212的方法包括完全熱氧化第二溝渠202b內的導體材料304。在另一實施例中,於第二溝渠202b內形成閘極間介電層212的方法包括部分熱氧化第二溝渠202b內的導體材料304,並以形成第一閘極204的一延伸部位,自第一溝渠202a內延伸至第二溝渠202b內,且所述延伸部位可位於磊晶層202與閘極間介電層212之間。其中,所述延伸部位是第一閘極204的一部分,因此其材料與第一閘極204相同,例如是多晶矽,在本實施例中,所述延伸部位與第一閘極204具有相同的電位。
接著,請參照圖3H,於第一溝渠202a內以及第二溝渠202b內形成第二閘極206,且第二閘極206位於閘極間介電層214上。其中,第二閘極206例如是藉由化學氣相沉積、物理氣相沉積或其他適當的成膜製程於第一溝渠202a與第二溝渠202b內形成的導體層,並對所述導體層進行化學機械研磨製程或蝕刻而形成,其中導體層例如是多晶矽。此外,在本實施例中,第一閘極204的材料可與第二閘極206的材料相同;也就是說,第一閘極204與第二閘極206的材料例如是多晶矽。在本實施例中,第一閘極204可作為遮蔽閘極,第二閘極206可作為控制閘極,用以控制斷閘極金氧半場效電晶體的導通與斷路。
在形成閘極結構之後,請參照圖3I,可利用離子植入製程等方式,於磊晶層202內形成井區306,再於磊晶層202表面形成源極區308。在本實施例中,基板200例如是具N+型摻雜的基板,可作為斷閘極金氧半場效電晶體的汲極區(drain);井區306例如是P型井;源極區308例如是N+摻雜區。在另一實施例中,可在形成第一溝渠202a與第二溝渠202b之前,就在磊晶層202內先形成井區306與源極區308。
由於本實施例第一溝渠202a的寬度W3大於第二溝渠202b的寬度W4,且控制前述寬度之比(W4/W3)小於等於0.7時,可以在增加第二閘極216(控制閘極)的密度的同時,僅用一道光罩即完成不同深度的溝渠,因此可以整合於現有製程,達到有效增加元件通道密度,並降低通道電阻的功效。
綜上所述,本發明藉由同時用一道光罩形成不同寬度及深度的第一溝渠與第二溝渠,而且在不大幅變更現有製程的情況下,能有效增加第二閘極的密度,降低元件導通時的通道電阻。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10、20:斷閘極金氧半導體場效電晶體的閘極結構 100、200:基板 102、202:磊晶層 102a、202a:第一溝渠 102b、202b:第二溝渠 104、204:第一閘極 106、206:第二閘極 108、208:底層介電層 110、210:閘極介電層 112、212:閘極間介電層 114、214:重疊區域 116:延伸部位 300:圖案化光罩 302a:第一開口 302b:第二開口 304:導體材料 306:井區 308:源極區 W1、W2、W3、W4、W5、W6:寬度 D1、D2、D3、D4:深度
圖1A是依照本發明的一實施例的一種斷閘極金氧半場效電晶體的閘極結構的截面示意圖。 圖1B是圖1A的另一種變形例的截面示意圖。 圖2A是依照本發明的另一實施例的一種斷閘極金氧半場效電晶體的閘極結構的俯視圖。 圖2B是圖2A的另一種變形例的俯視圖。 圖3A至圖3I是沿圖2A的A-A'線的製造流程剖面示意圖。
10:斷閘極金氧半導體場效電晶體的閘極結構
100:基板
102:磊晶層
102a:第一溝渠
102b:第二溝渠
104:第一閘極
106:第二閘極
108:底層介電層
110:閘極介電層
112:閘極間介電層
114:重疊區域
W1、W2:寬度
D1、D2:深度

Claims (17)

  1. 一種斷閘極金氧半場效電晶體的閘極結構,包括: 基板; 磊晶層,形成於所述基板上,且所述磊晶層具有延伸方向不同的第一溝渠與第二溝渠,其中所述第一溝渠與所述第二溝渠具有一重疊區域,所述第一溝渠的寬度大於所述第二溝渠的寬度,且所述第一溝渠的深度大於所述第二溝渠的深度; 第一閘極,位於所述第一溝渠內; 第二閘極,位於所述第一閘極上的所述第一溝渠內以及所述第二溝渠內; 底層介電層,位於所述第一閘極與所述磊晶層之間; 閘極介電層,位於所述第二閘極與所述磊晶層之間;以及 閘極間介電層,位於所述第一閘極與所述第二閘極之間。
  2. 如申請專利範圍第1項所述的斷閘極金氧半場效電晶體的閘極結構,其中所述第二溝渠的所述寬度與所述第一溝渠的所述寬度之比小於或等於0.7。
  3. 如申請專利範圍第1項所述的斷閘極金氧半場效電晶體的閘極結構,其中所述第二溝渠的所述深度與所述第一溝渠的所述深度之比例小於或等於0.8。
  4. 如申請專利範圍第1項所述的斷閘極金氧半場效電晶體的閘極結構,其中所述第一閘極更包括一延伸部位,自所述第一溝渠內延伸至所述第二溝渠內。
  5. 如申請專利範圍第4項所述的斷閘極金氧半場效電晶體的閘極結構,其中所述閘極間介電層更包括位於所述延伸部位與所述第二閘極之間。
  6. 如申請專利範圍第1項所述的斷閘極金氧半場效電晶體的閘極結構,其中所述第一溝渠與所述第二溝渠為十字形排列。
  7. 如申請專利範圍第1項所述的斷閘極金氧半場效電晶體的閘極結構,其中所述第一溝渠與所述第二溝渠為T形排列。
  8. 如申請專利範圍第1項所述的斷閘極金氧半場效電晶體,其中所述第一閘極與所述第二閘極的材料包括多晶矽。
  9. 如申請專利範圍第1項所述的斷閘極金氧半場效電晶體的閘極結構,其中所述磊晶層包括N型摻雜磊晶層或P型摻雜磊晶層。
  10. 一種斷閘極金氧半場效電晶體的閘極結構的製造方法,包括: 於基板上形成磊晶層; 於所述磊晶層上形成一圖案化光罩,所述圖案化光罩具有延伸方向不同的第一開口與第二開口,其中所述第一開口與所述第二開口具有一重疊區域,且所述第一開口的寬度大於所述第二開口的寬度; 利用所述圖案化光罩作為罩幕蝕刻所述磊晶層,以於所述磊晶層中形成第一溝渠與第二溝渠,其中所述第一溝渠與所述第二溝渠具有一重疊區域,所述第一溝渠的寬度大於所述第二溝渠的寬度,且所述第一溝渠的深度大於所述第二溝渠的深度; 於所述第一溝渠與所述第二溝渠的表面形成底層介電層; 於所述第一溝渠與所述第二溝渠內形成導體材料; 回蝕刻所述導體材料,以形成第一閘極並露出部分所述底層介電層; 移除露出的所述底層介電層; 進行熱氧化法,以於所述第一溝渠內與所述第二溝渠內的側壁形成閘極介電層並同時於所述第一閘極上形成閘極間介電層;以及 於所述第一溝渠內以及所述第二溝渠內形成第二閘極。
  11. 如申請專利範圍第10項所述的斷閘極金氧半場效電晶體的閘極結構的製造方法,其中形成所述底層介電層的方法包括沉積法或熱氧化法。
  12. 如申請專利範圍第10項所述的斷閘極金氧半場效電晶體的閘極結構的製造方法,其中所述第二開口的所述寬度與所述第一開口的所述寬度之比小於或等於0.7。
  13. 如申請專利範圍第10項所述的斷閘極金氧半場效電晶體的閘極結構的製造方法,其中所述第二溝渠的所述深度與所述第一溝渠的所述深度之比例小於或等於0.8。
  14. 如申請專利範圍第10項所述的斷閘極金氧半場效電晶體的閘極結構的製造方法,其中形成所述閘極間介電層的方法包括完全熱氧化所述第二溝渠內的所述導體材料。
  15. 如申請專利範圍第10項所述的斷閘極金氧半場效電晶體的閘極結構的製造方法,其中形成所述閘極間介電層的方法包括部分熱氧化所述第二溝渠內的所述導體材料,以形成所述第一閘極的一延伸部位,自所述第一溝渠內延伸至所述第二溝渠內。
  16. 如申請專利範圍第10項所述的斷閘極金氧半場效電晶體的閘極結構的製造方法,其中所述第一閘極與所述第二閘極的材料包括多晶矽。
  17. 如申請專利範圍第10項所述的斷閘極金氧半場效電晶體的閘極結構的製造方法,其中所述磊晶層包括N型摻雜磊晶層或P型摻雜磊晶層。
TW108104022A 2019-02-01 2019-02-01 斷閘極金氧半場效電晶體的閘極結構及其製造方法 TWI686903B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW108104022A TWI686903B (zh) 2019-02-01 2019-02-01 斷閘極金氧半場效電晶體的閘極結構及其製造方法
CN201910233122.8A CN111524969A (zh) 2019-02-01 2019-03-26 断栅极金属氧化物半导体场效应晶体管的栅极结构及其制造方法
US16/532,504 US20200251565A1 (en) 2019-02-01 2019-08-06 Gate structure of split-gate metal oxide semiconductor field effect transistor and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW108104022A TWI686903B (zh) 2019-02-01 2019-02-01 斷閘極金氧半場效電晶體的閘極結構及其製造方法

Publications (2)

Publication Number Publication Date
TWI686903B true TWI686903B (zh) 2020-03-01
TW202030841A TW202030841A (zh) 2020-08-16

Family

ID=70766888

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108104022A TWI686903B (zh) 2019-02-01 2019-02-01 斷閘極金氧半場效電晶體的閘極結構及其製造方法

Country Status (3)

Country Link
US (1) US20200251565A1 (zh)
CN (1) CN111524969A (zh)
TW (1) TWI686903B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3859788A1 (en) * 2020-01-29 2021-08-04 Infineon Technologies Austria AG Transistor device and method of forming a field plate in an elongate active trench of a transistor device
DE102020121309B4 (de) 2020-08-13 2024-07-18 Infineon Technologies Ag Erste und zweite grabenstrukturen enthaltende leistungshalbleitervorrichtung und verfahren zu deren herstellung
CN114122123B (zh) * 2022-01-26 2022-04-22 成都蓉矽半导体有限公司 集成高速续流二极管的碳化硅分离栅mosfet及制备方法
CN117790578B (zh) * 2024-01-05 2024-07-12 南京第三代半导体技术创新中心有限公司 一种SiC MOSFET器件及制造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201816858A (zh) * 2016-05-18 2018-05-01 杰力科技股份有限公司 功率金氧半導體場效電晶體的製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008034649A (ja) * 2006-07-28 2008-02-14 Sanyo Electric Co Ltd 半導体装置
JP4294050B2 (ja) * 2006-12-27 2009-07-08 三洋電機株式会社 半導体装置およびその製造方法
CN101656213B (zh) * 2008-08-19 2012-09-26 尼克森微电子股份有限公司 沟槽栅金属氧化物半导体场效应晶体管及其制作方法
JP5580150B2 (ja) * 2010-09-09 2014-08-27 株式会社東芝 半導体装置
US8759908B2 (en) * 2011-11-01 2014-06-24 Alpha And Omega Semiconductor Incorporated Two-dimensional shielded gate transistor device and method of manufacture
JP6808348B2 (ja) * 2016-04-28 2021-01-06 キヤノン株式会社 光電変換装置およびカメラ

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201816858A (zh) * 2016-05-18 2018-05-01 杰力科技股份有限公司 功率金氧半導體場效電晶體的製造方法

Also Published As

Publication number Publication date
CN111524969A (zh) 2020-08-11
US20200251565A1 (en) 2020-08-06
TW202030841A (zh) 2020-08-16

Similar Documents

Publication Publication Date Title
TWI686903B (zh) 斷閘極金氧半場效電晶體的閘極結構及其製造方法
TWI436479B (zh) 一種低阻高壓mosfet器件及其製造方法
US8747992B2 (en) Non-uniform semiconductor device active area pattern formation
JP2005039270A (ja) メモリ素子およびその製造方法
TWI696288B (zh) 遮蔽閘金氧半場效電晶體及其製造方法
WO2009041743A1 (ja) トレンチゲート型トランジスタ及びその製造方法
TW200536122A (en) Finfet transistor device on soi and method of fabrication
JP6198292B2 (ja) 半導体装置および半導体装置の製造方法
TW201338053A (zh) 半導體結構與其製造方法
TW201423869A (zh) 溝渠式電晶體的製作方法
TW200903655A (en) Method of fabricating high-voltage MOS having doubled-diffused drain
JP2009130357A (ja) トレンチmosfet及びその製造方法
JP2004158680A (ja) 半導体装置およびその製造方法
KR101382328B1 (ko) 반도체 소자 및 그 제조 방법
TWI750375B (zh) 溝槽閘極金氧半場效電晶體及其製造方法
KR100871976B1 (ko) 반도체 소자 및 그 제조 방법
JP2009070849A (ja) 半導体装置
TWI689098B (zh) 複合型溝槽式金氧半場效應電晶體及其製造方法
TWI498949B (zh) 半導體裝置及其製造方法
TWI458022B (zh) 低閘極電荷的溝槽式功率半導體製造方法
TWI528424B (zh) 於金氧半場效電晶體形成遮蔽閘之方法
JP5358653B2 (ja) トレンチゲート型トランジスタの製造方法
KR101427954B1 (ko) 반도체 소자 및 그 제조 방법
CN115775830B (zh) 屏蔽栅功率器件及其制备方法
TWI804303B (zh) 寄生接面場效電晶體阻抗的降低方法