CN112201642A - 包括连接介质和功率半导体部件的功率电子开关装置 - Google Patents
包括连接介质和功率半导体部件的功率电子开关装置 Download PDFInfo
- Publication number
- CN112201642A CN112201642A CN202010646235.3A CN202010646235A CN112201642A CN 112201642 A CN112201642 A CN 112201642A CN 202010646235 A CN202010646235 A CN 202010646235A CN 112201642 A CN112201642 A CN 112201642A
- Authority
- CN
- China
- Prior art keywords
- connection
- switching device
- semiconductor component
- power semiconductor
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0605—Shape
- H01L2224/06051—Bonding areas having different shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
- H01L2224/3001—Structure
- H01L2224/3003—Layer connectors having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
- H01L2224/3005—Shape
- H01L2224/30051—Layer connectors having different shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/32237—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Materials Engineering (AREA)
- Inverter Devices (AREA)
- Dc-Dc Converters (AREA)
- Power Conversion In General (AREA)
Abstract
提出一种功率电子开关装置,功率电子开关装置包括基板,该基板具有绝缘材料体以及布置在其上的第一和第二导体轨道;功率电子开关装置包括功率半导体部件,该功率半导体部件导电地连接到第一导体轨道;并且功率电子开关装置包括连接装置,该连接装置将所述功率半导体部件连接到基板的第二导体轨道并且在功率半导体部件和第二导体轨道之间的部分中具有弓形路线,其中第一导体轨道具有凹陷,凹陷具有指定的深度,并且功率半导体部件布置在所述凹陷中。
Description
技术领域
本发明描述了一种功率电子开关装置,功率电子开关装置包括基板,该基板具有绝缘材料体以及布置在其上的第一导体轨道和第二导体轨道;功率电子开关装置包括功率半导体部件,该功率半导体部件导电地连接到第一导体轨道;并且功率电子开关装置包括连接装置,该连接装置将所述功率半导体部件连接到基板的第二导体轨道。
背景技术
作为现有技术,DE 10 2007 006 706 A1公开了一种电路布置,电路布置包括基板;布置在所述基板的主表面上的导体轨道;至少一个半导体部件,半导体部件通过其第一主表面布置在第一导体轨道上;以及导电连接装置,导电连接装置与半导体部件的第二主表面的至少一个接触区域连接。在这种情况下,半导体部件与第一导体轨道和/或连接装置的连接实施为压力烧结连接,并且在连接装置与半导体部件的指定的边缘之间布置绝缘材料。
借助于提及的现有技术的知识,本发明是基于提出一种功率电子开关装置的目的,其中改进了连接装置的布置。
发明内容
根据本发明,该目的通过功率电子开关装置来实现,其包括基板、功率半导体部件和连接装置,所述基板具有绝缘材料体和布置在其上的第一导体轨道和第二导体轨道,所述功率半导体部件导电地连接到第一导体轨道,所述连接装置将所述功率半导体部件连接到基板的第二导体轨道并且在功率半导体部件和第二导体轨道之间的部分中具有弓形路线,其中第一导体轨道具有凹陷,凹陷具有指定的深度,并且功率半导体部件布置在所述凹陷中。
可能有利的是,如果连接装置实施为结合连接,特别是导线结合连接。其有利的替代方案是作为薄膜复合材料的实施例,特别地其包括面对基板和功率半导体部件的第一导电薄膜、在薄膜复合材料中跟随的电绝缘薄膜、以及在薄膜复合材料中进一步跟随的第二导电薄膜。在这种情况下,优选的是,薄膜复合材料的导电薄膜的相应厚度在10μm至500μm之间,优选在50μm至250μm之间,并且薄膜复合材料的电绝缘薄膜的厚度在2μm至200μm之间,优选在10μm至100μm之间。
也可能优选的是,如果在每种情况下,在连接装置和第二导体轨道之间的导电连接以及在连接装置和功率半导体部件之间的导电连接彼此独立地实施为力锁定连接或材料结合连接,特别是实施为钎焊连接或实施为焊接连接,特别是实施为激光焊接连接,或实施为烧结连接或实施为粘合结合连接。
在第一有利的配置中,凹陷的深度的尺寸以这种方式形成,使得如果连接介质存在的话,其至少是功率半导体部件与连接介质一起的厚度的一半,连接介质布置在所述功率半导体部件的主表面上。
在第二有利的配置中,凹陷的深度的尺寸以这种方式形成,使得如果连接介质存在的话,功率半导体部件与连接介质一起的表面的高度等于基板的第一导体轨道的表面的高度,连接介质布置在所述功率半导体部件的主表面上。
在第三有利的配置中,凹陷的深度的尺寸以这种方式形成,使得如果连接介质存在的话,功率半导体部件与连接介质一起的表面的高度等于基板的第二导体轨道与布置在那里的连接介质一起的表面的高度,连接介质布置在所述功率半导体部件的主表面上。
可能优选的是,如果连接装置的弓形路线的高度最小为连接装置的厚度的10%,优选最小为连接装置的厚度的25%,特别优选最小为连接装置的厚度的40%。
在这种情况下,则同样优选的是,如果连接装置的弓形路线的高度最大为连接装置的厚度的200%,优选最大为连接装置的厚度的100%,特别优选最大为连接装置的厚度的60%。
对于功率半导体部件,特别是功率晶体管和功率二极管,根据其电压等级,以下弓形路线的高度值的优选范围是适用的:
·电压等级为600V至750V:连接装置的厚度的10%至60%;
·电压等级为1200V:连接装置的厚度的25%至100%;
·电压等级为1700V:连接装置的厚度的40%至150%;
·电压等级超过1700V:连接装置的厚度的至少40%。
不言而喻的是,除非本身或明确地排除在外,否则以单数提及的特征,特别是功率半导体部件以及相应的导体轨道,也可以复数地存在于根据本发明的功率电子开关装置中。
不言而喻的是,本发明的各种配置可以独立地实现或以任何期望的组合实现,以便实现改进。特别地,在不脱离本发明的范围的情况下,上文和下文提及和解释的特征不仅在示出的组合中是可用的,而且在其他组合中或单独地也是可用的。
附图说明
通过以下对图1至图4示意性图示的本发明的示例性实施例或其相应部分的描述,本发明的进一步解释、有利的细节和特征将变得显而易见。
图1以侧视图示出根据现有技术的功率电子开关装置。
图2以侧视图示出根据本发明的功率电子开关装置的第一配置。
图3以平面视图示出所述第一配置。
图4以侧视图示出根据本发明的功率电子开关装置的第二配置。
在下文中使用以下变量,其在附图中使用并且在每种情况下沿相对于基板2的法线N的方向确定:
·800–功率半导体部件5与位于其上的连接介质50,52,54一起的表面950与第一导体轨道22的表面220之间的距离;
·802–功率半导体部件5与位于其上的连接介质52,54一起的表面950和第二导体轨道24与位于其上的连接介质240一起的表面之间的距离;
·820–基板2的绝缘材料体20的厚度;
·822–基板2的第一导体轨道22的厚度;
·824–基板2的第二导体轨道24的厚度;
·828–第一导体轨道22的凹陷28的深度,功率半导体部件5布置在凹陷28中;
·830–连接装置3的厚度;
·832–连接装置3的弓形路线36的高度;其中,此处如果薄膜复合材料作为连接装置3存在,则考虑一个薄膜内的高度差;
·850–功率半导体部件5与位于两个主表面上的连接介质50、52、54一起的厚度;
·852–没有连接介质的功率半导体部件5的厚度;
·854–在功率半导体部件5的第一主表面上的连接介质50的厚度;
·856–在功率半导体部件5的第二主表面上的连接介质52,54的厚度;
·922–基板2的第一导体轨道22的表面220的高度(level);
·924–基板2的第二导体轨道24与布置在那里的连接介质240一起的表面的高度;
·950–功率半导体部件5与布置在那里的连接介质52,54一起的表面的高度。
具体实施方式
图1以侧视图示出根据现有技术的功率电子开关装置以及与理解本发明相关的变量(参见上文)。该功率电子开关装置1实施为基板2和布置在其上的第一导体轨道22和第二导体轨道24,该基板2具有绝缘材料体20,例如,此处是陶瓷体(例如氧化铝、氮化铝或氮化硅),第一导体轨道22和第二导体轨道24优选由铜或铝制成。在此实施为功率晶体管的功率半导体部件5布置在第一导体轨道22的表面220上并且与其导电连接。在此,功率半导体部件5与第一导体轨道22的表面220的连接通过连接介质50以材料结合的方式实现,连接介质50布置在第一导体轨道22的表面220和面对的功率半导体部件5的主表面之间,不限制通用性,在此所述连接介质实施为烧结连接介质,例如,在产生压力烧结连接的情况下烧结连接介质由烧结膏制成。
所述功率半导体部件5通过连接装置3与基板2的第二导体轨道24导电连接。所述连接装置3在功率半导体部件5和第二导体轨道24之间的部分中具有弓形路线36。凝胶状的绝缘材料4布置在体积区域732中,体积区域732在所述弓形路线36下方形成。
在此,连接装置3本身实施为薄膜复合材料,薄膜复合材料包括面对基板2并且因此还面对功率半导体部件5的第一导电薄膜30,在薄膜复合材料中跟随的并且因此基本上在相对于基板2的法线N的方向上的电绝缘薄膜32,以及在薄膜复合材料中进一步跟随的第二导电薄膜34。特别地,导电薄膜30,34可以本身是结构化的并且因此形成薄膜导体轨道。这是基于第一导电薄膜30的示例说明的。此外,薄膜复合材料可以具有镀通孔320,镀通孔320在第一导电薄膜30和第二导电薄膜34之间通过电绝缘薄膜32,如在功率半导体部件5的上方示出的。
在此,薄膜复合材料的第一导电薄膜30和第二导电薄膜34的厚度为250μm,并且薄膜复合材料的电绝缘薄膜32的厚度为80μm。
在每种情况下,在连接装置3(在此是薄膜复合材料的第一导电薄膜30的两个相互电绝缘的薄膜导体轨道)和功率半导体部件5(在此是其背离基板2的第二主表面)之间的导电连接实施为材料结合连接,相应地在此是与指定的连接介质52,54(在此是烧结连接介质)的烧结连接。
连接装置3和第二导体轨道24之间的导电连接在此同样实施为材料结合连接,但是实施为激光焊接连接。因此,在薄膜复合材料、更确切地是其第一导电薄膜30与基板2的第二导体轨道24之间没有布置连接介质。
图2以侧视图示出根据本发明的功率电子开关装置的第一配置,以及与理解本发明相关的变量。作为薄膜复合材料的连接装置3的配置以及功率半导体部件5的配置、以及薄膜复合材料3与功率半导体部件5以及第二导体轨道24之间的连接在原理上与关于图1描述的那些相同。
根据本发明的配置与根据图1的现有技术的不同在于,在此第一导体轨道22具有凹陷28,并且功率半导体部件5布置在所述凹陷28中。
在该第一配置中,凹陷28的深度828的尺寸以这种方式形成,使得功率半导体部件5与布置在所述功率半导体部件5的两个主表面上的连接介质50、52、54一起的表面的高度950等于基板2的第一导体轨道22的表面的高度922。相等的高度也应理解为包括最多达10%的相应值的偏差,特别是由生产决定的偏差。
功率电子开关装置的该第一配置的典型变量在此是:
·基板2的绝缘材料体20的厚度820为:250μm;
·基板2的第一导体轨道22的厚度822和第二导体轨道24的厚度824为:300μm;
·第一导体轨道22的凹陷28的深度828为:100μm,功率半导体部件5布置在凹陷28中;
·连接装置3的厚度830为:580μm;
·连接装置的弓形路线36的高度为:460μm;
·功率半导体部件5与在两个主表面上的连接介质50、52、54一起的厚度为:100μm;
·没有连接介质的功率半导体部件5的厚度852为:80μm;
·在功率半导体部件5的第一主表面上的连接介质50的厚度854为:20μm;
·在功率半导体部件5的第二主表面上的连接介质52,54的厚度856为:20μm。
连接装置3的弓形路线36的高度832在此是连接装置的厚度830的大约80%。因此,该连接装置适合于电压等级为1200V的功率半导体部件5。
借助于提及的配置,根据现有技术(关于图1提及的)的功率电子开关装置(具有使用DCB,AMB或相关技术的基板)的构造的优点与使用传统印刷电路板(PCB)(其中功率半导体部件布置在其层结构中)的优点组合。传统功率电子基板具有其高载流能力的优点并没有减少,因为在凹陷的下方仍保持了200μm的第一导体轨道的厚度,这对于需要的载流能力绝对是足够的。这种载流能力不能通过本领域常规的传统印刷电路板来获得,或者仅在相当大的花费下才能获得。此外,具有传统印刷电路板的这种构造不允许连接装置的弓形路线或其等效方案的实施。
图3以平面视图示出根据本发明的功率电子开关装置的所述第一配置。该图示再次示出具有第一导体轨道22和第二导体轨道24的绝缘材料体20。功率半导体部件5布置在第一导体轨道22的相应凹陷28中。将多个功率半导体部件布置在凹陷中也可能是有利的。功率半导体部件5在其背离基板2的主侧上具有两个连接介质52,54。第一连接介质52在此布置在功率半导体部件5的控制端子区域上,而第二连接介质54在此布置在功率半导体部件5的负载端子区域上。
图4以侧视图示出根据本发明的功率电子开关装置1的第二配置。该第二配置与第一配置的不同首先在于,在此作为薄膜复合材料存在的连接装置3与第二导体轨道24之间的连接利用连接介质240通过材料结合连接实施。不限制通用性,相应地连接介质240是烧结连接介质。
其次,在此凹陷28的深度828的尺寸以这种方式形成,使得功率半导体部件5与布置在所述功率半导体部件的主表面上的连接介质50、52、54一起的表面的高度950等于基板2的第二导体轨道24与布置在那里的连接介质240一起的表面的高度924。
Claims (20)
1.功率电子开关装置(1),其包括基板(2)、功率半导体部件(5)和连接装置(3),所述基板(2)具有绝缘材料体(20)和布置在其上的第一导体轨道(22)和第二导体轨道(24),所述功率半导体部件(5)导电地连接到第一导体轨道(22),所述连接装置(3)将所述功率半导体部件(5)连接到基板(2)的第二导体轨道(24)并且在功率半导体部件和第二导体轨道之间的部分中具有弓形路线(36),其特征在于:第一导体轨道(22)具有凹陷(28),凹陷(28)具有指定的深度,并且功率半导体部件(5)布置在所述凹陷(28)中。
2.根据权利要求1所述的开关装置,其特征在于:
连接装置(3)实施为结合连接。
3.根据权利要求2所述的开关装置,其特征在于:
所述结合连接是导线结合连接。
4.根据权利要求1所述的开关装置,其特征在于:
连接装置(3)施为薄膜复合材料。
5.根据权利要求4所述的开关装置,其特征在于:
所述薄膜复合材料包括面对基板(2)和功率半导体部件(5)的第一导电薄膜(30)、在薄膜复合材料中跟随的电绝缘薄膜(32)、以及在薄膜复合材料中进一步跟随的第二导电薄膜(34)。
6.根据权利要求4所述的开关装置,其特征在于:
薄膜复合材料的导电薄膜(30,34)的相应厚度在10μm至500μm之间,并且薄膜复合材料的电绝缘薄膜(32)的厚度在2μm至200μm之间。
7.根据权利要求6所述的开关装置,其特征在于:
薄膜复合材料的导电薄膜(30,34)的相应厚度在50μm至250μm之间,并且薄膜复合材料的电绝缘薄膜(32)的厚度在10μm至100μm之间。
8.根据前述权利要求1到7中任一项所述的开关装置,其特征在于:
在每种情况下,在连接装置(3)和第二导体轨道(24)之间的导电连接以及在连接装置(3)和功率半导体部件(5)之间的导电连接彼此独立地实施为力锁定连接或材料结合连接。
9.根据前述权利要求8所述的开关装置,其特征在于:
所述材料结合连接实施为钎焊连接或实施为焊接连接或实施为烧结连接或实施为粘合结合连接。
10.根据前述权利要求9所述的开关装置,其特征在于:
所述焊接连接实施为激光焊接连接。
11.根据权利要求8所述的开关装置,其特征在于:
材料结合连接包括连接介质(50、52、54、240),其具有所述连接介质的厚度(850、852)。
12.根据权利要求1到7中任一项所述的开关装置,其特征在于:
凹陷(28)的深度(828)的尺寸以这种方式形成,使得如果连接介质(50,52,54)存在的话,其至少是功率半导体部件(5)与连接介质(50,52,54)一起的厚度的一半,连接介质(50,52,54)布置在所述功率半导体部件的主表面上。
13.根据权利要求1到7中任一项所述的开关装置,其特征在于:
凹陷(28)的深度(828)的尺寸以这种方式形成,使得如果连接介质(50,52,54)存在的话,功率半导体部件(5)与连接介质(50,52,54)一起的表面的高度(950)等于基板(2)的第一导体轨道(22)的表面的高度(922),连接介质(50,52,54)布置在所述功率半导体部件的主表面上。
14.根据权利要求1到7中任一项所述的开关装置,其特征在于:
凹陷(28)的深度(828)的尺寸以这种方式形成,使得如果连接介质(50,52,54)存在的话,功率半导体部件(5)与连接介质(50,52,54)一起的表面的高度(950)等于基板(2)的第二导体轨道(24)与布置在那里的连接介质(240)一起的表面的高度(924),连接介质(50,52,54)布置在所述功率半导体部件的主表面上。
15.根据权利要求1到7中任一项所述的开关装置,其特征在于:
连接装置(3)的弓形路线(36)的高度最小为连接装置(3)的厚度(830)的10%。
16.根据权利要求15所述的开关装置,其特征在于:
连接装置(3)的弓形路线(36)的高度最小为连接装置(3)的厚度(830)的25%。
17.根据权利要求15所述的开关装置,其特征在于:
连接装置(3)的弓形路线(36)的高度最小为连接装置(3)的厚度(830)的40%。
18.根据权利要求1到7中任一项所述的开关装置,其特征在于:
连接装置(3)的弓形路线(36)的高度最大为连接装置(3)的厚度(830)的200%。
19.根据权利要求18所述的开关装置,其特征在于:
连接装置(3)的弓形路线(36)的高度最大为连接装置(3)的厚度(830)的100%。
20.根据权利要求18所述的开关装置,其特征在于:
连接装置(3)的弓形路线(36)的高度最大为连接装置(3)的厚度(830)的60%。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102019118421.5A DE102019118421B4 (de) | 2019-07-08 | 2019-07-08 | Leistungselektronische Schalteinrichtung mit einem Verbindungsmittel und mit einem Leistungshalbleiterbauelement |
DE102019118421.5 | 2019-07-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN112201642A true CN112201642A (zh) | 2021-01-08 |
Family
ID=74006043
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202010646235.3A Pending CN112201642A (zh) | 2019-07-08 | 2020-07-07 | 包括连接介质和功率半导体部件的功率电子开关装置 |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN112201642A (zh) |
DE (1) | DE102019118421B4 (zh) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102015120156B4 (de) * | 2015-11-20 | 2019-07-04 | Semikron Elektronik Gmbh & Co. Kg | Vorrichtung zur materialschlüssigen Verbindung von Verbindungspartnern eines Leistungselekronik-Bauteils und Verwendung einer solchen Vorrichtung |
EP3481166B1 (en) * | 2017-11-06 | 2021-08-18 | Molex, LLC | Circuit assembly and mounting unit |
DE102018110132B3 (de) * | 2018-04-26 | 2018-11-29 | Semikron Elektronik Gmbh & Co. Kg | Drucksinterverfahren bei dem Leistungshalbleiterbauelemente mit einem Substrat über eine Sinterverbindung miteinander verbunden werden |
-
2019
- 2019-07-08 DE DE102019118421.5A patent/DE102019118421B4/de active Active
-
2020
- 2020-07-07 CN CN202010646235.3A patent/CN112201642A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
DE102019118421B4 (de) | 2021-03-18 |
DE102019118421A1 (de) | 2021-01-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8981553B2 (en) | Power semiconductor module with integrated thick-film printed circuit board | |
KR101319208B1 (ko) | 전자 부품용 접속 소자 | |
US11646251B2 (en) | Semiconductor device | |
CN116964730A (zh) | 具有陶瓷电路载体、柔性电路板和温度传感器的功率模块 | |
KR20130120385A (ko) | 기판 및 적어도 하나의 전력반도체 부품용 기판의 제조방법 | |
US12087752B2 (en) | Semiconductor module | |
CN113257801B (zh) | 半导体装置及半导体装置的制造方法 | |
US10026670B1 (en) | Power module | |
CN116888732A (zh) | 功率模块、电气设备和用于制造功率模块的方法 | |
CN115117011A (zh) | 功率半导体模块和生产功率半导体模块的方法 | |
CN112309994B (zh) | 半导体模块装置 | |
JP2007053371A (ja) | ライン要素を備えたパワー半導体モジュール | |
US11282774B2 (en) | Power semiconductor module arrangement | |
US10129987B2 (en) | Circuit carrier and a method for producing a circuit carrier | |
CN109844939A (zh) | 功率模块 | |
CN112201642A (zh) | 包括连接介质和功率半导体部件的功率电子开关装置 | |
US12035477B2 (en) | Electronic module and method for producing an electronic module | |
CN102576705B (zh) | 电路装置及其制造方法 | |
JP6697547B2 (ja) | 追加的トラックを備えた半導体パワーデバイスおよび半導体パワーデバイスを製造する方法 | |
US6989590B2 (en) | Power semiconductor device with a control circuit board that includes filled through holes | |
CN112054013A (zh) | 功率电子开关装置及其生产方法 | |
KR20230042373A (ko) | 전자 회로 모듈 | |
CN110168709B (zh) | 具有用于连接半导体芯片的第一和第二连接元件的半导体模块及制造方法 | |
CN111799581B (zh) | 电子电路单元 | |
US20240291393A1 (en) | Commutation cell for an inverter |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |