CN112201186A

CN112201186A - Test component group

Info

Publication number: CN112201186A
Application number: CN202011079419.2A
Authority: CN
Inventors: 吴瑞习
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2020-10-10
Filing date: 2020-10-10
Publication date: 2021-01-08

Abstract

The application discloses a test element group. The test element group is used for carrying out electrical test on an array substrate, and comprises: the test fixture comprises a plurality of groups of probe sets, and each group of probe sets is used for electrically contacting with a plurality of test terminals arranged at intervals on an array substrate; and each static eliminating device is arranged between two adjacent test terminals and is used for eliminating static on the probe set.

Description

Test component group

Technical Field

The application relates to the technical field of array substrate detection, in particular to a test element group.

Background

An Array Tester (ATS) is equipment for detecting the comprehensive performance of a product after the completion of an Array process of a TFT-LCD, and the testing method is to simulate the working principle of the TFT-LCD, and perform power-on Test on an effective display Area (Active Area, AA Area) of a TFT substrate by utilizing a testing jig of the equipment on one side of an Array Test terminal (Array Test Pad) in a short-circuit bar mode.

In actual production, in an Array substrate Gate drive (Gate On Array, GOA) TFT-LCD product, when a Shorting bar testing (Shorting bar testing) process is performed, line burn is easily generated at a position where metal lines Cross (Cross) as shown in a in fig. 1, which causes Short circuit (Short) of metal lines of different layers, resulting in abnormal product quality, as shown in fig. 1, fig. 1 is a schematic diagram of Short circuit burn occurring in a metal routing in the prior art, where the metal routing includes a Gate test signal line, a source test signal line, and a drain test signal line, and the metal routing is respectively used for connection between each test terminal and gates, sources, and drains of a plurality of thin film transistors of the Array substrate, so as to facilitate the test terminals to test the thin film transistors.

Referring to fig. 2, fig. 2 is a schematic diagram illustrating an electrical test of a test terminal of a TFT substrate by using a test fixture in the prior art; as shown in fig. 2, generally, since static electricity remains on a plurality of probes (pins) 101 on a test fixture 100 of a device itself, such as a needle Head, when the probes 101 contact with the test terminals (Array test pads) 200, the static electricity enters the TFT substrate through the contact between the probes 101 and the test terminals 200, which may cause an insulating layer of the TFT substrate to be burned, as shown in fig. 1.

Therefore, in order to eliminate static electricity on the probes of the test fixture before the probes are brought into contact with the test terminals of the TFT substrate, it is necessary to provide a test element group.

Disclosure of Invention

The embodiment of the application provides a testing component group, and this testing component group is used for carrying out the electrical test to each test terminal of an array base plate, and this testing component group includes static-eliminating device, test fixture and test board, and is through two adjacent set up static-eliminating device between the test terminal, set up multiunit probe group on a test fixture, utilize test board and probe group electricity to be connected in order to acquire the signal of telecommunication of probe group, at the signal of telecommunication in-process that detects each test terminal in proper order, utilize static-eliminating device to eliminate the static on the probe group to effectively reduce and eliminate phenomena such as the circuit burn of array base plate is unusual.

The embodiment of the application provides a test component group for carry out electrical test to an array base plate, test component group includes: the test fixture comprises a plurality of groups of probe sets, and each group of probe sets is used for electrically contacting with a plurality of test terminals arranged at intervals on the array substrate; the test machine is electrically connected with the probe group and used for acquiring the electric signals on the probe group; and each static eliminating device is arranged between two adjacent test terminals and is used for eliminating static on the probe group.

In some embodiments, the test element group further includes a test machine electrically connected to the plurality of sets of probes for acquiring electrical signals on the probe sets.

In some embodiments, each of the probe sets includes a first probe and a second probe spaced apart from each other, and the first probe and the second probe of each of the probe sets are respectively configured to contact two ends of a test terminal.

In some embodiments, the testing element group further includes a testing machine electrically connected to each of the first probes for obtaining electrical signals thereon, and electrically connected to each of the second probes for obtaining electrical signals thereon.

In some embodiments, the testing machine includes a real-time electrical signal monitor for monitoring the magnitude of the electrical signals of the first probe and the second probe in real time.

In some embodiments, the real-time electrical signal detector includes a plurality of detection terminals, and the first probe and the second probe are electrically connected to the detection terminals through data signal lines, respectively.

In some embodiments, the static elimination device comprises an impedance element for blocking a path between two adjacent test terminals of the array substrate.

In some embodiments, the testing fixture has a first end and a second end, the testing machine is disposed on the first end, and the plurality of probe sets are uniformly spaced on the second end.

In some embodiments, the second end of the test fixture extends into a side channel formed by a plurality of test terminals of the array substrate.

In some embodiments, the static elimination device is detachably connected with the second end of the test fixture. The embodiment of the application provides test component group, test component group is used for carrying out the electrical test to an array base plate, test component group includes static-eliminating device, test fixture and test board, through set up between array base plate's the two adjacent test terminals static-eliminating device be provided with a plurality of probe groups on the test fixture, utilize test board with probe group carries out the electricity and connects, in order to acquire probe group's signal of telecommunication is detecting each test terminal's signal of telecommunication in proper order in-process, utilizes static-eliminating device eliminates static on the probe group, thereby effectively reduces and eliminates array base plate's phenomenon such as circuit burn is unusual.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

FIG. 1 is a schematic diagram illustrating a metal trace being burned due to short circuit in the prior art;

FIG. 2 is a schematic diagram illustrating an electrical test of a test terminal of a TFT substrate by a test fixture in the prior art;

FIG. 3 is a schematic view of the assembly of the testing element set and the testing terminals of the array substrate according to the present invention;

FIG. 4 is a diagram illustrating an electrical test performed on an array substrate by a test element set.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.

Specifically, please refer to fig. 3 and 4, fig. 3 is an assembly diagram of the testing element group and the testing terminals of the array substrate according to the present application; FIG. 4 is a diagram illustrating an electrical test performed on an array substrate by a test element set. In the present application, a test element group and a detection method thereof are provided. In the present embodiment, as shown in fig. 3 and 4, a testing element group 100 is provided for performing an electrical test on an array substrate 200, where the array substrate 200 includes a plurality of testing terminals 201 arranged at intervals. In the embodiment of the present application, the array substrate 200 has a display Area 210(AA, Active Area) and a peripheral Area 220 surrounding the display Area 210, and in the display Area 210, the array substrate 200 includes a plurality of Thin Film Transistors (TFTs) (not shown); in the peripheral area 220, the array substrate 200 includes a plurality of test terminals 201 and a plurality of test signal lines (not shown) arranged at intervals, and the test terminals 201 are electrically connected to the plurality of thin film transistors through the test signal lines. In this embodiment, the array substrate 200 includes the testing element group 100, the testing element group 100 is used for performing an electrical test on the array substrate 200, and the testing element group 100 is used for performing an electrical test on other array substrates.

In the present application, as shown in fig. 3, the test element group 100 includes: a testing tool 110, a testing machine 120 and a plurality of static elimination devices 130. The testing fixture 110 includes a plurality of probe sets 111, each probe set 111 is used for electrically contacting with one of the testing terminals 201; the testing machine 120 is electrically connected with the probe group 111 and is used for acquiring an electrical signal on the probe group 111; each of the static elimination devices 130 is disposed between two adjacent test terminals 201, and the static elimination device 130 is used for eliminating static electricity possibly existing on the probe set 111.

In this embodiment, as shown in fig. 3, the test terminals 201 include a first test terminal 2011, a second test terminal 2012 and a third test terminal 2013, wherein the first test terminal 2011, the second test terminal 2012 and the third test terminal 2013 are sequentially and uniformly arranged at intervals, the first test terminal 2011, the second test terminal 2012 and the third test terminal 2013 are arranged in a row to extend to form a side channel, and two adjacent test terminals 201 form a receiving slot at intervals.

Referring to fig. 3, in the present embodiment, the test fixture 110 has a first end 11 and a second end 12, the probe assembly 111 is disposed on the second end 12 of the test fixture 110, the second end 12 is used to extend into the side channel formed by the plurality of test terminals 201, so as to facilitate the insertion or extraction of the second end 12 of the test fixture 110 and the probe assembly 111 into or out of the side channel, and the probe assembly 2 is used to contact with two ends of the test terminals 201.

As shown in fig. 3, a plurality of sets of probe sets 111 are respectively disposed on the second end 12 of the testing fixture 110 at regular intervals, and each set of probe sets 111 corresponds to one of the testing terminals 201. In a preferred embodiment, as shown in FIG. 3, each set 111 of probes comprises a first probe 21 and a second probe 22, and the first probe 21 and the second probe 22 are not connected to each other. In the embodiment of the present application, the first probe 21 and the second probe 22 of one probe set 111 are respectively used for testing the resistance of one test terminal 201.

In addition, in order to simplify the model of the present invention and ensure the reliability of the present invention, the types and sizes of the probes of the probe sets 111 are all set to be the same, that is, the test fixture 110 includes a plurality of probe pins 20, that is, the first probes 21 and the second probes 22 respectively have the probe pins 20.

It should be noted that, when the test fixture 110 is used to test a plurality of the test terminals 201 at present, the plurality of probe pins 20 in the test fixture 110 are arranged in a certain manner and the positions thereof are fixed, so that the arrangement manner of the probe pins 20 on the test fixture 110 needs to be consistent with the arrangement manner of the plurality of the test terminals 201, so as to perform the corresponding test.

In other embodiments, the test terminals 201 include, but are not limited to, the first test terminal 2011, the second test terminal 2012, and the third test terminal 2013, the test terminals 201 may further include idle test terminals, and the number of the test terminals 201 may be selected and set according to test requirements of a plurality of thin film transistors of the array substrate. In other embodiments, the arrangement of the plurality of test terminals 201 is not limited to a row arrangement, but the plurality of test terminals 201 may be a row arrangement or a multi-column arrangement, or may be arranged according to the actual requirement of each test signal line of the array substrate 200, for example, the plurality of test terminals 201 may be arranged at four-point positions, and the plurality of test terminals 201 may be arranged at two-row positions, which is not specifically described herein.

In this application, it is a plurality of test terminal 201 is respectively through all kinds test signal line and single or a plurality of thin film transistor's grid, source electrode and drain electrode carry out the electricity and connect, test signal line includes grid test signal line, source electrode test signal line and drain electrode test signal line, test signal line is the metal signal line.

In this embodiment, one of the test terminals 201 serves as a gate test terminal or a gate test interface, and the gate test terminal or the gate test interface is electrically connected to the gate of the TFT through the gate test signal line; the gates of at least two of the TFTs are electrically connected to the same test terminal 201 to save the number of the test terminals 201. The test terminal 201 may serve as a source test terminal or a source test interface, and the source test terminal or the source test interface is electrically connected to the source of the TFT through the source test signal line; and the test terminal 201 may be a drain test terminal or a drain test interface electrically connected to the drain of the TFT through the drain test signal line.

In this embodiment, as shown in fig. 3, the minimum pitch of two adjacent probe sets 111 is greater than the pitch between two adjacent test terminals 201, and the maximum pitch of two adjacent probe sets 111 is less than the sum of the pitch between two adjacent test terminals 201 and the extension length L of two test terminals 201, so that the first probes 21 and the second probes 22 contact the test terminals 201, wherein the extension length direction of the test terminals 201 is the same as the arrangement direction of the test terminals 201. And the distance between the first probe 21 and the second probe 22 of the same probe group 111 is smaller than the extension length L of the test terminal 201, and the ends of the first probe 21 and the second probe 22 are respectively used for contacting with two ends of the same test terminal 201.

Referring to fig. 3, the testing machine 120 is electrically connected to each of the first probes 21 and is used for acquiring electrical signals on the first probes 21, and the testing machine 120 is electrically connected to each of the second probes 22 and is used for acquiring electrical signals on the second probes 22.

In this embodiment, the testing machine 120 includes a real-time electrical signal detector for receiving and acquiring the electrical signals of the first probe 21 and the second probe 22. In this embodiment, the real-time electrical signal detector includes a plurality of detecting terminals 31, one of the detecting terminals 31 is electrically connected to the probe pin 20 of the first probe 21 through one of the signal lines 5, and the other detecting terminal 31 is electrically connected to the probe pin 20 of the second probe 22 through one of the signal lines 5. In this embodiment, the detecting terminal 31 of the real-time electrical signal detector is disposed on the first end 11 of the testing fixture 110, and the first end 11 of the testing fixture 110 is always located outside the side channel of the testing terminal 201.

In this application, the real-time detecting instrument of electric signal is used for real-time dynamic monitoring every group probe group 111 the electric signal change condition of probe pin 20, the real-time detecting instrument of electric signal is used for detecting whether test fixture 110 the probe pin 20 is last to have static, is particularly useful for probe group 111 the probe pin 20 with before the test terminal 201 contact to probe pin 20 carries out electrostatic detection.

Referring to fig. 3, one of the static eliminating devices 130 is disposed corresponding to one of the testing terminals 100, and in the process of inserting the testing fixture 1 into the side channel, the static eliminating device 130 is configured to eliminate static electricity on the probe set 111 before the probe set 111 contacts the testing terminal 201, and when the testing fixture 110 is completely inserted into the side channel, each static eliminating device 130 is received in the receiving slots formed at intervals between two adjacent testing terminals 201. In this embodiment, the static electricity eliminating apparatus 130 is configured to emit an anti-static ion wind to blow the first probe 21 and the second probe 22, so as to effectively reduce the short circuit and burn phenomenon of the test signal line between the test terminal 201 and the TFT caused by static electricity carried on the first probe 21 and the second probe 22.

It should be noted that, in some preferred embodiments, the static elimination apparatus 130 is detachably connected to the second end 12 of the test fixture 110. In other preferred embodiments, the static eliminating device 130 may be separately disposed between two adjacent test terminals 201, that is, the static eliminating device 130 is disposed independently of the test fixture 110, each static eliminating device 130 is always accommodated in the accommodating slot formed by two adjacent test terminals 201 at an interval, the static eliminating device 130 is not in contact with the test fixture 110, and the static eliminating device 130 can achieve the purpose of eliminating the static electricity of the test terminals 201. In addition, the static electricity eliminating apparatus 130 includes, but is not limited to, the above connection manner.

In some embodiments, the static elimination apparatus 130 further includes an impedance element for blocking a path between two adjacent test terminals 201 of the array substrate 200.

The embodiment of the present application provides a testing component group, which has an advantage in that the testing component group 100 is suitable for performing an electrical test on a plurality of testing terminals 201 arranged at intervals of an array substrate 200, and the testing component group 100 includes a testing fixture 110, a testing machine 120 and an electrostatic elimination device 130. The testing machine 120 is disposed on the testing fixture 110, the testing fixture 110 includes a plurality of probe sets 111, each probe set 111 includes a first probe 21 and a second probe 22, the first probe 21 and the second probe 22 of each probe set 111 are respectively configured to contact two ends of a testing terminal 201, and the first probe 21 and the second probe 22 are respectively configured to obtain a resistance of the testing terminal 201; in addition, by arranging the static elimination device 130 between two adjacent test terminals 201, in the process of sequentially detecting the electric signals of each test terminal 201, the static elimination device 130 is used for eliminating the static electricity on the probe group 111, so that the phenomena of abnormal line burn and the like of the array substrate 200 are effectively reduced and eliminated; and the first probe 21 and the second probe 22 are electrically connected to the testing machine 120, i.e. the real-time electrical signal detector, through the signal line 5, respectively, and the real-time electrical signal detector is configured to detect the magnitude of the electrical signal loaded by the first probe 21 and the second probe 22 on each testing terminal 201 in real time, so as to dynamically monitor the change of the electrical signal of each probe group 111 of the testing fixture 201 in real time, so as to ensure that the static electricity on the probe group 111 is eliminated by the static electricity eliminating device 130 before the probe group 111 on the testing fixture 201 contacts with the testing terminal 201.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The above detailed description is given to a testing component set provided in the embodiments of the present application, and specific examples are applied in the present application to explain the principle and the implementation of the present application, and the description of the above embodiments is only used to help understanding the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A testing component set for performing an electrical test on an array substrate, the testing component set comprising:

the test fixture comprises a plurality of groups of probe sets, and each group of probe sets is used for electrically contacting with a plurality of test terminals arranged at intervals on the array substrate;

and each static eliminating device is arranged between two adjacent test terminals and is used for eliminating static on the probe group.

2. The set of test elements of claim 1, further comprising a test machine electrically connected to the plurality of sets of probes for obtaining electrical signals on the sets of probes.

3. The set of test elements of claim 1, wherein each of the probe sets includes a first probe and a second probe spaced apart from each other, and the first probe and the second probe of each probe set are respectively configured to contact two ends of a test terminal.

4. The set of test elements of claim 3, further comprising a test stage electrically connected to each of the first probes for obtaining electrical signals thereon, and electrically connected to each of the second probes for obtaining electrical signals thereon.

5. The testing component set as claimed in claim 4, wherein the testing machine comprises a real-time monitor for monitoring the magnitude of the electrical signal of the first probe and the second probe.

6. The testing component set according to claim 5, wherein the real-time electrical signal detector comprises a plurality of detection terminals, and the first probe and the second probe are electrically connected to the detection terminals through data signal lines, respectively.

7. The set of test elements of claim 1, wherein the static elimination apparatus comprises an impedance element for blocking a path between two adjacent test terminals of the array substrate.

8. The testing device set as claimed in claim 1, wherein the testing fixture has a first end and a second end, the testing platform is disposed on the first end, and the plurality of probe sets are disposed on the second end at regular intervals.

9. The set of test elements of claim 8, wherein the second end of the test fixture extends into a side channel formed by the plurality of test terminals of the array substrate.

10. The set of test elements of claim 9, wherein the static elimination device is detachably connected to the second end of the test fixture.