CN112185839B - Passivation layer test structure - Google Patents
Passivation layer test structure Download PDFInfo
- Publication number
- CN112185839B CN112185839B CN202011177837.5A CN202011177837A CN112185839B CN 112185839 B CN112185839 B CN 112185839B CN 202011177837 A CN202011177837 A CN 202011177837A CN 112185839 B CN112185839 B CN 112185839B
- Authority
- CN
- China
- Prior art keywords
- passivation layer
- test structure
- test
- layer
- passivation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Abstract
The invention provides a passivation layer test structure. The passivation layer test structure includes: the structure layer comprises a plurality of conductive wires, and the conductive wires comprise at least one step-type structure; and passivation layers are formed on the surfaces of the substrate and the structural layer. According to the passivation layer test result provided by the invention, the stepped passivation layer test structure is provided, so that whether defects exist in a special position of the passivation layer, particularly in a corner area of the passivation layer is effectively detected, and the integrity of the passivation layer in a semiconductor device is checked. Compared with the existing passivation layer test structure, the test result of the passivation layer integrity test by adopting the passivation layer test structure provided by the invention has higher reliability.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a passivation layer test structure.
Background
Passivation of the chip surface has become one of the essential process steps for high performance and high reliability integrated circuits. The passivation layer is mainly used for electrically isolating the semiconductor devices and the wires from each other and isolating the semiconductor devices from the surrounding atmosphere, so as to enhance the blocking capability of the semiconductor devices against foreign ion contamination, protect the interconnections inside the semiconductor devices, and prevent the semiconductor devices from mechanical damage and chemical damage.
The kind and structure of the passivation layer have a great influence on the stress formed inside the interconnect line and the speed of the stress release. In the preparation process of an integrated circuit, the processes of deposition, polishing, photoetching and the like are accompanied by the change of temperature, and the internal stress of the passivation layer is changed in the process of the change of temperature, so that defects such as pinholes, cracks, falling off and the like are formed. The occurrence of such defects may cause deformation inside the chip and short or open circuit of the interconnection wires, thereby causing failure of the semiconductor device. In order to avoid this, it is necessary to perform integrity testing of the passivation layer on the semiconductor device to ensure that the semiconductor device can be used normally.
In order to check whether the passivation layer of the semiconductor device has the defect, the integrity test of the passivation layer is generally performed by using the passivation layer of an S-type (i.e., the structure shown in fig. 1), an interdigital type (i.e., the structure shown in fig. 2), or a ring type structure in the prior art. However, the S-shaped, interdigitated, or ring-shaped passivation layer test structure cannot accurately measure the integrity of the passivation layer having a specific structure (e.g., corner region) in the conventional process, and thus a new passivation layer test structure is required to better detect the integrity of the passivation layer.
Disclosure of Invention
The invention aims to provide a passivation layer test structure, which can effectively detect whether a special position of a passivation layer, particularly a corner region of the passivation layer has a defect or not by providing a step-type passivation layer test structure, thereby checking the integrity of the passivation layer in a semiconductor device.
In order to achieve the above object, the present invention provides a passivation layer test structure for testing integrity of a passivation layer, the passivation layer test structure comprising:
the structure layer comprises a plurality of conductive wires, and the conductive wires comprise at least one step-type structure; and passivation layers are formed on the surfaces of the substrate and the structural layer.
Optionally, the conductive wire includes a plurality of step structures arranged repeatedly in succession or a plurality of step structures arranged in a mirror image.
Optionally, the stepped structure includes a first bottom edge and a second bottom edge connected to each other, and the length L of the first bottom edge 1 Is greater than the length L of the second bottom edge 2 。
Optionally, the length L of the first base edge 1 And minimum design rule X 1 Is in a relationship of L 1 ≥5X 1 。
Optionally, the length L of the second base edge 2 And minimum design rule X 2 Is in the relationship of X 2 ≤L 2 ≤3X 2 。
Optionally, the included angle between the first bottom edge and the second bottom edge is 70-110 °.
Optionally, the number of the conductive wires is N, N is greater than or equal to 3 and less than or equal to 8, and the conductive wires are parallel to each other.
Optionally, the integrity test of the passivation layer is performed on the passivation layer test structure through an electrical test or a chemical test.
Optionally, the step of testing the electrical property includes: and forming a conductive material layer on the surface of the passivation layer, and judging whether the passivation layer is complete or not by detecting the resistance between the structural layer and the conductive material layer.
Optionally, in the chemical test, the passivation layer test structure is etched by using a chemical solution, and whether the passivation layer is complete or not is judged by observing the etched appearance of the passivation layer test structure.
In summary, the present invention provides a passivation layer testing structure for testing the integrity of a passivation layer. The passivation layer test structure includes: the structure layer comprises a plurality of conductive wires, and the conductive wires comprise at least one step-type structure; and passivation layers are formed on the surfaces of the substrate and the structural layer. According to the passivation layer test result provided by the invention, the stepped passivation layer test structure is provided, so that whether defects exist in a special position of the passivation layer, particularly in a corner area of the passivation layer is effectively detected, and the integrity of the passivation layer in a semiconductor device is checked. Compared with the existing passivation layer test structure, the test result of the passivation layer integrity test by adopting the passivation layer test structure provided by the invention has higher reliability.
Drawings
FIG. 1 is a schematic diagram of a defect structure of an S-type passivation layer test structure after chemical testing in the prior art;
FIG. 2 is a schematic diagram of a defect structure after a chemical test is performed on an interdigital passivation layer test structure in the prior art;
FIG. 3 is a top view of a passivation layer test structure according to an embodiment of the invention;
FIG. 4 is a cross-sectional view of the passivation layer test structure depicted in FIG. 3 along the OO' axis;
FIG. 5 is an enlarged view of a step-type structure in the passivation layer test structure illustrated in FIG. 3;
FIG. 6 is a schematic structural diagram of another passivation layer test structure according to an embodiment of the present invention;
FIG. 7 is a schematic view of a defect structure after chemical testing of the passivation layer test structure shown in FIG. 3;
wherein the reference numbers are as follows:
100-a substrate; 200-structural layer; 210. 210' -a conductive line; 211. 211' -a stepped structure;
300-passivation layer.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is provided for the purpose of facilitating and clearly illustrating embodiments of the present invention.
Fig. 3 is a top view of a passivation layer test structure provided in the present embodiment, and fig. 4 is a cross-sectional view of the passivation layer test structure shown in fig. 3 along an OO' axis. As can be seen from fig. 3 and 4, the passivation layer test structure of the present embodiment includes a substrate 100, a structural layer 200 is formed on at least a portion of a surface of the substrate 100, the structural layer 200 includes a plurality of conductive lines 210, and the conductive lines 210 include at least one step-type structure 211; a passivation layer 300 is formed on the surfaces of the substrate 100 and the structural layer 200.
The passivation layer test structure provided in this embodiment is described in detail below with reference to fig. 3 to 7.
Referring first to fig. 3, the conductive lines 210 include four conductive lines a, B, C, and D, and the conductive lines a, B, C, and D are parallel to each other. In other embodiments of the present invention, the number of the conductive wires 210 may be plural, which is not limited in the present invention, and it is preferable that the number of the conductive wires 210 is between 3 and 8 in consideration of the test cost and the test accuracy. Fig. 5 is an enlarged view of a step type structure 211 in the passivation layer test structure illustrated in fig. 3. Referring to fig. 5, the stepped structure 211 includes a first bottom edge and a second bottom edge connected to each other, and a length L of the first bottom edge 1 Is greater than the length L of the second bottom edge 2 . Specifically, the length L of the first base edge 1 And minimum design rule X 1 Is in a relationship of L 1 ≥5X 1 . The length L of the second bottom edge 2 And minimum design rule X 2 Has a relationship of X 2 ≤L 2 ≤3X 2 . In this embodiment, the minimum design rule X 1 And X 2 All are the minimum length units in the passivation layer test structure, and the minimum design rule X 1 And X 2 Are equal. In other embodiments of the invention, the minimum design rule X 1 And X 2 May not be equal, and the invention is not limited in this regard. In this embodiment, the included angle between the first base line and the second base line is 90 °, and in other embodiments of the present invention, the included angle between the first base line and the second base line comprises 70 ° to 110 °.
Referring to fig. 3 and 6, a plurality of step-shaped structures 211 may be arranged on the conductive line in a mirror image manner or a plurality of step-shaped structures 211' may be arranged in a continuous and repeated manner. In this embodiment, the structural layer 200 is made of a conductive material, including aluminum, copper or gold, and the structural layer 200 may also be made of an alloy or other conductive materials, which is not limited in the present invention. Optionally, a functional region or other regions of the semiconductor device may be further included between the substrate 100 and the structural layer 200, which is common knowledge of those skilled in the art and is not described herein.
The passivation layer test structure provided by the embodiment is used for testing the integrity of the passivation layer in the semiconductor device, and the integrity test of the passivation layer comprises an electrical test or a chemical test. It should be noted that there are various methods for testing the integrity of the passivation layer in the semiconductor device, and in other embodiments of the present invention, other passivation layer integrity test methods may be used to perform integrity test on the passivation layer test structure provided by the present invention.
The electrical property testing step comprises: a conductive material layer (not shown in the drawings) is formed on the surface of the passivation layer 300, and whether the passivation layer 300 is complete or not is determined by detecting the resistance between the structural layer 200 and the conductive material layer. In this embodiment, the conductive material layer is formed on the surface of the passivation layer 300 by a deposition process. When the passivation layer 300 has defects such as pinholes, cracks, and the like, the defects expose a portion of the structural layer 200, and therefore, in the process of depositing and forming the conductive material layer, the conductive material layer is deposited on the surface of the structural layer 200 where the defects are exposed, resulting in the conductive material layer being in communication with the structural layer 200, and the resistance between the conductive material layer and the structural layer 200 is very low. When the passivation layer 300 is not defective, the conductive material layer and the structural layer 200 are separated by the passivation layer 300, and the resistance between the conductive material layer and the structural layer 200 is very high. Therefore, it is only necessary to measure the resistance between the structural layer 200 and the conductive material layer to determine whether the passivation layer 300 is complete. It should be noted that the specific method for electrical testing and the specific external circuit are both in the prior art, and the present invention will not be described in detail.
The chemical test uses a chemical solution to corrode the passivation layer test structure, and whether the passivation layer 300 is complete or not is judged by observing the corroded appearance of the passivation layer test structure. Specifically, since the size of a part of defects in the passivation layer 300 is too small to be directly observed, the passivation layer test structure needs to be processed by using a chemical solution. Firstly, immersing the passivation layer test structure into the chemical solution, wherein the chemical solution enters the structural layer 200 through the defects in the passivation layer 300, and the structural layer 200 forms corrosion holes under the corrosion of the chemical solution; and then, observing the passivation layer test structure by using an optical microscope, wherein the corrosion holes are black under the optical microscope, and the passivation layer 300 is in a transparent state under the optical microscope, so that whether the passivation layer 300 is complete or not can be judged by observing whether the corrosion holes appear in the passivation layer test structure or not. Alternatively, the chemical solution may be a potassium hydroxide (KOH) solution; phosphorous acid (H) 3 PO 3 ) Nitric acid (HNO) 3 ) And acetaldehyde (CH) 3 CHO); ammonium fluoride (NH) 4 F) And acetaldehyde (CH) 3 CHO); ammonium monohydrate (NH) 4 OH), hydrogen peroxide (H) 2 O 2 ) And Ultra Pure Water (UPW). In other embodiments of the present invention, the chemical solution may be other solutions having a corrosive effect, and the present invention is not limited thereto.
In order to verify the integrity test effect of the passivation layer test structure provided by this embodiment, a chemical test is performed on the passivation layer test structure provided by this embodiment. Fig. 7 is a schematic view of a defect structure of the passivation layer test structure after chemical testing. Referring to fig. 7, in the passivation layer test structure provided in this embodiment, defects (i.e., regions indicated by circles in fig. 7) are prone to occur on the inner sides of the corners of the two outermost conductive lines of the structure layer. Similarly, the S-type passivation layer test structure and the interdigital passivation layer test structure are chemically tested under the same test conditions, so as to obtain a defect structure schematic diagram of the S-type passivation layer test structure (i.e., fig. 1) and a defect structure schematic diagram of the interdigital passivation layer test structure (i.e., fig. 2). As can be seen by comparing fig. 1, 2 and 7, no significant defect is detected at a specific position of the passivation layer (e.g., a corner region of the passivation layer) in the S-type passivation layer test structure and the interdigitated passivation layer test structure; in the stepped passivation layer test structure provided in this embodiment, a distinct corrosion hole can be detected at a specific position of the passivation layer (e.g., a corner region of the passivation layer, i.e., a region indicated by a circle in fig. 7), which indicates that a defect exists at the specific position of the passivation layer (i.e., the corner region of the passivation layer). Compared with the S-type passivation layer test structure and the interdigital passivation layer test structure, the passivation layer test structure provided by the embodiment can effectively detect whether defects occur at a special position of the passivation layer in the semiconductor device, especially in a corner region of the passivation layer.
In summary, the present invention provides a passivation layer testing structure for testing the integrity of a passivation layer. The passivation layer test structure includes: the structure layer comprises a plurality of conductive wires, and the conductive wires comprise at least one step-type structure; and passivation layers are formed on the surfaces of the substrate and the structural layer. According to the passivation layer test result provided by the invention, the stepped passivation layer test structure is provided, so that whether defects exist in a special position of the passivation layer, particularly in a corner area of the passivation layer is effectively detected, and the integrity of the passivation layer in a semiconductor device is checked. Compared with the existing passivation layer test structure, the test result of the passivation layer integrity test by adopting the passivation layer test structure provided by the invention has higher reliability.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (5)
1. A passivation layer test structure for testing the integrity of a passivation layer, comprising:
the structure layer comprises a plurality of conductive wires, the number of the conductive wires is N, N is not less than 3 and not more than 8, the conductive wires are parallel to each other and comprise a plurality of step structures which are continuously and repeatedly arranged or a plurality of step structures which are arranged in a mirror image mode, the step structures comprise a first bottom edge and a second bottom edge which are connected, and the length L of the first bottom edge is 1 Is greater than the length L of the second bottom edge 2 Length L of said first base 1 And minimum design rule X 1 Has a relationship of L 1 ≥5X 1 Length L of said second base 2 And minimum design rule X 2 Has a relationship of X 2 ≤L 2 ≤3X 2 The minimum design rule X 1 And X 2 All are the minimum length units in the passivation layer test structure; and passivation layers are formed on the surfaces of the substrate and the structural layer.
2. The passivation layer test structure of claim 1, wherein the first base edge and the second base edge are angled at an angle of 70 ° -110 °.
3. The passivation layer test structure of claim 1, wherein the passivation layer test structure is subjected to an integrity test of the passivation layer by an electrical test or a chemical test.
4. The passivation layer test structure of claim 3, wherein the step of electrically testing comprises: and forming a conductive material layer on the surface of the passivation layer, and judging whether the passivation layer is complete or not by detecting the resistance between the structural layer and the conductive material layer.
5. The passivation layer test structure of claim 3, wherein the chemical test uses a chemical solution to etch the passivation layer test structure, and the integrity of the passivation layer is determined by observing the etched topography of the passivation layer test structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011177837.5A CN112185839B (en) | 2020-10-27 | 2020-10-27 | Passivation layer test structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011177837.5A CN112185839B (en) | 2020-10-27 | 2020-10-27 | Passivation layer test structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112185839A CN112185839A (en) | 2021-01-05 |
| CN112185839B true CN112185839B (en) | 2022-11-18 |
Family
ID=73917475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011177837.5A Active CN112185839B (en) | 2020-10-27 | 2020-10-27 | Passivation layer test structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112185839B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004119460A (en) * | 2002-09-24 | 2004-04-15 | Denso Corp | Semiconductor device |
| CN1953173A (en) * | 2005-10-19 | 2007-04-25 | 国际商业机器公司 | Wiring test structures for determining open and short circuits in semiconductor devices and forming method of the same |
| CN101896827A (en) * | 2007-12-17 | 2010-11-24 | Nxp股份有限公司 | Embedded structure for passivation integrity testing |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5946042A (en) * | 1982-09-09 | 1984-03-15 | Mitsubishi Electric Corp | Observing method for pin hole, crack and coverage of semiconductor device |
| CN107481976B (en) * | 2016-06-08 | 2019-12-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN111354783B (en) * | 2018-12-21 | 2024-02-20 | 苏州捷芯威半导体有限公司 | Semiconductor device and preparation method thereof |
| CN111341683A (en) * | 2020-03-03 | 2020-06-26 | 胜科纳米（苏州）有限公司 | Method for detecting pinhole defect on passivation layer of semiconductor wafer |
| CN111599707A (en) * | 2020-05-27 | 2020-08-28 | 广州粤芯半导体技术有限公司 | Method for detecting micro-cracks of passivation layer |
-
2020
- 2020-10-27 CN CN202011177837.5A patent/CN112185839B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004119460A (en) * | 2002-09-24 | 2004-04-15 | Denso Corp | Semiconductor device |
| CN1953173A (en) * | 2005-10-19 | 2007-04-25 | 国际商业机器公司 | Wiring test structures for determining open and short circuits in semiconductor devices and forming method of the same |
| CN101896827A (en) * | 2007-12-17 | 2010-11-24 | Nxp股份有限公司 | Embedded structure for passivation integrity testing |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112185839A (en) | 2021-01-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3910406B2 (en) | Inspection method of semiconductor device | |
| US20160300800A1 (en) | Integrated Circuit with Die Edge Assurance Structure | |
| US20030197289A1 (en) | Design of interconnection pads with separated probing and wire bonding regions | |
| JP4592634B2 (en) | Semiconductor device | |
| CN112185839B (en) | Passivation layer test structure | |
| JP2006140276A (en) | Semiconductor wafer and semiconductor device using the same and chip size package, and semiconductor wafer manufacturing method and semiconductor wafer testing method | |
| US6741940B2 (en) | Computer-implemented method of defect analysis | |
| JP5244898B2 (en) | Semiconductor integrated circuit device | |
| US8106476B2 (en) | Semiconductor die with fuse window and a monitoring window over a structure which indicates fuse integrity | |
| US6623995B1 (en) | Optimized monitor method for a metal patterning process | |
| EP0345924A2 (en) | Testing IC devices | |
| CN201281719Y (en) | Probe structure and test board with the same | |
| US20070134598A1 (en) | Manufacturing method of semiconductor device, and wafer and manufacturing method thereof | |
| US20110140104A1 (en) | Embedded structure for passivation integrity testing | |
| JP2007242862A (en) | Inspection substrate and inspection method of defects of transfer pattern | |
| JP2003051521A (en) | Connection hole monitor and semiconductor device | |
| CN117637505A (en) | Crack defect detection method and detection system | |
| JP3070543B2 (en) | Method for manufacturing semiconductor device | |
| JP4087289B2 (en) | Semiconductor device and inspection method thereof | |
| KR100520509B1 (en) | A equipment for monitoring electrical test of dielectric layer using guardring pattern | |
| JPS6057225B2 (en) | Testing method for semiconductor devices | |
| CN113097088A (en) | Method for detecting pin hole defects of chip | |
| KR100403319B1 (en) | Method for forming a test pattern of semiconductor device | |
| JP4179004B2 (en) | Semiconductor sensor device | |
| CN115547980A (en) | Multilayer interconnection structure and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |