CN113097088A - Method for detecting pin hole defects of chip - Google Patents
Method for detecting pin hole defects of chip Download PDFInfo
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- CN113097088A CN113097088A CN202110336501.7A CN202110336501A CN113097088A CN 113097088 A CN113097088 A CN 113097088A CN 202110336501 A CN202110336501 A CN 202110336501A CN 113097088 A CN113097088 A CN 113097088A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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Abstract
The embodiment of the invention discloses a method for detecting pin hole defects of a chip. The method comprises the steps of soaking a chip to be detected in a metal corrosive liquid for detection; wherein the chip comprises a metal layer and a passivation layer; and if the abnormal shape of the corrosion discoloration does not exist, soaking the detected chip in a buffering oxidation etching agent for detection. The technical scheme provided by the embodiment of the invention solves the problem that the pinhole defect which does not penetrate from the passivation layer to the metal layer below the passivation layer cannot be conveniently detected by the conventional pinhole defect detection method.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a method for detecting pin hole defects of a chip.
Background
In the process of manufacturing a chip, temperature changes occur such as deposition, polishing, photoetching and the like, the side wall of a metal bump on the chip and a Passivation layer on the surface of the chip are mutually extruded, so that internal stress changes, and the Passivation layer has defects such as pinholes, cracks or falling off, which cause deformation inside the chip and short circuit or open circuit of an interconnection wire, and cause device failure.
The problem that the pinhole defect of a metal layer which does not penetrate from a passivation layer to the bottom cannot be conveniently detected by the conventional pinhole defect detection method becomes an urgent problem to be solved in the industry.
Disclosure of Invention
The embodiment of the invention provides a method for detecting a pinhole defect of a chip, which aims to solve the problem that the existing method for detecting the pinhole defect cannot conveniently detect the pinhole defect which does not penetrate from a passivation layer to a metal layer below the passivation layer.
In order to realize the technical problem, the invention adopts the following technical scheme:
the embodiment of the invention provides a method for detecting pin hole defects of a chip, which comprises the following steps:
soaking the detected chip in a metal corrosive liquid for detection; wherein the chip comprises a metal layer and a passivation layer;
and if the abnormal shape of the corrosion discoloration does not exist, soaking the detected chip in a buffering oxidation etching agent for detection.
Further, the detecting by soaking the detected chip in the metal corrosive liquid includes:
soaking the detected chip in a metal corrosive liquid, and taking out the chip after a second time period;
and judging the abnormal shape of the corrosion discoloration of the passivation layer of the chip.
Further, the detecting by soaking the detected chip in the buffered oxide etchant includes:
soaking the detected chip in a buffering oxidation etching agent, and taking out the chip after a first time period;
soaking the detected chip in a metal corrosive liquid, and taking out the chip after a second time period; wherein the second time period is greater than the first time period;
and judging the abnormal shape of the corrosion discoloration of the passivation layer of the chip.
Further, the determining the abnormal morphology of the corrosion discoloration of the passivation layer of the chip includes:
and amplifying the passivation layer of the detected chip through a high-power microscope, and tracking the abnormal corrosion discoloration morphology of the chip.
Further, before the determining the abnormal morphology of the corrosion discoloration of the passivation layer of the chip, the method further includes:
and cleaning and drying the detected chip by adopting deionized water.
Further, after the chip to be detected is immersed in the metal corrosion solution and taken out after a second period of time, the method further includes:
and cleaning and drying the detected chip by adopting deionized water.
Further, the first time period is greater than or equal to 20 minutes;
the second period of time was 4 minutes.
Further, the passivation layer comprises a first inorganic layer adjacent to the metal layer, and a second inorganic layer arranged on the side of the first inorganic layer far away from the metal layer;
the material of the first inorganic layer comprises one or more of silicon dioxide, phosphosilicate glass or borophosphosilicate glass, and the material of the second inorganic layer comprises silicon nitride.
Further, the buffered oxide etchant includes a mixed solution of hydrofluoric acid and ammonium fluoride.
Further, before the chip to be detected is immersed in the metal corrosive liquid for detection, the method further comprises the following steps:
sampling the chip.
The chip pinhole defect detection method provided by the embodiment of the invention detects the pinhole defect of the chip by soaking the detected chip in the metal corrosive liquid, if a blackened and dark area is observed, the passivation layer cracks, the metal corrosive liquid at the defect position invades through the defect position of the passivation layer and corrodes the metal layer at the corresponding position, and thus the pinhole defect of the passivation layer is found in time. If no corrosion discoloration abnormal morphology exists, the detected chip is soaked in the buffer oxidation etching agent for detection, the buffer oxidation etching agent can seep through the passivation layer and corrode silicon dioxide of the passivation layer, so that metal corrosion liquid is used for corroding corresponding metal subsequently, the pinhole defect of a metal layer which does not penetrate through the passivation layer to the bottom can be detected, the accuracy of pinhole detection is improved, the pinhole defect of the passivation layer can be found in time, process optimization measures can be conveniently taken, the chip adopting an advanced flip-chip process is avoided, when the chip is inversely arranged on a base material, short circuit between isolated structures of the chip is caused, and the problem that the pinhole defect of the metal layer which does not penetrate through the passivation layer to the bottom cannot be conveniently detected by the existing detection method for the pinhole defect is solved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the contents of the embodiments of the present invention and the drawings without creative efforts.
FIG. 1 is a flowchart of a method for detecting pin hole defects in a chip according to an embodiment of the present invention;
FIG. 2 is a flow chart of another method for detecting a pinhole defect in a chip according to an embodiment of the present invention;
FIG. 3 is a flow chart of another method for detecting a pinhole defect in a chip according to an embodiment of the present invention;
FIG. 4 is a flowchart of another method for detecting a pinhole defect in a chip according to an embodiment of the present invention;
FIG. 5 is a flowchart of another method for detecting a pinhole defect in a chip according to an embodiment of the present invention;
FIG. 6 is a flowchart of a method for detecting a pinhole defect in a chip according to an embodiment of the present invention;
FIG. 7 is a flowchart of a method for detecting a pinhole defect in a chip according to an embodiment of the present invention;
FIG. 8 is a flowchart of a method for detecting a pinhole defect in a chip according to an embodiment of the present invention;
FIG. 9 is a flowchart of a method for detecting a pinhole defect in a chip according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Based on the above technical problem, the present embodiment proposes the following solutions:
fig. 1 is a flowchart of a method for detecting a pinhole defect in a chip according to an embodiment of the present invention. Referring to fig. 1, the method for detecting a chip pinhole defect provided by the embodiment of the present invention includes:
s101, the detected chip is soaked in metal corrosion liquid for detection, wherein the chip comprises a metal layer and a passivation layer.
And S102, if the abnormal shape of the corrosion discoloration does not exist, soaking the detected chip in a buffered oxidation etching agent for detection.
Specifically, the chip may include a metal layer and a passivation layer, and the pin hole defect detection of the chip is also called a Pinhole test, which is a method for detecting the pin hole of the passivation layer of the chip, i.e., the semiconductor wafer. The passivation layer is an essential process measure for a high-performance and high-reliability chip, can realize the isolation among different devices and wiring in the chip, and has the functions of adsorbing external movable ions and protecting the surface of the chip from being damaged by external machinery and chemistry. The passivation layer may be attached to the metal layer of the chip by a chemical vapor deposition method, and optionally, the passivation layer may include a first inorganic layer adjacent to the metal layer and a second inorganic layer disposed on a side of the first inorganic layer away from the metal layer, the first inorganic layer may include one or more of silicon dioxide (USG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and the second inorganic layer may include silicon nitride. Silicon dioxide and silicon nitride have stronger hardness, PSG has better gettering function due to the function of doping P element, but PSG has the defect of easy moisture absorption, and BPSG has lower reflow temperature and better coverage. The passivation layer is made of different materials in the chip manufacturing process, and the metal material on the front surface of the chip can be different because the stress between different substances is different, and various metal layer steps and other dielectric layer steps can be arranged on one side of the passivation layer adjacent to the metal layer. In the preparation process of a chip, the deposition, polishing, photoetching and other processes can generate temperature change, so that the side wall of the metal layer step and the passivation layer on the surface of the chip are mutually extruded, the internal stress changes, the defects of pinholes, cracks, falling off and the like are easily formed, the deformation in the chip and the short circuit or open circuit of the interconnection wire are caused, and the failure of a device is caused. Therefore, a pinhole defect test is required for the chip.
The detected chip is soaked in the metal corrosive liquid for detection, if a blackened and dark area is observed, the passivation layer cracks, the metal corrosive liquid at the defect position invades through the defect position of the passivation layer and corrodes the metal at the corresponding position, and therefore the pinhole defect of the passivation layer is found in time. If the abnormal morphology of corrosion discoloration does not exist, the passivation layer has no pinhole defect or the first inorganic layer of the passivation layer has pinhole defect but the second inorganic layer has no pinhole defect, because the manufacturing production of the chip is a complicated process, the number of the manufacturing production is hundreds of steps, and the number of the manufacturing production is thousands of steps.
The detection can be performed by soaking the detected chip in a Buffered Oxide Etchant (BOE) because the metal etchant can penetrate through cracked silicon nitride but cannot penetrate through uncracked silicon dioxide. And BOE can seep through the pinholes of the silicon nitride to corrode the complete silicon dioxide below, so that the metal corrosion liquid is used for corroding the corresponding metal subsequently, the pinhole defects that the passivation layer cracks in the silicon nitride but the silicon dioxide does not crack can be detected, and the pinhole detection accuracy is improved.
The method for detecting the pinhole defect of the chip provided by the embodiment is to soak the detected chip in the metal corrosive liquid for detection, if a blackened and dark area is observed, the passivation layer is cracked, the metal corrosive liquid at the defect position invades through the defect position of the passivation layer and corrodes the metal layer at the corresponding position, and thus the pinhole defect of the passivation layer is found in time. If no corrosion discoloration abnormal morphology exists, the detected chip is soaked in the buffer oxidation etching agent for detection, the buffer oxidation etching agent can seep through the passivation layer and corrode silicon dioxide of the passivation layer, so that metal corrosion liquid is used for corroding corresponding metal subsequently, the pinhole defect of a metal layer which does not penetrate through the passivation layer to the bottom can be detected, the accuracy of pinhole detection is improved, the pinhole defect of the passivation layer can be found in time, process optimization measures can be conveniently taken, the chip adopting an advanced flip-chip process is avoided, when the chip is inversely arranged on a base material, short circuit between isolated structures of the chip is caused, and the problem that the pinhole defect of the metal layer which does not penetrate through the passivation layer to the bottom cannot be conveniently detected by the existing detection method for the pinhole defect is solved.
Optionally, the buffered oxide etchant includes a mixed solution of hydrofluoric acid and ammonium fluoride.
Specifically, BOE (a mixed solution of HF acid and ammonium fluoride) is an oxide layer corrosive liquid, silicon nitride can be subjected to osmotic corrosion, the cost is low, and the accuracy of chip pinhole detection is improved under the condition that the cost is not increased.
Optionally, fig. 2 is a flowchart of another method for detecting a chip pinhole defect according to an embodiment of the present invention. On the basis of the above embodiment, referring to fig. 1, the method for detecting a chip pinhole defect provided by the embodiment of the present invention includes:
s201, soaking the detected chip in the metal corrosive liquid, and taking out the chip after a second time period.
Specifically, the metal corrosion liquid can corrode metal, the passivation layer is nonmetal, and when the passivation layer is not cracked or does not penetrate through the cracks, the metal corrosion liquid cannot corrode the metal layer covered by the passivation layer. The second time period needs to be greater than or equal to 20 minutes and may be, for example, 20 minutes, half an hour, or other time period.
S202, judging the abnormal corrosion discoloration morphology of the passivation layer of the chip.
Specifically, the appearance of the passivation layer of the chip after being soaked in the metal corrosive liquid is observed, and the chip is judged to have no corrosion discoloration abnormal appearance or corrosion discoloration abnormal appearance. And if the corrosion discoloration abnormal morphology exists, judging that the passivation layer of the chip has the pinhole defect.
S203, if the abnormal shape of the corrosion discoloration does not exist, soaking the detected chip in a buffering oxidation etching agent for detection.
Optionally, fig. 3 is a flowchart of a method for detecting a chip pinhole defect according to an embodiment of the present invention. On the basis of the above embodiment, referring to fig. 3, the method for detecting a chip pinhole defect provided by the embodiment of the present invention includes:
s301, the chip to be detected is soaked in the metal corrosive liquid for detection.
S302, if the abnormal shape of the corrosion discoloration does not exist, soaking the detected chip in a buffering oxidation etching agent, and taking out the chip after a first time period.
Specifically, the material of the first inorganic layer may include one or more of silicon dioxide (USG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), etc., and the material of the second inorganic layer may include silicon nitride, and the chip to be tested is immersed in a buffered oxide etchant, which may penetrate through the pinholes of the silicon nitride to etch away the intact silicon dioxide of the first inorganic layer. The first period of time may be several minutes, for example, 4 minutes or 5 minutes, etc.
S303, soaking the detected chip in the metal corrosive liquid, and taking out the chip after a second time period; wherein the second time period is greater than the first time period.
Specifically, the corresponding metal is corroded by the metal corrosive liquid.
S304, judging the abnormal corrosion discoloration morphology of the passivation layer of the chip.
Specifically, by observing the abnormal appearance of the corrosion discoloration, if the abnormal appearance of the corrosion discoloration exists, the pinhole defect that the silicon nitride cracks and the silicon dioxide does not crack in the passivation layer can be judged, so that the pinhole detection accuracy is improved; if the abnormal morphology of the corrosion discoloration does not exist, the passivation layer can be judged to have no pinhole defect.
Optionally, fig. 4 is a flowchart of a method for detecting a chip pinhole defect according to an embodiment of the present invention. On the basis of the above embodiment, referring to fig. 4, the method for detecting a chip pinhole defect provided by the embodiment of the present invention includes:
s401, soaking the detected chip in the metal corrosive liquid, and taking out the chip after a second time period.
S402, amplifying the passivation layer of the detected chip through a high-power microscope, and tracking the abnormal corrosion discoloration morphology of the chip.
Specifically, the surface of the chip is observed under a high power microscope, whether phenomena such as corrosion discoloration of the metal layer exist or not is observed, and if the metal layer has obvious phenomena such as corrosion discoloration and even disconnection, the phenomena that the top layer and the bottom layer of the passivation layer both crack are shown.
And S403, if the abnormal shape of the corrosion discoloration does not exist, soaking the detected chip in a buffered oxidation etching agent for detection.
Optionally, fig. 5 is a flowchart of a method for detecting a chip pinhole defect according to an embodiment of the present invention. On the basis of the above embodiment, referring to fig. 5, the method for detecting a chip pinhole defect provided by the embodiment of the present invention includes:
s501, the chip to be detected is soaked in the metal corrosive liquid for detection.
S502, if the abnormal shape of corrosion and discoloration does not exist, soaking the detected chip in a buffering oxidation etching agent, and taking out the chip after a first time period.
S503, soaking the detected chip in the metal corrosive liquid, and taking out the chip after a second time period; wherein the second time period is greater than the first time period;
s504, amplifying the passivation layer of the detected chip through a high-power microscope, and tracking the abnormal corrosion color change appearance of the chip.
Specifically, whether the metal layer has corrosion discoloration or the like can be observed under a high power microscope, so that whether the pinhole defect that the passivation layer cracks and the silicon dioxide does not crack exists on the surface of the chip or not can be judged.
Optionally, fig. 6 is a flowchart of a method for detecting a chip pinhole defect according to an embodiment of the present invention. On the basis of the above embodiment, referring to fig. 6, the method for detecting a chip pinhole defect provided by the embodiment of the present invention includes:
s601, soaking the detected chip in the metal corrosive liquid, and taking out the chip after a second time period.
And S602, washing and drying the detected chip by using deionized water.
Specifically, the glass is rinsed with deionized water and then dried with compressed air, so that the observation is facilitated.
And S603, judging the abnormal corrosion discoloration morphology of the passivation layer of the chip.
And S604, if the abnormal shape of the corrosion discoloration does not exist, soaking the detected chip in a buffered oxidation etching agent for detection.
Optionally, fig. 7 is a flowchart of a method for detecting a chip pinhole defect according to an embodiment of the present invention. On the basis of the above embodiment, referring to fig. 7, the method for detecting a chip pinhole defect provided by the embodiment of the present invention includes:
and S701, soaking the detected chip in a metal corrosive liquid for detection.
S702, if the abnormal shape of the corrosion discoloration does not exist, soaking the detected chip in a buffering oxidation etching agent, and taking out the chip after a first time period.
S703, soaking the detected chip in the metal corrosive liquid, and taking out the chip after a second time period; wherein the second time period is greater than the first time period.
And S704, washing and drying the detected chip by using deionized water.
S705, judging the abnormal corrosion discoloration morphology of the passivation layer of the chip.
Optionally, fig. 8 is a flowchart of a method for detecting a chip pinhole defect according to an embodiment of the present invention. On the basis of the above embodiment, referring to fig. 8, the method for detecting a chip pinhole defect provided by the embodiment of the present invention includes:
and S801, soaking the detected chip in the metal corrosive liquid for detection.
S802, if the abnormal shape of the corrosion discoloration does not exist, soaking the detected chip in a buffering oxidation etching agent, and taking out the chip after a first time period.
And S803, washing and drying the detected chip by using deionized water.
S804, soaking the detected chip in the metal corrosive liquid, and taking out the chip after a second time period; wherein the second time period is greater than the first time period;
optionally, the first time period is greater than or equal to 20 minutes; the second period of time was 4 minutes.
In particular, the amount of the solvent to be used,
and S805, washing and drying the detected chip by using deionized water.
S806, judging the abnormal corrosion discoloration morphology of the passivation layer of the chip.
Optionally, fig. 9 is a flowchart of a method for detecting a chip pinhole defect according to an embodiment of the present invention. On the basis of the above embodiment, referring to fig. 9, the method for detecting a chip pinhole defect provided by the embodiment of the present invention includes:
and S901, sampling the chip.
Specifically, the chip to be detected is sampled, and the sampling can be random sampling or sampling according to the requirement.
And S902, soaking the detected chip in the metal corrosive liquid for detection.
And S903, if the abnormal shape of the corrosion discoloration does not exist, soaking the detected chip in a buffered oxidation etching agent for detection.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A method for detecting pin hole defects of a chip is characterized by comprising the following steps:
soaking the detected chip in a metal corrosive liquid for detection; wherein the chip comprises a metal layer and a passivation layer;
and if the abnormal shape of the corrosion discoloration does not exist, soaking the detected chip in a buffering oxidation etching agent for detection.
2. The method for detecting the pinhole defect of the chip according to claim 1, wherein the detecting by immersing the chip to be detected in the metal corrosive liquid comprises:
soaking the detected chip in a metal corrosive liquid, and taking out the chip after a second time period;
and judging the abnormal corrosion discoloration morphology of the passivation layer of the chip.
3. The method for detecting pinhole defects in a chip according to claim 1, wherein the detecting by immersing the chip to be detected in a buffered oxide etchant comprises:
soaking the detected chip in a buffering oxidation etching agent, and taking out the chip after a first time period;
soaking the detected chip in a metal corrosive liquid, and taking out the chip after a second time period; wherein the second time period is greater than the first time period;
and judging the abnormal corrosion discoloration morphology of the passivation layer of the chip.
4. The method for detecting the pinhole defect of the chip according to claim 2 or 3, wherein the step of judging the abnormal morphology of the corrosion discoloration of the passivation layer of the chip comprises the following steps:
and amplifying the passivation layer of the detected chip through a high-power microscope, and tracking the abnormal corrosion discoloration morphology of the chip.
5. The method for detecting the pinhole defect of the chip according to claim 2 or 3, further comprising, before the determining the abnormal morphology of the corrosion discoloration of the passivation layer of the chip:
and cleaning and drying the detected chip by adopting deionized water.
6. The method for detecting pinhole defects in a chip according to claim 3, wherein after the chip to be detected is immersed in the metal etchant and taken out after a second period of time, the method further comprises:
and cleaning and drying the detected chip by adopting deionized water.
7. The method for detecting pinhole defect in chip according to claim 3,
the first time period is greater than or equal to 20 minutes;
the second period of time was 4 minutes.
8. The method for detecting pinhole defects in a chip according to claim 1,
the passivation layer comprises a first inorganic layer adjacent to the metal layer and a second inorganic layer arranged on one side of the first inorganic layer far away from the metal layer;
the material of the first inorganic layer comprises one or more of silicon dioxide, phosphosilicate glass or borophosphosilicate glass, and the material of the second inorganic layer comprises silicon nitride.
9. The method for detecting pinhole defects in a chip according to claim 1,
the buffered oxide etchant includes a mixture of hydrofluoric acid and ammonium fluoride.
10. The method for detecting pinhole defects in a chip according to claim 1, further comprising, before the detecting by immersing the chip to be detected in a metal etchant, the steps of:
sampling the chip.
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| US6248661B1 (en) * | 1999-03-05 | 2001-06-19 | Taiwan Semiconductor Manufacturing Company | Method for monitoring bubble formation and abnormal via defects in a spin-on-glass planarization, etchback process |
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| CN104795340A (en) * | 2015-04-13 | 2015-07-22 | 上海华力微电子有限公司 | Method for analyzing failures due to defects of ONO (silicon oxide-silicon nitride-silicon oxide) thin films of Flash products |
| CN104851820A (en) * | 2014-02-19 | 2015-08-19 | 北大方正集团有限公司 | Semiconductor device defect detection method |
| CN111599707A (en) * | 2020-05-27 | 2020-08-28 | 广州粤芯半导体技术有限公司 | Method for detecting micro-cracks of passivation layer |
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2021
- 2021-03-29 CN CN202110336501.7A patent/CN113097088A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6248661B1 (en) * | 1999-03-05 | 2001-06-19 | Taiwan Semiconductor Manufacturing Company | Method for monitoring bubble formation and abnormal via defects in a spin-on-glass planarization, etchback process |
| CN104051291A (en) * | 2013-03-11 | 2014-09-17 | 中芯国际集成电路制造(上海)有限公司 | Detection method of metal gate blocking layer pin hole |
| CN104851820A (en) * | 2014-02-19 | 2015-08-19 | 北大方正集团有限公司 | Semiconductor device defect detection method |
| CN104795340A (en) * | 2015-04-13 | 2015-07-22 | 上海华力微电子有限公司 | Method for analyzing failures due to defects of ONO (silicon oxide-silicon nitride-silicon oxide) thin films of Flash products |
| CN111599707A (en) * | 2020-05-27 | 2020-08-28 | 广州粤芯半导体技术有限公司 | Method for detecting micro-cracks of passivation layer |
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