CN112151545A - 包括磁性压持层的半导体设备 - Google Patents

包括磁性压持层的半导体设备 Download PDF

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CN112151545A
CN112151545A CN201910575682.1A CN201910575682A CN112151545A CN 112151545 A CN112151545 A CN 112151545A CN 201910575682 A CN201910575682 A CN 201910575682A CN 112151545 A CN112151545 A CN 112151545A
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semiconductor
die
layer
dies
semiconductor device
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CN112151545B (zh
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刘扬名
叶宁
杨波
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Western Digital Technologies Inc
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Western Digital Technologies Inc
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Abstract

本发明题为“包括磁性压持层的半导体设备”。本发明公开了一种半导体设备，所述半导体设备包括安装在基板上的一个或多个半导体管芯。每个半导体管芯可在所述半导体管芯的下部失活表面上形成有铁磁层。所述铁磁层在制造期间将所述半导体管芯下拉到彼此和所述基板上，以防止所述管芯翘曲。所述铁磁层还平衡所述管芯层之间的热膨胀系数的不匹配，从而进一步防止所述管芯翘曲。

Description

包括磁性压持层的半导体设备
背景技术
便携式消费电子器件需求的强劲增长推动了对高容量存储设备的需求。非易失性半导体存储器设备诸如闪存存储卡已广泛用于满足对数字信息存储和交换的日益增长的需求。此类存储器设备的设计具有便携性、多功能性且坚固耐用，加上它们的高可靠性和大容量，使得它们成为用于各种电子设备的理想选择，包括例如数字相机、数字音乐播放器、视频游戏控制器、PDA、蜂窝电话和固态驱动器。
虽然已知许多不同的封装配置，但是闪存存储卡通常可以被制造为系统级封装(SiP)或多芯片模块(MCM)，其中多个管芯被安装并互连在小占有面积的基板上。基板通常可以包括刚性的电介质基部，该电介质基部具有在一侧或两侧上蚀刻的导电层。在管芯与导电层之间形成电连接，并且导电层提供用于将管芯连接到主机设备的电引线结构。一旦进行管芯与基板之间的电连接，然后就通常将组件封装在提供保护包装的模塑化合物中。
为了最有效地使用封装占用面积，已知的是将半导体管芯堆叠在彼此的顶部。为了在半导体管芯上获得接合焊盘，将管芯彼此完全重叠地堆叠(相邻管芯之间具有间隔层)或者偏移地堆叠。在偏移配置中，将管芯堆叠在另一管芯的顶部，使得下部管芯的接合焊盘暴露出来。
常规堆叠管芯的问题在于，在固化将管芯保持在堆叠中的粘合剂附接膜之前，管芯趋于在非线接合侧处向上翘曲或倾斜。例如，这是由于管芯在堆叠之后冷却时，半导体管芯层具有不同的热膨胀系数。现有技术图1示出了常规半导体封装50的示例，该半导体封装包括堆叠的存储器管芯52，这些存储器管芯在非线接合侧处从基板54向上倾斜。使用管芯附接膜(DAF)层将管芯附连到每个基板。然而，在固化DAF层之前，管芯的翘曲可能导致DAF层剥离以及相邻半导体管芯之间和/或最底部管芯与基板之间形成空隙。
这由于一些原因可能存在问题。例如，来自模塑化合物的二氧化硅颗粒可以进入DAF已经分离并且管芯已经翘曲的管芯之间。图1示出了底部管芯下面的二氧化硅颗粒56的示例。在模塑工艺的压力下，这些二氧化硅颗粒56会导致管芯破裂。
此外，在一些情况下，管芯可能翘曲并倾斜到顶部管芯的边缘延伸穿过封装模塑化合物56的表面的点，然后暴露于外部环境。封装制造商在封装表面上打印封装名称、规格、标识和/或其他信息。如果已知管芯边缘突出，可将管芯边缘突出的区域指定为禁止区域，不能在其中打印任何东西。这限制了制造商在封装表面上打印的能力。
附图说明
图1是常规半导体封装中的管芯堆叠倾斜的横截面边缘视图。
图2是根据本发明技术的实施方案的用于形成半导体设备的流程图。
图3是根据本发明技术的实施方案的半导体晶圆的顶视图。
图4是根据本发明技术的实施方案的半导体管芯的透视图。
图5是根据本发明技术的实施方案的半导体管芯的横截面边缘视图。
图6是根据本发明技术的实施方案的半导体管芯的连续平坦铁磁层的顶视图。
图7至图9是根据本发明技术的实施方案的半导体管芯的铁磁层的另外的实施方案的顶视图。
图10是根据本发明技术的实施方案的在制造的第一阶段包括多个堆叠管芯的半导体设备的示例。
图11是根据本发明技术的实施方案的在制造的第二阶段包括多个堆叠管芯的半导体设备的示例。
图12是根据本发明技术的实施方案的包括多个堆叠管芯的完成的半导体设备的示例。
具体实施方式
现在将参考附图描述本发明的技术，附图在实施方案中涉及包括安装在基板上的一个或多个半导体管芯的半导体设备。每个半导体管芯可在半导体管芯的下部失活表面上形成有铁磁层。在制造之后，一个或多个管芯可安装在基板上，该基板本身安装在磁性载体上。磁性载体在管芯中的每一个的铁磁层上施加吸引磁力，以便将管芯向下拉到基板上，并防止管芯在管芯附接过程中向上倾斜。一旦固化管芯中的每一个的下表面上的管芯附接膜(DAF)以将管芯平坦地固定在基板上，就可移除磁性载体。
本发明技术能够减少和/或消除管芯在悬伸区域处的倾斜，并且可以通过磁力来增强DAF粘附性和均一性，从而防止模具翘曲以及DAF空隙和剥离。此外，铁磁层进一步平衡了半导体管芯内不同层的热膨胀系数的不匹配，从而进一步防止了管芯翘曲以及DAF空隙和剥离。
应当理解，本发明可体现为许多不同形式并且不应解释为限于本文所阐述的实施方案。相反，提供了这些实施方案，使得本公开将是周密且完整的，并且将充分地将本发明传达给本领域的技术人员。实际上，本发明旨在覆盖这些实施方案的另选方案、修改和等同物，这些均包括在由所附权利要求书所限定的本发明的范围和实质内。此外，在本发明的以下具体实施方式中，给出了许多具体细节，以便提供对本发明的周密理解。然而，对于本领域的普通技术人员将显而易见的是，本发明可在没有此类具体细节的情况下被实施。
本文所用的术语“顶部”和“底部”、“上”和“下”以及“垂直”和“水平”及其形式，如可仅以举例方式和出于示例性目的用于本文，并且不旨在限制技术的描述，因为所引用的项目可在位置和取向上交换。另外，如本文所用，术语“基本上”和/或“约”是指指定的尺寸或参数可在给定应用的可接受的制造公差内变化。在一个实施方案中，可接受的制造公差为给定尺寸的±2.5％。
现在将参考图2的流程图以及图3至图12的视图解释本发明技术的实施方案。在步骤200中，可将半导体晶圆100加工成多个半导体管芯102，如图3所示。半导体晶圆100开始时可以是晶圆材料的晶锭，晶圆材料可以是根据Czochralski(CZ)或浮区(FZ)工艺生长的单晶硅。然而，在另外的实施方案中，第一晶圆100可由其他材料并通过其他工艺形成。
半导体晶圆100可从晶锭切割而来并在第一主平坦表面104和与表面104相对的第二主平坦表面106(图5)两者上抛光，以提供平滑表面。第一主表面104可在步骤200中经历各种加工以将晶圆100分成相应的半导体管芯102，并且在第一主表面104上和/或第一主表面104中形成相应半导体管芯102的集成电路122。图3中在晶圆100上所示的半导体管芯102的数量和图案是出于说明的目的，并且晶圆100可包括比在另外的实施方案中所示更多的半导体管芯102，以及不同的图案。
在步骤200中形成的集成电路122可包括形成在包括层124和层126的介电基板中的存储器单元和逻辑，如图5的横截面边缘视图所示。在实施方案中，集成电路122可形成为3D堆叠存储器结构，该结构具有形成为层的存储器单元串。然而，应当理解，可加工半导体管芯102，以包括除3D堆叠存储器结构之外的集成电路。可在上部介电膜层126的顶部形成钝化/聚酰亚胺层128。
在形成集成电路122之后，可在步骤204中在半导体管芯102内形成内部电连接件。内部电连接件可包括穿过介电膜126的层顺序地形成的多层金属互连件130和通孔132。如本领域中已知的，可使用光刻工艺和薄膜沉积工艺一次一层地形成金属互连件130、通孔132和介电膜层126。光刻工艺可包括例如图案定义、等离子体、化学或干法蚀刻和抛光。薄膜沉积工艺可包括例如溅射和/或化学气相沉积。金属互连件130可由各种导电金属形成，包括例如本领域中已知的铜和铜合金，并且通孔132可衬有和/或填充有各种导电金属，包括例如本领域中已知的钨、铜和铜合金。
在步骤208中，可在半导体管芯102的主平坦表面104上形成接合焊盘。如图4和图5所示，这些接合焊盘可包括一排接合焊盘108，但应当理解，接合焊盘108能够以各种图案和各种数量设置在管芯102的表面上。可蚀刻钝化层128，并且可在钝化层的蚀刻区域中在衬垫105上方形成每个接合焊盘108。如本领域中已知的，接合焊盘108可由例如铜、铝以及它们的合金形成，并且衬垫105可由例如钛/氮化钛堆叠(诸如，例如Ti/TiN/Ti)形成，不过在另外的实施方案中这些材料可有所不同。可通过气相沉积和/或镀覆技术来施加接合焊盘108和衬垫105。接合焊盘和衬垫一起可具有720nm的厚度，不过在另外的实施方案中该厚度可更大或更小。集成电路122可通过金属互连130和通孔132电连接到接合焊盘108。
在步骤210中，晶圆100的失活表面、特别是介电层124可经历背面研磨工艺，以将晶圆100薄化至最终厚度。在实施方案中，晶圆的最终厚度可例如为30μm至40μm，不过该最终厚度可比另外的实施方案中的最终厚度更小或更大。
根据本发明技术的方面，接下来可在晶圆100的失活表面上、特别是在介电层124上形成铁磁层110。铁磁层110可由例如铁、钢、不锈钢(Fe)、镍(Ni)、钴(Co)、石墨烯或经受磁力的其他材料形成。可通过溅镀或其他薄膜沉积方法，诸如化学气相沉积和物理气相沉积施加该铁磁层。代替铁磁材料或除铁磁材料之外，层110可由亚铁磁材料形成。此外，除了非磁性材料之外，层110本身可由磁性材料形成，包括例如铝镍钴(铝镍钴合金)或各种铁氧体(由铁氧化物与镍、锶或钴的混合物制成的陶瓷类材料)。这种磁性材料可设置有与载体134的磁体相反的磁极，将在下文中说明。
在实施方案中，层110可以是实心连续(无空隙)平坦材料层，如图6的顶视图所示。在另外的实施方案中，层110可用直的或弯曲的材料节段图案化，其间具有空隙，例如如图7至图9所示。可以设想其他图案。在实施方案中，铁磁层110可为1μm至2μm，不过其可比另外的实施方案中的铁磁层更薄或更厚。
再次参考图2的流程图和图5的横截面视图，在步骤216中，可将管芯附接膜(DAF)层112附连在铁磁层110上方。作为一个示例，DAF层112可以是来自Henkel AG&Co.KGaA的8988UV环氧树脂，不过可使用其他类型的膜。DAF层112可为5μm至10μm，不过其可更薄或更厚，并且可通过旋涂或其他方法施加并固化到B阶段。如下所述，在将管芯102堆叠在基板和磁性载体上之后，可将DAF层固化到最终的C阶段。
在步骤218中，可通过已知方法(例如通过激光或锯片)从晶圆100切割各个管芯，以提供各个半导体管芯102，诸如图4所示。
在步骤220中，可将一个或多个半导体管芯102安装在基板120上，如图10的边缘视图所示。半导体管芯102可以例如是闪存存储器管芯，诸如2D NAND闪存存储器或3D BiCS(位成本缩放)、V-NAND或其他3D闪存存储器，但可以使用其他类型的管芯102。这些其他类型的半导体管芯包括但不限于控制器管芯(诸如ASIC)或RAM(诸如SDRAM、DDR SDRAM、LPDDR和GDDR)。堆叠122中所示的管芯102的数量仅作为示例，并且实施方案可包括不同数量的半导体管芯，包括例如1、2、4、8、16、32或64个管芯。在另外的实施方案中可存在其他数量的管芯。
在包括多个半导体管芯102的情况下，可将半导体管芯102以偏移阶梯式配置堆叠在彼此之上，以形成管芯堆叠122，例如如图10所示。可将管芯偏移地堆叠，使得堆叠中的管芯上的管芯接合焊盘108保持暴露并且不被接下来的上部管芯覆盖。当将管芯102堆叠在彼此和基板120上时，可将该管芯加热例如至150℃，以软化b阶段DAF层112并促进正确的堆叠。在步骤220中堆叠管芯之后，可将管芯堆叠122冷却至室温。
如背景技术部分中所述，例如由于半导体管芯102的不同层具有不同的热膨胀系数，因此常规管芯在堆叠之后冷却时趋于向上翘曲和/或弯曲，如现有技术图1所示。根据本发明技术的方面，可将基板120进一步安装在磁性载体134上，该磁性载体在堆叠122中的相应管芯102中的铁磁层110上施加磁力，从而将它们下拉平放在彼此和基板120上。
磁性载体134可以是或包括永磁体，该永磁体由例如铝镍钴(铝镍钴合金)或各种铁氧体(由铁氧化物与镍、锶或钴的混合物制成的陶瓷类材料)形成。永磁体可具有支撑基板120的下表面的上表面。另选地，可将永磁体安装在外壳内，该外壳具有支撑基板120的下表面的上表面。在该示例中，外壳本身可以是铁磁材料或非铁磁材料。
磁性载体134可另选地包括电磁体，该电磁体具有缠绕在铁磁芯周围的导线，使得电磁体在电流通过该线时变为磁性的。在此类示例中，该线可以是铜，并且该芯可以是铁或其他铁磁材料。可将电磁体安装在外壳内，该外壳具有支撑基板120的下表面的上表面。在该示例中，外壳本身可以是铁磁材料或非铁磁材料。
如上所述，在制造过程的这一点上，基板120可以是基板的面板的一部分。在这种情况下，可存在用于基板的整个面板的单个载体134。另选地，每个基板120可具有其自己的载体134。可用可移除的粘合剂将基板120附连到载体134。
如图10中的箭头所示，磁性载体134在管芯堆叠122中的管芯102中的每一个的铁磁层110上施加吸引力。吸引力可足够大以克服趋于使管芯102翘曲或将管芯的端部向上拉离基板或彼此的任何力。因此，在磁性载体的吸引力下，管芯102中的每一个可平放在其下方的管芯上，并且最底部管芯102可平放在基板102上。
在磁性载体的磁力下，管芯牢固地保持在彼此和基板上，可在步骤222中将管芯中的每一个的DAF层112从b阶段固化到最终的c阶段，以将管芯102永久地附连到彼此和基板120。可通过加热和压力将DAF层112硬化到c阶段。在一个示例中，可将管芯堆叠122加热至150℃保持数小时以固化DAF层112，不过在另外的实施方案中温度和持续时间可有所不同。
除了加热之外，由吸引磁力产生的压力进一步确保了固化过程中管芯102紧密且牢固地接合到彼此和基板上。在固化DAF层112时，将管芯固定在堆叠中的适当位置，并且在固化之后不会发生管芯翘曲或倾斜。一旦将DAF层112固化，就可在步骤224中将基板与磁性载体134分离。在实施方案中，从步骤220中将管芯102堆叠在基板120上直到在步骤222中固化DAF层112之后，都可使用磁性载体122。
在步骤226中，可将半导体管芯102电互连到彼此和基板120。图11示出了线接合138的边缘视图，该线接合在相应管芯102上的对应管芯接合焊盘108之间沿着堆叠122向下形成，然后接合到基板120的上表面上的接触焊盘。可通过球焊技术形成线接合，但其他线接合技术也是可能的。在另外的实施方案中，可通过其他方法(包括通过硅通孔(TSV))将半导体管芯102电互连到彼此和基板120。
在将管芯102电连接到基板120之后，可在步骤228中且如图12所示将半导体设备150封装在模塑化合物140中。模塑化合物140可包括例如固体环氧树脂、酚醛树脂、熔融二氧化硅、结晶二氧化硅、炭黑和/或金属氢氧化物。可以设想其他模塑化合物。模塑化合物可通过各种已知工艺施加，包括通过压缩模塑、FFT(无流动薄)模塑、传递模塑或注塑成型技术。
在半导体设备150是BGA(球栅阵列)封装的情况下，可在步骤230中将焊料球144附连到基板120的下表面上的接触焊盘，如图12所示。焊料球144可用于将半导体设备150焊接到主机设备(未示出)，诸如印刷电路板。在半导体设备150是LGA(格栅阵列)封装的情况下，可省略焊料球144。
如上所述，半导体设备150可形成在基板的面板上。在形成和封装基板100之后，可在步骤232中将基板100彼此分割，以形成完成的半导体设备150，如图12所示。可通过多种切割方法(包括锯切、水射流切割、激光切割、水导激光切割、干介质切割和金刚石涂层线切割)中的任何一种来分割半导体设备150。虽然直线切割将限定大致矩形或正方形的半导体设备150，但应当理解，在本发明技术的另外的实施方案中，半导体设备150可具有除矩形和正方形之外的形状。
在管芯102的底部包括铁磁层110提供了若干优点。首先，在将每个管芯的铁磁层110安装在磁性载体上时，该铁磁层用于将管芯下拉平放在彼此和基板上。
其次，每个管芯102的铁磁层110用于平衡不同的热膨胀系数，否则当将它们堆叠之后冷却时往往会使管芯翘曲。具体地讲，再次参考图5，钝化/聚酰亚胺层128的热膨胀系数(CTE)相对较大，为约20ppm/k。集成电路层122的CTE为约10ppm/k-15ppm/k，并且介电层124的CTE为约3ppm/k。在升高的温度(例如，150℃)下将管芯102安装在基板上。当管芯102在堆叠后冷却至室温时，钝化/聚酰亚胺层128和电路层122发生相对较大的收缩，导致在常规设计中发生翘曲。
根据本发明技术的另外方面，管芯102的底表面上的铁磁层110也具有相对大的CTE，例如10ppm/k-15ppm/k。在管芯102的底表面上提供铁磁层110平衡了管芯102上的相应层之间的CTE不匹配，并且进一步防止了管芯在冷却时发生翘曲。具体地讲，集成电路层122和铁磁层110的CTE可彼此大致相等，并且两者都大于设置在它们之间的介电层124的热膨胀系数。类似地，钝化/聚酰亚胺层128和铁磁层110的CTE两者均大于设置在它们之间的介电层124的热膨胀系数。
概括地说，本发明技术的示例涉及一种半导体设备，包括：基板；和堆叠在基板上且彼此阶梯式偏移的多个半导体管芯，每个半导体管芯包括：管芯的第一表面上的一组管芯接合焊盘，以及管芯的第二表面上的铁磁层，半导体管芯的铁磁层被配置成朝向基板牵拉多个半导体管芯并平衡多个半导体管芯的管芯层中的热膨胀系数的不匹配。
在另一示例中，本发明技术涉及一种半导体设备，包括：基板；和堆叠在基板上的多个半导体管芯，每个半导体管芯包括：集成电路层、介电层和铁磁层，集成电路层设置在介电层的第一侧上，并且铁磁层设置在介电层的第二侧上，多个半导体管芯偏移地堆叠在基板上，使得每个半导体管芯上的管芯接合焊盘组暴露出来，半导体管芯的铁磁层被配置成朝向基板牵拉多个半导体管芯并平衡集成电路层和介电层中的热膨胀系数的不匹配。
在另一示例中，本发明技术涉及一种半导体设备，包括：基板；和堆叠在基板上且彼此阶梯式偏移的多个半导体管芯，每个半导体管芯包括：管芯的第一表面上的一组管芯接合焊盘，以及用于朝向基板牵拉多个半导体管芯并用于平衡多个半导体管芯的管芯层中的热膨胀系数的不匹配的铁磁装置。
已出于例证和描述的目的提出本发明的上述具体实施方式。它并非旨在是穷尽的或将本发明限制为所公开的精确形式。根据以上教导内容，很多修改形式和变型形式都是可能的。选择所述实施方案是为了最佳地阐明本发明的原理以及其实际应用，以由此使得本领域的其他技术人员能够最佳地在各种实施方案中使用具有适合于所构想的特定用途的各种修改的本发明。本发明的范围旨在由所附权利要求书限定。

Claims (20)

1.一种半导体设备，包括：
基板；和
多个半导体管芯，所述多个半导体管芯堆叠在所述基板上并且彼此阶梯式偏移，每个半导体管芯包括：
一组管芯接合焊盘，所述一组管芯接合焊盘在所述管芯的第一表面上，和
铁磁层，所述铁磁层在所述管芯的第二表面上，所述半导体管芯的所述铁磁层被配置成朝向所述基板牵拉所述多个半导体管芯并平衡所述多个半导体管芯的管芯层中的热膨胀系数的不匹配。
2.根据权利要求1所述的半导体设备，其中所述多个半导体管芯中的每个管芯的所述铁磁层是连续平坦层。
3.根据权利要求1所述的半导体设备，其中所述多个半导体管芯中的每个管芯的所述铁磁层被图案化成包括空隙。
4.根据权利要求1所述的半导体设备，其中所述多个半导体管芯中的每个管芯的所述铁磁层的厚度为1μm至2μm。
5.根据权利要求1所述的半导体设备，其中所述多个半导体管芯中的每个管芯的所述铁磁层包括铁、钢、不锈钢、镍、钴和石墨烯中的一种。
6.根据权利要求1所述的半导体设备，还包括用于将所述多个管芯粘附到彼此和所述基板的多个管芯附接膜层。
7.根据权利要求1所述的半导体设备，其中每个半导体管芯包括集成电路层和介电层，所述集成电路层设置在所述介电层的第一侧上，并且所述铁磁层设置在所述介电层的第二侧上。
8.根据权利要求7所述的半导体设备，其中所述集成电路层和所述铁磁层的热膨胀系数大于所述介电层的热膨胀系数。
9.根据权利要求7所述的半导体设备，其中每个半导体管芯还包括钝化/聚酰亚胺层，所述钝化/聚酰亚胺层设置在所述介电层的所述第一侧上。
10.根据权利要求9所述的半导体设备，其中所述钝化/聚酰亚胺层和所述铁磁层的热膨胀系数大于所述介电层的热膨胀系数。
11.一种半导体设备，包括：
基板；和
多个半导体管芯，所述多个半导体管芯堆叠在所述基板上，每个半导体管芯包括：
集成电路层；
介电层；和
铁磁层，所述集成电路层设置在所述介电层的第一侧上，并且所述铁磁层设置在所述介电层的第二侧上，所述多个半导体管芯偏移地堆叠在所述基板上，使得每个半导体管芯上的管芯接合焊盘组暴露出来，所述半导体管芯的所述铁磁层被配置成朝向所述基板牵拉所述多个半导体管芯并平衡所述集成电路层和所述介电层中的热膨胀系数的不匹配。
12.根据权利要求11所述的半导体设备，其中每个半导体管芯还包括钝化/聚酰亚胺层，所述钝化/聚酰亚胺层设置在所述介电层的所述第一侧上。
13.根据权利要求12所述的半导体设备，其中所述钝化/聚酰亚胺层和所述铁磁层的热膨胀系数大于所述介电层的热膨胀系数。
14.根据权利要求11所述的半导体设备，其中所述多个半导体管芯中的每个管芯的所述铁磁层是连续平坦层。
15.根据权利要求11所述的半导体设备，其中所述多个半导体管芯中的每个管芯的所述铁磁层被图案化成包括空隙。
16.根据权利要求11所述的半导体设备，其中所述多个半导体管芯中的每个管芯的所述铁磁层包括铁、钢、不锈钢、镍、钴和石墨烯中的一种。
17.根据权利要求11所述的半导体设备，还包括用于将所述多个管芯粘附到彼此和所述基板的多个管芯附接膜层。
18.根据权利要求11所述的半导体设备，其中所述多个半导体管芯包括闪存存储器管芯。
19.一种半导体设备，包括：
基板；和
多个半导体管芯，所述多个半导体管芯堆叠在所述基板上并且彼此阶梯式偏移，每个半导体管芯包括：
一组管芯接合焊盘，所述一组管芯接合焊盘在所述管芯的第一表面上，和
铁磁装置，所述铁磁装置用于朝向所述基板牵拉所述多个半导体管芯并用于平衡所述多个半导体管芯的管芯层中的热膨胀系数的不匹配。
20.根据权利要求19所述的半导体设备，其中每个半导体管芯还包括：
集成电路层；
介电层，所述集成电路层设置在所述介电层的第一侧上，并且所述铁磁装置设置在所述介电层的第二侧上，所述铁磁装置进一步平衡所述集成电路层和所述介电层中的热膨胀系数的不匹配。
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