CN112117194B - Manufacturing method of chip packaging structure - Google Patents

Manufacturing method of chip packaging structure Download PDF

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Publication number
CN112117194B
CN112117194B CN201910538944.7A CN201910538944A CN112117194B CN 112117194 B CN112117194 B CN 112117194B CN 201910538944 A CN201910538944 A CN 201910538944A CN 112117194 B CN112117194 B CN 112117194B
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layer
package
plastic
die
forming
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CN112117194A (en
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周辉星
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SIPLP Microelectronics Chongqing Ltd
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SIPLP Microelectronics Chongqing Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Abstract

The invention provides a method for manufacturing a chip packaging structure, which is characterized in that a multi-grain packaging structure is divided into a plurality of areas, and each area comprises a plurality of grains; and in the step of forming a second plastic packaging layer for embedding the outer pins on the multi-grain packaging structure, the second plastic packaging layer between the adjacent areas is isolated during curing. The liquid plastic packaging material is partitioned into a plurality of small areas, so that the shrinkage range of the liquid plastic packaging material during curing is reduced to the small areas from the whole multi-grain packaging structure, the shrinkage stress is reduced in multiples, the warping problem of the multi-chip packaging structure is solved, and the electric connection reliability problem of the outer pins is solved.

Description

Manufacturing method of chip packaging structure
Technical Field
The invention relates to the technical field of chip packaging, in particular to a manufacturing method of a chip packaging structure.
Background
In recent years, with the continuous development of circuit integration technology, electronic products are increasingly developed toward miniaturization, intellectualization, high performance, and high reliability. The packaging technique not only affects the performance of the product, but also restricts the miniaturization of the product.
However, the existing chip package has low production efficiency and unreliable package structure performance.
In view of the above, the present invention provides a method for manufacturing a novel chip package structure to solve the above technical problems.
Disclosure of Invention
The invention aims to provide a manufacturing method of a chip packaging structure, which improves the production efficiency and the performance reliability of the packaging structure.
In order to achieve the above object, the present invention provides a method for manufacturing a chip package structure, including:
providing a multi-die package structure, wherein the multi-die package structure comprises a first plastic package layer and a plurality of dies embedded in the first plastic package layer, each die comprises a front surface and a back surface, and the front surface is provided with an electrical interconnection structure; the front surface is exposed outside the first plastic package layer;
forming an outer pin on the front surface of each crystal grain in the multi-crystal grain packaging structure;
dividing the multi-die packaging structure into a plurality of regions, wherein each region comprises a plurality of dies; forming a second plastic package layer embedding the outer pins on the multi-grain packaging structure, wherein in the second plastic package layer forming step, the second plastic package layer between adjacent regions is isolated during curing;
grinding the second plastic packaging layer until the outer pins are exposed to form a multi-chip packaging structure;
and cutting the multi-chip packaging structure to form a plurality of chip packaging structures.
Optionally, in the step of forming the second plastic package layer, the second plastic package layer is formed by a plastic package film mounted by hot pressing, and the second plastic package layer between adjacent regions is separated and disconnected during curing by the plastic package film mounted at intervals.
Optionally, in the step of forming the second plastic package layer, the second plastic package layer is formed through an injection molding process, and the separation of the second plastic package layer between adjacent regions during curing is realized by arranging a stop block or a mold frame.
Optionally, the area of each region is equal.
Optionally, the number of grains within each region is equal.
Optionally, a redistribution layer is formed on a front surface of each die in the multi-die package structure, and the outer leads are formed on the redistribution layer; or sequentially forming a rewiring layer and a fan-out circuit on the front surface of each crystal grain in the multi-crystal grain packaging structure, wherein the outer pins are formed on the fan-out circuit.
Optionally, forming the redistribution layer comprises:
forming a photoresist layer on the front surface of each exposed crystal grain and the first plastic packaging layer;
exposing and developing the photoresist layer, and removing the photoresist layer in a first preset area, wherein the first preset area corresponds to a bonding pad on the front surface of the crystal grain, and the bonding pad is electrically connected with the electrical interconnection structure;
filling a metal layer in the first preset area to form the rewiring layer;
and ashing to remove the residual photoresist layer.
Optionally, forming a fan-out line on the rewiring layer includes:
forming a third plastic packaging layer on the first plastic packaging layer and the rewiring layer;
removing part of the third plastic packaging layer to form a through hole, wherein the through hole exposes the rewiring layer;
forming a photoresist layer in the through hole and on the third plastic packaging layer outside the through hole;
exposing and developing the photoresist layer to reserve the photoresist layer of a second preset area;
filling a metal layer in a complementary region of the second preset region to form the fan-out line;
and ashing and removing the residual photoresist layer in the second preset area.
Optionally, the forming an outer pin on the fanout line includes:
forming a photoresist layer on the fan-out circuit and the third plastic packaging layer;
exposing and developing the photoresist layer to reserve the photoresist of a third preset area;
filling a metal layer in a complementary region of the third predetermined region to form the outer pin;
ashing and removing the residual photoresist layer in the third preset area;
and forming the second plastic packaging layer on the third preset area and the outer pin.
Optionally, the filling metal layer is completed by an electroplating process.
Optionally, the photoresist layer is a photosensitive film.
Optionally, the method for manufacturing the multi-die package structure includes:
providing a plurality of crystal grains and a carrier plate, fixing the front surfaces of the crystal grains on the carrier plate, and forming a first plastic packaging layer embedding the crystal grains on the carrier plate to form the multi-crystal-grain packaging structure;
and removing the carrier plate to expose the front surface of each crystal grain.
Optionally, the dies formed by cutting the multiple wafers are carried on the same carrier to form a multi-die package structure.
Optionally, before removing the carrier plate, thinning the first molding compound layer in the multi-die package structure until the back surfaces of the multiple dies are exposed.
Optionally, before forming the first molding compound layer, a sealing layer is formed on the back surfaces of the dies and the surface of the carrier between the dies, where the sealing layer is used to prevent the plurality of dies from shifting on the carrier when the first molding compound layer is cured.
Optionally, the first molding compound layer includes an inner surface embedding a plurality of dies and an outer surface opposite to the inner surface, and the multi-die package structure includes a supporting plate located on the outer surface of the first molding compound layer, and the supporting plate is removed after the step of grinding the second molding compound layer until the outer leads are exposed.
Compared with the prior art, the invention has the beneficial effects that:
1) dividing a multi-die packaging structure into a plurality of areas, wherein each area comprises a plurality of dies; and in the step of forming a second plastic packaging layer for embedding the outer pins on the multi-grain packaging structure, the second plastic packaging layer between the adjacent areas is isolated during curing. The liquid plastic packaging material is spaced, the shrinkage range of the liquid plastic packaging material during curing can be reduced to a plurality of small areas from the whole multi-chip packaging structure, so that the shrinkage stress is reduced in multiples, the warping problem of the multi-chip packaging structure is improved, and the electric connection reliability problem of the outer pins is improved.
2) In the alternative, a) the separation of the second plastic package layer between adjacent regions is realized by mounting plastic package films at intervals during curing; or b) the separation of the second plastic sealing layer between adjacent areas during curing is realized by arranging a stop block or a mould frame. a) The second plastic package layer in the scheme is formed by the plastic package films which are mounted in a hot pressing mode, namely the plastic package films are mounted in each area only, and after the plastic package films in the adjacent areas are melted in a hot pressing mode, the liquid plastic package materials are solidified when the liquid plastic package materials do not flow to be connected. b) The second plastic package layer in the scheme is formed through an injection molding process, and a stop block or a mold frame for limiting the flow of the liquid plastic package material is arranged between adjacent regions before the injected liquid plastic package material, so that the liquid plastic package material is isolated during solidification.
3) In an alternative scheme, the areas of all the regions are equal, so that the contraction stress of the second plastic package layers of all the regions is approximately equal, and the warping probability of the multi-chip packaging structure is reduced. Furthermore, the number of the crystal grains in each area is equal, so that the shrinkage stress of the second plastic package layers in the areas is equal.
4) In an alternative, a) a rewiring layer is formed on the front surface of each die in the multi-die package structure, and the outer pins are formed on the rewiring layer; or b) sequentially forming a rewiring layer and a fan-out circuit on the front surface of each crystal grain in the multi-crystal-grain packaging structure, wherein the outer pins are formed on the fan-out circuit. a) And b) the scheme can realize the expansion of the narrow space between the bonding pads on the front surface of the crystal grain to the larger space between the outer pins.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a chip package structure according to an embodiment of the invention;
FIGS. 2 to 6 are schematic intermediate structures corresponding to the flow chart of FIG. 1;
FIG. 7 is a flow chart of a method for fabricating a chip package structure according to another embodiment of the present invention;
fig. 8 to 33 are intermediate structural diagrams corresponding to the flow in fig. 7.
To facilitate an understanding of the invention, all reference numerals appearing in the invention are listed below:
first plastic packaging layers 100, 200 and 200 'of multi-die packaging structures 10 and 20'
Front sides 101a, 201a of dies 101, 201
Outer leads 11, 21 of back surfaces 101b, 201b
Second plastic packaging layers 12 and 29 for chip packaging structures 1a and 2a
Carrier 4 pad 2010
Seal layer 202 rewiring layer 22
Fan-out line 23 photoresist layers 24, 27, 28
First predetermined area A third plastic packaging layer 25
Second predetermined region B of through-hole 26
Third predetermined area C area Q
Plastic packaging film 29' mould 6
Upper mold body 61 and lower mold body 62
Stop block 30 and mold frame 31
Supporting plate 5 multi-chip packaging structure 1, 2
Detailed Description
Fig. 1 is a flowchart of a method for manufacturing a chip package structure according to an embodiment of the invention. Fig. 2 to 6 are intermediate schematic diagrams corresponding to the flow in fig. 1.
First, referring to step S01 in fig. 1 and fig. 2, a multi-die package 10 is provided, the multi-die package 10 includes a first molding compound layer 100 and a plurality of dies 101 embedded in the first molding compound layer 100, each die 101 includes a front surface 101a and a back surface 101b, the front surface 101a has an electrical interconnection structure (not shown); the front surface 101a is exposed outside the first molding layer 100.
Next, referring to step S02 in fig. 1 and fig. 3, the outer leads 11 are formed on the front surface 101a of each die 101 in the multi-die package 10.
Thereafter, referring to step S03 in fig. 1 and fig. 4, the second molding compound layer 12 embedding the outer leads 11 is formed on the multi-die package 10.
Then, referring to step S04 in fig. 1 and fig. 5, the second molding compound layer 12 is ground until the outer leads 11 are exposed, so as to form the multi-chip package structure 1;
referring to step S05 in fig. 1 and fig. 6, the multi-chip package structure 1 is diced to form a plurality of chip package structures 1 a.
In the above embodiment, the outer leads 11 and the outer leads 11 are simultaneously fabricated for the plurality of dies 101, so that the production efficiency in the packaging process can be improved compared with the scheme of fabricating the outer leads 11 and the outer leads 11 for each die 101. However, the manufactured chip package structure 1a has a problem of performance reliability. The reason is that:
referring to fig. 4, the multi-die package structure 10 may warp due to the shrinkage of the molding compound during the formation of the second molding layer 12. It is understood that the larger the number of dies 101 packaged at a time, the larger the planar size of the multi-die package structure 10, and the more severe the warpage problem. This results in: referring to fig. 5, in the step of grinding the second molding compound layer 12 to expose the outer leads 11, the grinding amount is difficult to control accurately, there is over grinding of a part of the outer leads 11, and a part of the outer leads 11 is still covered with the second molding compound layer 12. Referring to fig. 6, in the chip package structure 1a formed after dicing, the upper surfaces of some of the outer leads 11 are uneven, and cannot be reliably electrically connected to an external circuit, and some of the outer leads 11 cannot be electrically connected to an external circuit.
In view of the above problems, another embodiment of the present invention provides an improvement. The improvement scheme comprises: dividing the multi-die package 10 into a plurality of regions, each region including a plurality of dies 101; in the step of forming the second molding compound layer 12 embedding the outer leads 11 on the multi-die package structure 10, the second molding compound layer 12 between adjacent regions is isolated during curing. Compared with the former embodiment, the liquid plastic packaging material is partitioned into a plurality of small areas, the shrinkage stress is reduced by times due to the reduction of the shrinkage range when the liquid plastic packaging material is solidified, the warping degree of the multi-chip packaging structure is reduced, and the problem of the electric connection reliability of the outer pin 11 can be further improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 7 is a flowchart of a method for manufacturing a chip package structure according to another embodiment of the invention. Fig. 8 to 33 are intermediate structural diagrams corresponding to the flow in fig. 7.
First, referring to step S1 in fig. 7 and fig. 8, a multi-die package 20 is provided, the multi-die package 20 includes a first molding compound 200 and a plurality of dies 201 embedded in the first molding compound 200, each die 201 includes a front surface 201a and a back surface 201b, the front surface 201a has an electrical interconnection structure (not shown); the front surface 201a is exposed outside the first molding layer 200.
The step S1 may specifically include steps S11 to S12.
Fig. 9 is a top view of a multi-die package; fig. 10 is a sectional view taken along line AA in fig. 9.
Step S11, referring to fig. 10, providing a plurality of dies 201 and a carrier 4, and fixing the front surfaces 201a of the dies 201 on the carrier 4; a first molding compound layer 200 embedding a plurality of dies 201 is formed on the carrier 4 to form a multi-die package 20.
The number of the die 201 may be two, three, all the die after one wafer dicing, or even all the die after a plurality of wafer dicing, and the invention is not limited to the number of the die 201.
The wafer may be thinned before dicing to reduce the thickness of the multi-die package 20.
Die 201 contains a variety of devices and electrical interconnect structures are used to electrically connect the various devices. Specifically, the front side 201a of the die 201 may have pads 2010, the pads 2010 being connected to electrical interconnect structures for inputting/outputting electrical signals of the respective devices.
In the multi-die package 20, the structure and function of each die 201 may be the same or different.
The carrier plate 4 is a rigid plate and may comprise a glass plate, a ceramic plate, a metal plate, etc.
An adhesive layer may be disposed between the carrier 4 and the die 201 to fix the carrier and the die. Specifically, a full-surface bonding layer may be coated on the surface of the carrier 4, and the plurality of dies 201 are disposed on the bonding layer.
The encapsulation may be performed by filling liquid molding compound between the dies 201 and then curing the molding compound at high temperature. As shown in fig. 10, the first molding compound layer 200 in the multi-die package structure 20 has a relatively thick thickness.
In one alternative, as shown in fig. 11, the first molding compound 200 in the multi-die package 20 may be thinned after the molding compound is cured until the back surfaces 201b of the plurality of dies 201 are exposed. The thinned first molding compound layer 200 is denoted as a first molding compound layer 200'.
In still another alternative, as shown in fig. 12, before filling the molding compound, a sealing layer 202 is further formed on the back surface 201b of the die 201 and the surface of the carrier 4 between the die 201. It is understood that the larger the number of the dies 201 packaged at a time, the larger the planar size of the multi-die package structure 20, the larger the displacement of the dies 201 caused by the shrinkage of the molding compound, and the position of each die 201 on the carrier 4 fixed by the sealing layer 202 can avoid the displacement problem.
The sealing layer 202 may be formed by spraying (spraying), printing (printing), Coating (Coating), or the like, using a polymer insulating material liquid or paste.
In another alternative, as shown in fig. 13, the first molding layer 200 includes an inner surface embedding the plurality of crystal grains 201 and an outer surface opposite to the inner surface, and a support plate 5 is further provided on the outer surface of the first molding layer 200. The supporting board 5 may support the multi-die package 20 formed with the first molding compound layer 200 in a subsequent process.
The support plate 5 is a hard plate member and may include a glass plate, a ceramic plate, a metal plate, and the like.
The following steps will be described by taking the structure in fig. 13 as an example. It is understood that the subsequent steps are also applicable to the structures in fig. 11 and 12.
In step S12 and as shown in fig. 8, the carrier 4 is removed to expose the front surface 201a of each die 201 in the multi-die package 20.
The removal method of the carrier plate 4 may be an existing removal method such as laser lift-off.
Thereafter, referring to step S2 in fig. 7 and fig. 14 to 20, the outer leads 21 are formed on the front surface 201a of each die 201 in the multi-die package 20.
In an alternative, the rewiring layer 22 and the fan-out lines 23 are sequentially formed on the front surface 201a of each die 201 in the multi-die package 20, and the outer leads 21 are formed on the fan-out lines 23.
For clarity of the manufacturing process of the redistribution layer 22, the fan-out line 23 and the outer lead 21, the P region in fig. 8 is taken as an example. In other words, the process steps for simultaneously fabricating the redistribution layer 22, the fan-out line 23 and the outer leads 21 will be described by taking two dies 201 as an example.
In one alternative, step S21 of forming rewiring layer 22 includes steps S210-S213.
Step S210: referring to fig. 14, a photoresist layer 24 is formed on the exposed front surface 201a of each die 201 and the first molding compound layer 200.
In this step S210, in an alternative, the photoresist layer 24 may be a photosensitive film. The photosensitive film may be peeled off from the adhesive tape and applied on the front surface 201a of each die 201 and the first molding layer 200. In other alternatives, the photoresist layer 24 may be cured by first applying a liquid photoresist and then heating.
Step S211: still referring to fig. 14, the photoresist layer 24 is exposed and developed to remove the photoresist layer 24 in a first predetermined area a corresponding to a pad 2010 on the die front side 201a, the pad 2010 being electrically connected to the electrical interconnect structure.
It should be noted that the correspondence between the pads 2010 of the die front surface 201a and the first predetermined area a may be to expose all or part of the pads 2010, in other words, the area of the first predetermined area a may be larger than the area of all or part of the pads 2010.
This step S211 patterns the photoresist layer 24. In other alternatives, other sacrificial materials that are easily removable may be used in place of the photoresist layer 24.
Step S212: continuing to refer to fig. 14, the first predetermined area a is filled with a metal layer to form a re-wiring layer 22.
In an alternative, the step S212 is performed by an electroplating process. The process of electroplating copper or aluminum is mature. A Seed Layer may also be electroplated prior to electroplating the copper or aluminum. In other alternatives, the metal layer on the photoresist layer 24 may be removed after the entire metal layer is deposited by physical vapor deposition or chemical vapor deposition.
Step S213: referring to fig. 15, ashing removes the remaining photoresist layer 24.
Ashing removes the remaining photoresist layer 24, which reduces the overall thickness of the final chip package structure.
Note that the redistribution layer 22 in step S21 is arranged as required by design, and the distribution of the redistribution layer 22 on each die 201 may be the same or different.
Step S22 of forming fan-out lines 23 on rewiring layer 22 may include steps S220-S225.
Step S220: referring to fig. 16, a third molding layer 25 is formed on the first molding layer 200 and the rewiring layer 22.
In one alternative, the third molding layer 25 may be formed using a compression molding method (ABF). The film pressing method comprises the following steps: firstly, sticking semi-solid plastic package films on the first plastic package layer 200 and the rewiring layer 22; and (3) closing the hot-pressing mould, changing the semi-solid plastic package film into a liquid plastic package material, and continuously heating the plastic package material after the semi-solid plastic package film fully flows to change the plastic package material from the liquid state into a solid third plastic package layer 25. In other alternatives, the third molding layer 25 may be formed by the same process as the first molding layer 200, i.e., by an injection molding process.
Step S221: still referring to fig. 16, a partial region of the third molding layer 25 is removed to form a via hole 26, and the via hole 26 exposes the rewiring layer 22.
The through-hole 26 may be formed by a conventional process such as laser cutting.
In the specific implementation process, a plurality of through holes 26 may be formed in one redistribution layer 22, so as to meet the requirement of a large current for the die 201, and also reduce the self-resistance of a single conductive plug (formed by the metal filled in the through hole 26).
Step S222: referring to fig. 16 and 17, a photoresist layer 27 is formed on the third molding layer 25 inside the through hole 26 and outside the through hole 26.
In this step S222, in an alternative, the photoresist layer 27 may be formed as a photosensitive film. The photosensitive film may be peeled off from the adhesive tape and applied to the third molding layer 25. In other alternatives, the photoresist layer 27 may be cured by first applying a liquid photoresist and then heating.
Step S223: still referring to fig. 17, the exposure develops the photoresist layer 27 leaving the photoresist layer 27 in the second predetermined area B. The second predetermined region B is complementary to a region where the fan-out line 23 is to be formed.
This step S223 patterns the photoresist layer 27. In other alternatives, other sacrificial materials that are easily removable may be used in place of the photoresist layer 27.
Step S224: still referring to fig. 17, complementary regions of the second predetermined region B are filled with a metal layer to form fan-out lines 23.
In an alternative, step S224 is performed by an electroplating process. The process of electroplating copper or aluminum is relatively mature. A Seed Layer may also be electroplated prior to electroplating the copper or aluminum. In other alternatives, the metal layer on the photoresist layer 27 may be removed after the entire metal layer is deposited by physical vapor deposition or chemical vapor deposition.
Step S225: referring to fig. 18, ashing removes the photoresist layer 27 remaining in the second predetermined region B.
Ashing removes the patterned photoresist layer 27, which reduces the overall thickness of the final chip package structure.
It should be noted that the fan-out lines 23 in step S22 are arranged according to design requirements, and the distribution of the fan-out lines 23 on each die 201 may be the same or different.
After that, the outer leads 21 are formed on the fan-out lines 23. Specifically, the present step S23 may include steps S230-S233.
Step S230: referring to fig. 19, a photoresist layer 28 is formed on the fan-out line 23 and the third molding layer 25.
In this step S230, in an alternative, the photoresist layer 28 may be formed as a photosensitive film. The photosensitive film can be peeled off from the adhesive tape and applied on the fan-out lines 23 and the third molding layer 25. In other alternatives, the photoresist layer 28 may be cured by first applying a liquid photoresist and then heating.
Step S231: still referring to fig. 19, the exposure develops the photoresist layer 28 to leave the photoresist 28 in the third predetermined area C. The third predetermined region C is complementary to the region where the outer leads 21 are to be formed.
The photoresist layer 28 is patterned in step S231. In other alternatives, other sacrificial materials that are easily removable may be used in place of the photoresist layer 28.
Step S232: continuing to refer to fig. 19, the complementary region of the third predetermined region C is filled with a metal layer to form the outer lead 21.
In an alternative, step S232 is performed by an electroplating process. The process of electroplating copper or aluminum is mature. A Seed Layer may also be electroplated prior to electroplating the copper or aluminum. Alternatively, the metal layer on the photoresist layer 28 may be removed after the entire metal layer is deposited by physical vapor deposition or chemical vapor deposition.
Step S233: referring to fig. 20, ashing removes the photoresist layer 28 remaining in the third predetermined region C.
It should be noted that the fan-out lines 23 and rewiring layer 22 enable the narrow spacing between the die face pads 2010 to be expanded to a larger spacing between the outer leads 21. In a specific implementation process, the manufacturing step S22 of the fan-out line 23 may also be omitted, and the outer pins 21 are directly manufactured on the rewiring layer 22; alternatively, the step S21 of fabricating the redistribution layer 22 and the step S22 of fabricating the fan-out line 23 are omitted, and the outer leads 21 are directly fabricated on the pads 2010 on the front surface 201a of the die.
Next, referring to step S3 in fig. 7 and fig. 21, the multi-die package 20 is divided into a plurality of regions Q, each region Q including a plurality of dies 201; referring to fig. 22 to 29, a second molding compound 29 embedding the outer leads 21 is formed on the multi-die package 20, and in the second molding compound 29 forming step, the second molding compound 29 between adjacent regions Q is isolated during curing.
In fig. 21, the multi-die package 21 is divided into four regions Q, but in other alternatives, other numbers of regions Q may be divided.
Referring to fig. 21, the areas of the regions Q are preferably equal to ensure that the shrinkage of the second molding layer 29 in the regions Q is equal during curing, so as to avoid warpage of the multi-chip package structure. Further, the number of the crystal grains 201 in each area Q is also preferably equal, and the specific number may be one or more. It is understood that the greater the number of dies 201 per area Q, the higher the packaging efficiency, but the more the shrinkage stress is accumulated when the second molding layer 29 is cured, the greater the occurrence of warpage.
Fig. 22 is a top view of a multi-die package with a plastic film attached; fig. 23 is a cross-sectional view taken along line BB in fig. 22. Fig. 24 is a schematic view of the structure of the mold. Fig. 25 is a schematic structural view of the mold film in fig. 23 when cured.
Referring to fig. 24, the mold 6 includes an upper mold body 61 and a lower mold body 62, and the upper mold body 61 and the lower mold body 62 are combined to form a mold cavity.
In an alternative, as shown in fig. 22 and 23, the present step S3 attaches the plastic film 29' only in each region Q. Referring to fig. 25, the multi-die package 20 with the plastic film 29' is placed on the lower mold 62 and joined to the high temperature upper mold 61; when the upper mold body 61 hot presses the plastic package film 29', the semi-solid plastic package film 29' becomes a liquid plastic package material, and after flowing, the semi-solid plastic package film is continuously heated, and the plastic package material is changed into a solid second plastic package layer 29 from the liquid state; the mould 6 is removed. In other words, the plastic package films 29 'mounted in the regions Q are separated, so that the plastic package films 29' are heated to become liquid plastic package materials, and the plastic package materials in the adjacent regions Q are separated and disconnected in the process of further heating the plastic package materials to be cured to form the second plastic package layer 29.
The second molding compound 29 is isolated during the curing process, so that the shrinkage stress is not greatly accumulated. The verification experiment is carried out, the warpage value of the multi-grain packaging structure 20 is 6-8 mm after the second plastic packaging layer 29 is subjected to plastic packaging by a whole block, and the warpage value can be reduced to be less than 1mm after four areas are subjected to plastic packaging.
Fig. 26 is a top view of a multi-die package provided with a stop block; fig. 27 is a cross-sectional view taken along line CC in fig. 26 after the second molding layer is cured. In another alternative, as shown in fig. 26, this step S3 provides a stopper 30 between adjacent regions Q. Then hot pressing by adopting a high-temperature upper die body 61; referring to fig. 27, after the semi-solid plastic film 29' is changed into a liquid plastic package material and flows, the plastic package material is continuously heated to change the liquid plastic package material into a solid second plastic package layer 29. Or injecting normal temperature liquid plastic package material into the high temperature mould cavity, wherein the normal temperature liquid plastic package material flows and is changed into the solid second plastic package layer 29 from the liquid state due to heating. The stop block 30 can limit the liquid molding compound in one region Q from flowing to another region Q, thereby separating the liquid molding compound and preventing the shrinkage stress in the curing process from being greatly accumulated.
The height of the second molding layer 29 may be less than or equal to the height of the stopper 30.
The material of the stop block 30 can be selected to have the same thermal expansion coefficient or close to that of the second molding layer 29.
In the region Q located at the edge, the liquid molding compound in the region Q is restricted from flowing in the region Q by the stopper 30 and the side wall of the mold.
The stops 30 extending in the same direction may be connected to extend from one side of the multi-die package 20 to the opposite side.
In FIG. 26, the stops 30 extending in different directions are perpendicular to each other, and in other alternatives, the included angle between the stops 30 extending in different directions may be an acute angle.
Fig. 28 is a top view of a multi-die package provided with a mold frame; fig. 29 is a cross-sectional view taken along line DD in fig. 28 after the second molding layer is cured. In still another alternative, referring to fig. 28, the present step S3 sets a mold frame 31 surrounding each region Q. Referring to fig. 29, the mold frame 31 can confine the liquid molding compound in the area Q to the area Q and prevent the liquid molding compound from flowing to the other area Q, thereby blocking the second molding layer 29 during the curing process. The shape of the mold 31 of each region Q matches the shape of the region Q, and is not limited to the rectangle in fig. 28.
The height of the second molding layer 29 may be less than or equal to the height of the mold frame 31.
The material of the mold frame 31 may be selected to have the same thermal expansion coefficient or close to that of the second molding layer 29.
The second molding compound 29 can improve electrical insulation between the adjacent outer leads 21 and the fan-out lines 23 with respect to the air gap.
Next, referring to step S4 in fig. 7 and fig. 30 to 32, the second molding layer 29 is ground until the outer leads 21 are exposed, so as to form the multi-chip package structure 2.
The second molding layer 29 may be mechanically ground, for example, by using a grinding wheel.
It can be understood that, in the step of forming the second molding layer 29 in step S3, since the liquid molding compound is partitioned into a plurality of small areas, the shrinkage stress of the liquid molding compound is small when the liquid molding compound is cured, and the formed multi-chip package structure 2 has no warpage problem; in the process of grinding the second plastic package layer 29 to expose the outer leads 21, the grinding amount can be precisely controlled, and the electrical connection performance of the outer leads 21 is reliable.
In an alternative, after the outer leads 21 are exposed, a tin coating may be plated on the outer leads 21; or solder balls may be formed on the outer leads 21 for flip-chip mounting of the chip package structure 2a (see fig. 33).
In this step, after the second molding layer 29 is exposed on the outer leads 21, the supporting plate 5 is removed.
The support plate 5 may be removed by a conventional removal method such as laser lift-off.
Thereafter, referring to step S5 in fig. 7 and fig. 30 to 33, the multi-chip package structure 2 is diced to form a plurality of chip package structures 2 a.
Referring to fig. 30 to 32, in the dicing process of this step, dicing is performed along dicing streets between adjacent chips.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (14)

1. A method for manufacturing a chip packaging structure is characterized by comprising the following steps:
providing a multi-die package structure, wherein the multi-die package structure comprises a first plastic package layer and a plurality of dies embedded in the first plastic package layer, each die comprises a front surface and a back surface, and the front surface is provided with an electrical interconnection structure; the front surface is exposed outside the first plastic package layer;
forming an outer pin on the front surface of each crystal grain in the multi-crystal grain packaging structure;
dividing the multi-die package structure into a plurality of regions, wherein each region comprises a plurality of dies; forming a second plastic package layer embedding the outer pins on the multi-grain packaging structure, wherein in the second plastic package layer forming step, the second plastic package layer between adjacent regions is isolated during curing;
grinding the second plastic packaging layer until the outer pins are exposed to form a multi-chip packaging structure;
cutting the multi-chip packaging structure to form a plurality of chip packaging structures;
in the step of forming the second plastic package layer, the second plastic package layer is formed through a plastic package film which is subjected to hot-pressing mounting, and the second plastic package layer between adjacent regions is separated and disconnected during curing through the plastic package film which is mounted at intervals.
2. The method of claim 1, wherein each region has an equal area.
3. The method of claim 2, wherein the number of dies in each region is equal.
4. The method of manufacturing a chip package according to claim 1, wherein a redistribution layer is formed on a front surface of each die in the multi-die package, and the outer leads are formed on the redistribution layer; or sequentially forming a rewiring layer and a fan-out circuit on the front surface of each crystal grain in the multi-crystal grain packaging structure, wherein the outer pins are formed on the fan-out circuit.
5. The method of manufacturing a chip package structure according to claim 1, wherein the forming of the rewiring layer comprises:
forming a photoresist layer on the front surface of each exposed crystal grain and the first plastic packaging layer;
exposing and developing the photoresist layer, and removing the photoresist layer in a first preset area, wherein the first preset area corresponds to a bonding pad on the front surface of the crystal grain, and the bonding pad is electrically connected with the electrical interconnection structure;
filling a metal layer in the first preset area to form the rewiring layer;
and ashing to remove the residual photoresist layer.
6. The method of manufacturing a chip package structure according to claim 5, wherein forming a fan-out line on the redistribution layer comprises:
forming a third plastic packaging layer on the first plastic packaging layer and the rewiring layer;
removing part of the third plastic packaging layer to form a through hole, wherein the through hole exposes the rewiring layer;
forming a photoresist layer in the through hole and on the third plastic packaging layer outside the through hole;
exposing and developing the photoresist layer to reserve the photoresist layer of a second preset area;
filling a metal layer in a complementary region of the second preset region to form the fan-out line;
and ashing and removing the residual photoresist layer in the second preset area.
7. The method of claim 6, wherein forming an outer lead on the fanout line comprises:
forming a photoresist layer on the fan-out circuit and the third plastic packaging layer;
exposing and developing the photoresist layer to reserve the photoresist of a third preset area;
filling a metal layer in a complementary region of the third predetermined region to form the outer pin;
ashing and removing the residual photoresist layer in the third preset area;
and forming the second plastic package layer on the third preset area and the outer pin.
8. The method for manufacturing the chip package structure according to claim 5, 6 or 7, wherein the filling metal layer is formed by an electroplating process.
9. The method for manufacturing a chip package structure according to claim 5, 6 or 7, wherein the photoresist layer is a photosensitive film.
10. The method of manufacturing a chip package according to claim 1, wherein the method of manufacturing a multi-die package comprises:
providing a plurality of crystal grains and a carrier plate, fixing the front surfaces of the crystal grains on the carrier plate, and forming a first plastic packaging layer embedding the crystal grains on the carrier plate to form the multi-crystal-grain packaging structure;
and removing the carrier plate to expose the front surface of each crystal grain.
11. The method of claim 10, wherein the die formed by dicing the plurality of wafers is carried on a same carrier to form a multi-die package.
12. The method of claim 10 or 11, wherein before removing the carrier, the first molding compound layer of the multi-die package is thinned until the back surfaces of the dies are exposed.
13. The method for manufacturing a chip package structure according to claim 10, wherein before the first molding compound layer is formed, a sealing layer is formed on the back surfaces of the dies and the surface of the carrier between the dies, and the sealing layer is used for preventing the dies from shifting on the carrier when the first molding compound layer is cured.
14. The method of claim 1, wherein the first molding compound includes an inner surface embedding a plurality of dies and an outer surface opposite to the inner surface, and the multi-die package includes a support plate located on the outer surface of the first molding compound, and the support plate is removed after the step of grinding the second molding compound until the outer leads are exposed.
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