CN112103233B - Method for determining wafer breaking position - Google Patents
Method for determining wafer breaking position Download PDFInfo
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- CN112103233B CN112103233B CN202011025214.6A CN202011025214A CN112103233B CN 112103233 B CN112103233 B CN 112103233B CN 202011025214 A CN202011025214 A CN 202011025214A CN 112103233 B CN112103233 B CN 112103233B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/30—Computing systems specially adapted for manufacturing
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The present disclosure provides a method for determining a wafer breaking position, comprising the steps of: s1, setting a first wafer and a template, setting a positioning edge on the first wafer, and respectively setting a positioning edge and a positioning hole on the template; s2, setting a map; s3, placing the first wafer on the marking chart, and making a positioning mark for positioning the subsequent wafer to be broken off in the marking chart; s4, placing the wafer to be broken on a standard chart, positioning the wafer to be broken by using the positioning mark in the step S3, and marking a positioning point on the wafer to be broken; s5, placing the template on the wafer to be broken, enabling the positioning point of the wafer to be broken to coincide with the positioning hole of the template, and further obtaining the wafer breaking position. The method for determining the wafer breaking position is simple to operate, can accurately determine the breaking position of each wafer, and improves the quality of wafer products.
Description
Technical Field
The present disclosure relates to the field of semiconductor substrate manufacturing, and more particularly, to a method for determining a wafer breaking position.
Background
Gallium arsenide is used as an important III-V group direct band gap compound semiconductor material, and is widely applied in the fields of microelectronics and photoelectronic devices due to the characteristics of high electron mobility, large forbidden bandwidth, low power consumption and the like. Gallium arsenide has shown great development potential in the aspects of microwave devices and light-emitting devices, and in particular, gallium arsenide is still a mainstream substrate material in the fields of red light LEDs and LD devices at present.
During processing, for various reasons (e.g., customer specific requirements for locating edges; defective large-size wafer/crystal reworking small-size wafer … …) it is necessary to rework the wafer using the wafer breaking method, and in some cases it is necessary to determine the pass area based on the wafer defect, in which case it is necessary to determine the pass area of the wafer using the ingot head and tail pieces and mark it on other wafers. If each wafer is to be ensured to be qualified, the breaking position of each wafer needs to be accurately determined.
Disclosure of Invention
In view of the needs of wafer processing, an object of the present disclosure is to provide a method of determining a wafer breaking position, which can accurately determine a breaking position of each wafer.
In some embodiments, the present disclosure provides a method of determining a wafer breaking position, comprising the steps of: s1: setting a first wafer and a template, setting a positioning edge on the first wafer, setting a positioning edge and a positioning hole on the template, and marking a wafer breaking area and a wafer breaking center on the first wafer by using the template; s2: setting a standard chart, wherein the length and the width of the standard chart are larger than the diameter of a wafer to be broken off, and the minimum scale in the standard chart is 1mm; s3: placing a first wafer on a mark F, positioning the first wafer by using a positioning edge on the first wafer, making a positioning mark for positioning a subsequent wafer to be broken off by using a breaking-off center in the mark graph, and taking the first wafer off the mark graph; s4: positioning the wafer to be broken off by utilizing the positioning mark in the step S3, and marking positioning points on the wafer to be broken off; s5: and placing the template on the wafer to be broken, positioning the wafer by a positioning edge on the template, and simultaneously enabling a positioning point of the wafer to be broken to coincide with a positioning hole of the template, marking a wafer to be broken area along the edge of the template, so as to obtain the wafer breaking position.
In some embodiments, the first wafer and the wafer to be broken are the same in size, the breaking area of the first wafer and the breaking area of the first wafer are the same in size, and the template and the breaking area of the first wafer are the same in size.
In some embodiments, in step S1, the first wafer has a first locating edge and a second locating edge thereon, and the template has a third locating edge and a fourth locating edge thereon; a round hole is dug in the center of the template to be used as a positioning hole.
In some embodiments, in step S3, the first positioning edge coincides with the first coordinate axis of the map, and the second positioning edge coincides with the second coordinate axis, so as to complete positioning of the first wafer.
In some embodiments, in step S3, a first parallel line parallel to the first coordinate axis is drawn through the breaking center; drawing a second parallel line parallel to the second coordinate axis through the breaking center; the first parallel lines extend to the standard diagram to obtain a first extension line and a second extension line; the second parallel line extends to the map to obtain a third extension line and a fourth extension line.
In some embodiments, in step S4, the fifth positioning edge of the wafer to be broken is coincident with the first coordinate axis, the sixth positioning edge of the wafer to be broken is coincident with the second coordinate axis, the first extension line and the second extension line are connected to form a line segment, the third extension line and the fourth extension line are connected to form a line segment, and the intersection point of the two line segments is the marking positioning point of the wafer to be broken.
In some embodiments, in step S5, the third positioning edge of the template is parallel to the first coordinate axis, and the round hole of the template coincides with the positioning point, and the area to be broken is marked on the wafer to be broken along the edge of the template by a pen.
In some embodiments, the locating holes in the template are circular holes 1-3mm in diameter.
In some embodiments, the length and width of the map is at least 10mm greater than the diameter of the wafer to be broken
In some embodiments, after the positioning of the first wafer is completed in step 3, the center coordinates of the breaking center are recorded as positioning marks for positioning the subsequent wafer to be broken.
The beneficial effects of the present disclosure are as follows: the method has the advantages that the first wafer 1 provided with the positioning edge and the positioning hole is used, the positioning mark is made by taking the mark diagram F as an auxiliary tool, the wafer 3 to be broken is positioned, the minimum scale in the mark diagram 3 is 1mm, the positioning accuracy is improved, the template 2 and the mark diagram F are utilized to determine the area to be broken of the wafer 3 to be broken, the operation is simple, the breaking position of each wafer can be accurately determined, and the wafer product quality is improved.
Drawings
Fig. 1 is a schematic view of a first wafer according to the present disclosure.
Fig. 2 is a schematic diagram of a template according to the present disclosure.
Fig. 3 is a schematic view of a first wafer from which a breaking-off region and a breaking-off center are made according to the present disclosure.
Fig. 4 is a schematic view of a wafer to be broken according to the present disclosure.
Fig. 5 is a schematic diagram of a map according to the present disclosure.
Fig. 6 is a schematic diagram of making positioning marks according to the present disclosure.
Fig. 7 is a schematic view of a wafer to be broken off according to the present disclosure placed on a standard chart.
Fig. 8 is a schematic diagram of determining anchor points on a wafer to be broken according to the present disclosure.
Fig. 9 is a schematic diagram of determining a wafer breaking position according to the present disclosure.
Fig. 10 is a schematic view of a wafer to be broken after determining a wafer breaking position according to the present disclosure.
Wherein reference numerals are as follows:
1 first wafer
11 first positioning edge
12 second positioning edge
B1 breaking-off region
C1 breaking-off center
2 templates
21 third locating edge
22 fourth locating edge
C2 round hole
3 wafer to be broken off
31 fifth locating edge
32 sixth locating edge
B2 area to be broken
F label graph
A1 first coordinate axis
A2 second coordinate axis
L1 first parallel lines
L2 second parallel line
L11 first extension line
L12 second extension line
L21 third extension line
L22 fourth extension line
P setpoint
Detailed Description
The drawings illustrate embodiments of the present disclosure, and it is to be understood that the disclosed embodiments are merely examples of the disclosure that may be embodied in various forms and that, therefore, specific details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously practice the disclosure.
In the description of the present disclosure, unless otherwise indicated, the terms "first," "second," and the like are used for descriptive and component identification purposes only and are not to be construed as being of relative importance and in relation to each other.
Before breaking, firstly, selecting a crystal bar meeting the requirement of a customer, referring to fig. 1 and 2, cutting a head wafer or a tail wafer of the selected crystal bar as a first wafer 1, and additionally, setting a template 2 with the same size as a target wafer, namely, a region B2 to be broken, wherein in an embodiment, the first wafer 1 is a four-inch wafer, the target wafer is a three-inch wafer, the size of the template 2 is three inches, and the template 2 can be made of plastics, quartz or the like.
After the first wafer 1 and the template 2 are arranged, slicing the crystal bar to obtain a plurality of wafers 3 to be broken off, and determining the position of breaking off the wafer, wherein whether the accuracy of the position of breaking off the wafer is a key for influencing the quality of the wafer.
A method of determining a wafer breaking position according to the present disclosure will be described in detail with reference to the accompanying drawings.
The method for determining the wafer breaking position according to the present disclosure includes the steps of: s1, arranging a first wafer 1 and a template 2, arranging a positioning edge on the first wafer 1, arranging a positioning edge and a positioning hole on the template 2, and marking a breaking area B1 and a breaking center C1 on the first wafer by using the template 2; s2, setting a marking chart F, wherein the length and the width in the marking chart F are both larger than the diameter of the wafer 3 to be broken, and the minimum scale in the marking chart F is 1mm; s3, placing the first wafer 1 on the marking chart F, positioning the first wafer 1 by using a positioning edge on the first wafer 1, making a positioning mark for positioning the subsequent wafer 3 to be broken off on the marking chart F by using the breaking-off center C1, and taking the first wafer 1 off the marking chart F; s4, placing the wafer 3 to be broken on the marking chart F, positioning the wafer 3 to be broken by using the positioning mark in the step S3, and marking positioning points on the wafer 3 to be broken; s5, placing the template 2 on the wafer 3 to be broken, positioning through the positioning edge on the template 2, enabling the positioning point of the wafer 3 to be broken to coincide with the positioning hole of the template 2, and marking the wafer 3 to be broken out of the wafer area B2 along the edge of the template 2 to obtain the wafer breaking position.
The first wafer 1 provided with the positioning edge and the template 2 provided with the positioning edge and the positioning hole are used, the marking chart F is used as an auxiliary tool for making positioning marks for positioning the wafer 3 to be broken, the minimum scale in the marking chart 3 is 1mm, positioning accuracy is improved, the template 2 and the marking chart F are used for determining the area B2 to be broken of the wafer 3 to be broken, operation is simple, meanwhile, the breaking position of each wafer can be accurately determined, and wafer product quality is improved.
In step S1, referring to fig. 1 and 4, the first wafer 1 and the wafer 3 to be broken are sliced from the same ingot, so that the first wafer 1 and the wafer 3 to be broken have the same size, and at the same time, the template 2 and the target wafer, that is, the area B2 to be broken have the same size, and referring to fig. 3, the area B1 to be broken on the first wafer 1 determined by the template 2 has the same size as the area B2 to be broken.
In step S1, referring to fig. 1 and 3, a first positioning edge 11 and a second positioning edge 12 are provided on a first wafer 1, a third positioning edge 21 and a fourth positioning edge 22 are provided on a template 2, a circular hole C2 is dug in the center of the template 2 as a positioning hole, the template 2 is placed in a qualified area on the first wafer 1, a piece breaking area B1 is marked on the first wafer 1 along the edge of the template 2 by a pen, a piece breaking center C1 is marked on the first wafer 1 through the circular hole C2 on the template 2, and the positioning hole C2 is a circular hole with a diameter of 1-3 mm. The positioning edge is used for positioning the first wafer 1 and the template 2 and determining the breaking position subsequently, so that the positioning accuracy is improved, the size of the positioning hole is small, and the accuracy of the breaking position of each wafer is improved.
In step 2, referring to fig. 5 and 6, the length and width of the index drawing F are at least 10mm larger than the diameter of the wafer 3 to be broken, so that the operation is convenient and the positioning mark is convenient.
In step 3, there are two methods for making a positioning mark in the map F, one is a line drawing method: referring to fig. 6, first, the first positioning edge 11 is overlapped with the first coordinate axis A1 of the labeling diagram F, and the second positioning edge 12 is overlapped with the second coordinate axis A2, so as to complete the positioning of the first wafer 1; then, drawing a first parallel line L1 parallel to the first coordinate axis A1 through the breaking center C1; thirdly, drawing a second parallel line L2 parallel to the second coordinate axis A2 through the breaking center C1; finally, the first parallel line L1 extends to the indication chart F to obtain a first extension line L11 and a second extension line L12, and the second parallel line L2 extends to the indication chart F to obtain a third extension line L21 and a fourth extension line L22, and referring to fig. 7, the first extension line L11, the second extension line L12, the third extension line L21 and the fourth extension line L22 can be used as positioning marks for positioning the wafer 3 to be broken later. The other is a coordinate method: first, the first positioning edge 11 is overlapped with the first coordinate axis A1 of the mark graph F, and the second positioning edge 12 is overlapped with the second coordinate axis A2, so as to finish the positioning of the first wafer 1; after the positioning of the first wafer 1 is completed, the coordinates of the breaking center C1 in the index chart F are recorded as positioning marks for the positioning of the subsequent wafer 3 to be broken.
In step S4, the process of marking the positioning points on the wafer to be broken 3 by using the positioning marks made by the scribing method is as follows: referring to fig. 7 and 8, the fifth positioning edge 31 of the wafer 3 to be broken is overlapped with the first coordinate axis A1, the sixth positioning edge 32 of the wafer 3 to be broken is overlapped with the second coordinate axis A2, the first extension line L11 and the second extension line L12 are connected into a line segment, the third extension line L21 and the fourth extension line L22 are connected into a line segment, and the intersection point of the two line segments is the marking positioning point P of the wafer 3 to be broken. The process of marking the positioning points on the wafer 3 to be broken by using the positioning marks made by the coordinate method is as follows: the fifth positioning edge 31 of the wafer 3 to be broken is overlapped with the first coordinate axis A1, the sixth positioning edge 31 of the wafer 3 to be broken is overlapped with the second coordinate axis A2, the coordinate position recorded in the step 3 is marked on the wafer 3 to be broken, and the coordinate position is used as a mark positioning point P of the wafer 3 to be broken.
In step S5, referring to fig. 9 and 10, the third positioning edge 21 of the template 2 is parallel to the first coordinate axis A1, and the round hole C2 of the template 2 is overlapped with the positioning point P, and the area B2 to be broken is marked on the wafer 3 to be broken along the edge of the template 2 by a pen.
After the wafer breaking position is determined by the method, the wafer breaking process can be performed along the position. According to the method for determining the wafer breaking position, the uniformity and the accuracy of the wafer breaking position can be greatly improved, the product quality of the wafer is improved, and bad product flowing to a client is prevented.
The above detailed description describes various exemplary embodiments, but is not intended to be limited to the combinations explicitly disclosed herein. Thus, unless otherwise indicated, the various features disclosed herein may be combined together to form a number of additional combinations that are not shown for the sake of brevity.
Claims (8)
1. A method for determining the breaking position of a wafer, comprising the steps of:
s1: setting a first wafer (1) and a template (2), setting a positioning edge on the first wafer (1), setting a positioning edge and a positioning hole on the template (2), and marking a piece breaking area (B1) and a piece breaking center (C1) on the first wafer (1) by using the template (2);
s2: setting a marking chart (F) so that the length and the width in the marking chart (F) are both larger than the diameter of the wafer (3) to be broken, and the minimum scale in the marking chart (F) is 1mm;
s3: the method comprises the steps of placing a first wafer (1) on a marking chart (F), positioning the first wafer (1) by using a positioning edge on the first wafer (1), making a positioning mark for positioning a subsequent wafer (3) to be broken off on the marking chart (F) by using a breaking-off center (C1), and taking the first wafer (1) off from the marking chart (F);
s4: positioning the wafer (3) to be broken by utilizing the positioning mark in the step S3 on the marking chart (F), and marking positioning points on the wafer (3) to be broken;
s5: placing a template (2) on a wafer (3) to be broken, positioning the template (2) through a positioning edge on the template (2), and simultaneously enabling positioning points of the wafer (3) to be broken to coincide with positioning holes of the template (2), marking a wafer breaking area (B2) to be broken along the edge of the template (2) on the wafer (3) to be broken to obtain a wafer breaking position;
the size of the first wafer (1) is the same as that of the wafer (3) to be broken, the size of a breaking area (B1) of the first wafer (1) is the same as that of a breaking area (B2), and the size of the template (2) is the same as that of the breaking area (B2);
in the step S1, a first positioning edge (11) and a second positioning edge (12) are arranged on a first wafer (1), and a third positioning edge (21) and a fourth positioning edge (22) are arranged on a template (2);
a round hole (C2) is dug in the center of the template (2) and is used as a positioning hole.
2. The method for determining a wafer breaking position according to claim 1, wherein in step S3, the first positioning edge (11) coincides with the first coordinate axis (A1) of the map (F), and the second positioning edge (12) coincides with the second coordinate axis (A2), so as to complete the positioning of the first wafer (1).
3. The method of determining a breaking position of a wafer according to claim 2, wherein in step S3, a first parallel line (L1) parallel to the first coordinate axis (A1) is drawn through the breaking center (C1); drawing a second parallel line (L2) parallel to the second coordinate axis (A2) through the breaking center (C1); the first parallel line (L1) extends to the marking chart (F) to obtain a first extension line (L11) and a second extension line (L12); the second parallel line (L2) extends onto the map (F) to obtain a third extension line (L21) and a fourth extension line (L22).
4. A method for determining a wafer breaking position according to claim 3, wherein in step S4, a fifth positioning edge (31) of the wafer (3) to be broken is overlapped with the first coordinate axis (A1), a sixth positioning edge (32) of the wafer (3) to be broken is overlapped with the second coordinate axis (A2), the first extension line (L11) and the second extension line (L12) are connected to form a line segment, and simultaneously the third extension line (L21) and the fourth extension line (L22) are connected to form a line segment, and an intersection point of the two line segments is the positioning point (P) marked by the wafer (3) to be broken.
5. The method for determining a wafer breaking position according to claim 4, wherein in step S5, the third positioning edge (21) of the template (2) is parallel to the first coordinate axis (A1), and the round hole (C2) of the template (2) is overlapped with the positioning point (P), and the area (B2) to be broken is marked on the wafer (3) to be broken along the edge of the template (2) by a pen.
6. The method for determining the breaking position of a wafer according to claim 1, wherein the positioning hole on the template (2) is a circular hole (C2) with a diameter of 1-3 mm.
7. Method for determining the breaking position of wafers according to claim 1, characterized in that the length and width of the map (F) are at least 10mm greater than the diameter of the wafer (3) to be broken.
8. The method of determining a wafer breaking position according to claim 2, characterized in that after the positioning of the first wafer (1) is completed in step 3, coordinates of the breaking center (C1) are recorded as positioning marks for the positioning of the subsequent wafer (3) to be broken.
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| CN202011025214.6A CN112103233B (en) | 2020-09-25 | 2020-09-25 | Method for determining wafer breaking position |
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| CN202011025214.6A CN112103233B (en) | 2020-09-25 | 2020-09-25 | Method for determining wafer breaking position |
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| CN112103233B true CN112103233B (en) | 2023-08-22 |
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| EP0580895A2 (en) * | 1992-07-24 | 1994-02-02 | Fujitsu Limited | Method of mapping a tested semiconductor device |
| CN101128928A (en) * | 2005-02-22 | 2008-02-20 | Oc欧瑞康巴尔斯公司 | Method for positioning a wafer |
| CN201089195Y (en) * | 2007-08-31 | 2008-07-23 | 中芯国际集成电路制造(上海)有限公司 | Auxiliary appliance for sheet severing |
| CN104779191A (en) * | 2014-01-10 | 2015-07-15 | 株式会社迪思科 | Mark detecting method |
| CN108975671A (en) * | 2018-10-12 | 2018-12-11 | 广东工业大学 | A kind of dual robot glass breaks piece work planning method and system |
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2020
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0580895A2 (en) * | 1992-07-24 | 1994-02-02 | Fujitsu Limited | Method of mapping a tested semiconductor device |
| CN101128928A (en) * | 2005-02-22 | 2008-02-20 | Oc欧瑞康巴尔斯公司 | Method for positioning a wafer |
| CN201089195Y (en) * | 2007-08-31 | 2008-07-23 | 中芯国际集成电路制造(上海)有限公司 | Auxiliary appliance for sheet severing |
| CN104779191A (en) * | 2014-01-10 | 2015-07-15 | 株式会社迪思科 | Mark detecting method |
| CN108975671A (en) * | 2018-10-12 | 2018-12-11 | 广东工业大学 | A kind of dual robot glass breaks piece work planning method and system |
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| CN112103233A (en) | 2020-12-18 |
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