CN111799220B - Wafer splitting method and application thereof - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000005336 cracking Methods 0.000 claims abstract description 31
- 238000004458 analytical method Methods 0.000 claims abstract description 19
- 230000007423 decrease Effects 0.000 claims description 2
- 238000010330 laser marking Methods 0.000 claims 1
- 230000003247 decreasing effect Effects 0.000 abstract description 3
- 208000010392 Bone Fractures Diseases 0.000 description 8
- 206010017076 Fracture Diseases 0.000 description 8
- 238000010884 ion-beam technique Methods 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 229910003460 diamond Inorganic materials 0.000 description 3
- 239000010432 diamond Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000003550 marker Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
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- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 208000006670 Multiple fractures Diseases 0.000 description 1
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- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
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Abstract
The invention provides a wafer cracking method and application thereof, wherein the wafer cracking method comprises the following steps: providing a wafer, wherein a crack point is arranged on the wafer; breaking the wafer to obtain a chip comprising the crack point; breaking a crack in the wafer to form a crack in the wafer extending from a location proximate to the crack point to the wafer edge, the crack width decreasing from the wafer edge to the crack point; and splitting the wafer from the crack so that the wafer is split from the crack and passes through the crack to obtain the cross section at the crack. According to the technical scheme, the wafer splitting process is simplified to shorten the splitting time, meanwhile, the precision of the splitting can reach the micron level, and therefore the wafer can be subjected to rapid and effective failure analysis.
Description
Technical Field
The invention relates to the field of integrated circuit manufacturing, in particular to a wafer cracking method and application thereof.
Background
During the development of semiconductor technology or the failure analysis of semiconductor device manufacture, the analysis of the cross-sectional profile of a specific pattern on a wafer is a very common method, and its basic steps include: firstly, a wafer (including a silicon substrate and a film layer and a pattern on the silicon substrate) is cracked along the pattern to be observed to obtain a cross section (cross-section) of the pattern, as shown in fig. 1, the wafer is cracked along an AA' section to obtain the appearance of the cross section, as shown in fig. 2, the internal appearance of a gate 11, a source 12 and a drain 13 formed on a substrate 10 can be obtained; then, the cross section of the figure is magnified by a Scanning Electron Microscope (SEM) or a Transmission Electron Microscope (TEM) to perform observation analysis of the cross section of the figure.
For the step of cracking the wafer along the pattern to be observed, the following two methods are mainly adopted:
the method comprises the following steps: the manual method comprises the steps of manually marking a scratch with a certain depth on a wafer by using a diamond pen, and then utilizing the specific orientation of the wafer to cleave a plane, and splitting along the scratch to obtain a required cross section. The method has the disadvantages that accurate fixed-point splinting cannot be carried out, the precision is very low, and even if an optical microscope is used for assistance, the precision is difficult to be higher than a millimeter level due to the limitation of manual operation precision.
The second method comprises the following steps: a Focused Ion Beam (FIB) precise sampling method mainly uses an electron microscope to observe the position, and uses a focused gallium (Ga) ion beam to cut a sample wafer so as to obtain a required cross section. The method has the defects of complex equipment, complex structures such as a special ion generator, an ion positioning system and the like, relatively high cost, expensive equipment and long sample preparation time, so the method is generally only used for the conditions of high sample sampling precision of a sample wafer such as transmission electron microscope sample preparation and the like.
Therefore, it is desirable to provide a new wafer splitting method and an application thereof, so as to simplify the splitting process and enable the precision of the splitting to reach the micron level, thereby enabling the rapid and effective failure analysis of the wafer.
Disclosure of Invention
The invention aims to provide a wafer cracking method and application thereof, which can simplify the cracking process to shorten the cracking time, and can ensure that the cracking precision reaches the micron level, thereby further quickly and effectively analyzing the failure of the wafer.
In order to achieve the above object, the present invention provides a wafer cracking method, comprising:
providing a wafer, wherein a crack point is arranged on the wafer;
breaking the wafer to obtain a chip comprising the crack point;
breaking a crack in the wafer to form a crack in the wafer extending from a location proximate to the crack point to the wafer edge, the crack width decreasing from the wafer edge to the crack point; and the number of the first and second groups,
and splitting the wafer from the crack so that the wafer is cracked from the crack and passes through the crack to obtain the cross section at the crack.
Optionally, before the wafer is broken, the position of the crack point is marked on the wafer.
Optionally, the step of breaking the wafer includes:
determining the position of the crack point on the wafer;
drawing a mark around the split point; and the number of the first and second groups,
and breaking the wafer along the scribing mark.
Optionally, the periphery of the split point is marked by lines respectively, one side of the split point is a close side, and the distance between the edge of the wafer and the split point on the close side is 0.5 mm-1 mm.
Optionally, the step of cracking the wafer includes:
placing the wafer on a laser calibration machine, and setting parameters of the laser calibration machine;
finding the position of the crack point on the laser calibration machine; and the number of the first and second groups,
and on the close side of the fracture point, performing multiple fractures from the position close to the fracture point to the position of the wafer edge to form the fracture, wherein the fracture width is gradually increased from the fracture point to the wafer edge.
Optionally, the step of cracking the wafer further includes: and on the opposite side of the close distance side, cracking from the position close to the cracking point to the edge of the wafer for multiple times, so that the width of the formed crack is gradually increased from the cracking point to the edge of the wafer.
Optionally, the distance between one end of the crack close to the crack point and the crack point is 1-3 times of the length of the primary crack of the laser calibration machine.
Optionally, the step of splitting the wafer from the crack comprises:
providing a thimble;
placing the ejector pin on the close distance side and aligning the split; and the number of the first and second groups,
and applying force to the wafer and the ejector pin so that the wafer is cracked from the crack and passes through the crack point.
The invention also provides an application of the wafer cracking method, which comprises the following steps:
providing a wafer, wherein a crack point is arranged on the wafer, and the crack point is a graph to be subjected to failure analysis;
by adopting the wafer splitting method provided by the invention, the cross section of the graph at the splitting point is obtained; and the number of the first and second groups,
and carrying out failure analysis on the graphical cross section at the crack point.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. the wafer cracking method of the invention forms a crack extending from a position close to the cracking point to the edge of the wafer on the wafer by cracking the wafer obtained after the wafer is cracked, and the width of the crack is gradually reduced from the edge of the wafer to the cracking point; and splitting the wafer from the crack so that the wafer is split from the crack and passes through the split point, so that the accuracy and stability of splitting can be improved while the splitting process is simplified to shorten the splitting time, and the precision of splitting can reach a micron level.
2. Due to the application of the wafer splitting method provided by the invention to obtain the graphic cross section at the splitting point, the wafer can be subjected to rapid and effective failure analysis.
Drawings
FIG. 1 is a schematic top view of a wafer;
FIG. 2 is a cross-sectional view along AA' of the wafer shown in FIG. 1;
FIG. 3 is a flow chart of a wafer breaking method according to an embodiment of the invention;
FIGS. 4-5 are schematic views of devices in the wafer breaking method shown in FIG. 3.
Wherein the reference numerals of figures 1 to 5 are as follows:
10-a substrate; 11-a gate; 12-a source electrode; 13-a drain electrode; 20-a wafer; 21-break point; 22-a wafer; 31-a first split; 32-second break.
Detailed Description
In order to make the objects, advantages and features of the present invention more apparent, the wafer breaking method and the wafer failure analysis method proposed by the present invention are further described in detail below. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
An embodiment of the present invention provides a wafer breaking method, and referring to fig. 3, fig. 3 is a flowchart of the wafer breaking method according to an embodiment of the present invention, where the wafer breaking method includes:
step S1, providing a wafer, wherein the wafer has a crack point;
step S2, breaking the wafer to obtain a chip containing the crack point;
step S3, cracking the wafer to form a crack on the wafer extending from a position near the crack point to the edge of the wafer, wherein the crack width gradually decreases from the edge of the wafer to the crack point;
and step S4, splitting the wafer from the crack, so that the wafer is split from the crack and passes through the crack to obtain the cross section at the crack.
The wafer breaking method is described in detail with reference to fig. 4 and 5. It should be noted that, for the sake of clearly identifying the position of the crack 21 in fig. 4 and 5, the dimensional ratios among the wafer 20, the crack 21 and the chip 22 are all non-precise ratios, and fig. 5 is an enlarged view of the chip 22 in fig. 4 after being rotated counterclockwise.
According to step S1, a wafer having a crack point thereon is provided. The crack point may be a pattern to be subjected to failure analysis, and as shown in fig. 4, the crack point 21 may be a pattern at any position on the wafer 20. The split point can be any pattern for manufacturing a semiconductor device, such as a circle, a rectangle, etc., and the diameter or the side length of the split point can be 1 μm to 1mm (for example, 5 μm, 100 μm, 500 μm, etc.).
According to step S2, the wafer is broken to obtain chips including the crack points.
Before the wafer is broken, the wafer may be placed under an optical microscope to confirm the position of the crack point on the wafer and mark the position of the crack point on the wafer. A marker pen may be used to circle around the break point to enable the break point to be quickly found in subsequent steps.
The step of breaking the wafer comprises: firstly, determining the position of the crack point on the wafer, wherein the position can be determined under an optical microscope; then, marking marks around the split point, wherein the split point may be marked with a short distance around the split point, and one side is a short distance side, as shown in fig. 4, four lines of the marks surround the split point 21 to form a rectangle, the mark on the short distance side of the split point 21 is spaced apart from the split point 21 by a distance D1, the mark on the opposite side of the short distance side is spaced apart from the split point 21 by a distance D2, the distance D1 is smaller than the distance D2, and in order to make the position of the split point 21 close to the edge of the wafer 22 obtained after the breaking, and further facilitate the subsequent breaking of the wafer 22, the smaller the distance D1, the better the distance D1 is, for example, 0.5mm to 1mm (for example, 0.6mm, 0.8mm, etc.), and the distance between two marks connected to the mark on the short distance side is D3, the split point 21 is preferably located at a position midway between the two marks at a distance D3, so that when the wafer 22 is subsequently split by using the ejector pins in step S4, the force is uniformly applied to the wafer 22 on both sides of the split; next, the wafer is broken along the marked line to obtain a chip including the breaking point, as shown in fig. 5, the width of the chip 22 obtained after the breaking is the sum of the distance D1 and the distance D2, and the length is the distance D3, the length and the width of the chip 22 are not limited to specific values, as long as the chip 22 is of a size convenient for the subsequent breaking operation of the chip 22, for example, the chip 22 may have a length of 10mm and a width of 5 mm.
In addition, since the precision requirement for the wafer breaking in step S2 is not high, the wafer may be manually broken by using a diamond pen.
According to step S3, a crack is formed in the wafer to form a crack in the wafer extending from a location near the crack point to the wafer edge, the crack width decreasing from the wafer edge to the crack point.
The step of cracking the wafer comprises: firstly, placing the wafer on a Laser marker (Laser mark), and setting parameters of the Laser marker, wherein the set parameters can include the depth and energy of each fracture, the wavelength of the Laser of the fracture and the like; then, finding the position of the crack point on the laser calibration machine, wherein the position of the crack point can be found by using a high-power microscope on the laser calibration machine, and the length, the width and the levelness of the crack which is shot each time can be adjusted, and the direction of the crack which is shot each time is perpendicular to the edge of the wafer, so as to avoid the crack from being distorted; then, on the close side of the crack, multiple cracks are formed from the position close to the crack to the wafer edge position to form the crack, and the width of the crack gradually increases from the crack to the wafer edge to ensure the accuracy of the subsequent cracking in step S4. As shown in fig. 5, when the short distance side of the crack 21 is cracked at a distance D1 from the edge of the wafer 22, the width of the formed first crack 31 (for distinguishing from the subsequently formed crack at the opposite side of the short distance side, the formed crack is defined as the first crack) gradually increases from the position near the crack 21 to the edge of the wafer 22; and because the distance (i.e. the distance D1) between the crack point 21 and the edge of the wafer 22 is very short, the laser calibration machine has a short crack distance, so that the speed of forming the first crack 31 is increased, and the position of the crack in the subsequent step S4 is more accurate, thereby ensuring that the crack is cracked along the lattice direction. Moreover, the deeper the first split 31 is, the closer to the edge of the wafer 22, the better the force applied by the thimble to the first split 31 in the subsequent step S4, the better the splitting effect.
And the step of cracking the wafer further comprises: and on the opposite side of the close distance side, cracking from the position close to the cracking point to the edge of the wafer for multiple times, so that the width of the formed crack is gradually increased from the cracking point to the edge of the wafer. As shown in fig. 5, a second split 32 (distinguished from the first split 31 described above) is formed by cracking on the opposite side of the close side, i.e., on the side of the split point 21 that is a distance D2 from the edge of the wafer 22, the width of the second split 32 gradually increases from the split point 21 to the edge of the wafer 22, and the length, width and depth of the second split 32 may be smaller than the first split 31; the second split 32 is located on the same straight line as the first split 31, so that when the wafer 22 is split in the subsequent step S4, the wafer 22 can be split from the first split 31 and the second split 32 and pass through the position of the split point 21, and it is ensured that the split position does not shift.
In addition, the distance between one end of the split (including the first split and the second split) close to the split point and the split point can be 1-3 times of the length of one-time split of the laser calibration machine, so that structural damage of the split point caused by the fact that the laser calibration machine punches the split point when the laser calibration machine punches the split point is avoided, and further failure analysis of the graph of the split point is avoided being influenced.
And according to the step S4, splitting the wafer from the crack, so that the wafer is split from the crack and passes through the crack to obtain the cross section at the crack.
The step of breaking the wafer from the fracture comprises: firstly, providing a thimble, and vertically placing the thimble under an optical microscope; then, the wafer is placed above the ejector pin, the position of the split is upward, the ejector pin is placed on the close-distance side and aligned with the split, preferably, the ejector pin is aligned with the position, close to the edge of the wafer, of the split, and due to the fact that the depth and the width of the split at the position are large, force can be applied to the ejector pin conveniently, and the splitting effect is good; then, force is applied to the wafer and the thimble, and the wafer on two sides of the crack can be applied downwards, so that the thimble applies force upwards to the wafer at the crack, and the wafer is cracked from the crack and passes through the crack point, and the cross section at the crack point is obtained. The wafer is split through the steps S1 to S4 to produce a sample to be subjected to failure analysis, and the failure analysis is performed on the graph at the split point, so that the following effects can be achieved:
(1) shorten system appearance time, practice thrift system appearance cost: compared with the method adopting the focused ion beam to prepare samples, the method only needs about 0.5 h;
(2) promote the system appearance success rate, improve the system appearance precision: the sample is prepared by a manual method, the graph of a sample to be analyzed is required to be above the millimeter level, and the sample is manually scratched by a diamond pen under an optical microscope and then split, so that the success rate is low, and the sample preparation cannot be completed for the sample below the millimeter level; the method of the invention adopts the laser calibration machine to crack, so that the size and the position of the crack are very accurate, the width of the formed crack is gradually reduced from the edge of the wafer to the crack point, the accuracy and the stability of the crack can be improved, the crack is ensured to crack along the direction of the crystal lattice during the crack, and the success rate for manufacturing a sample of a micron-sized pattern to be analyzed is very high, for example, more than nine times;
(3) saving sample preparation cost: compared with the method of preparing samples by adopting focused ion beams, the method of the invention greatly saves the cost because the price of a focused ion beam machine is far higher than that of a laser calibration machine.
Based on the same inventive concept, an embodiment of the present invention provides an application of a wafer breaking method, including: firstly, providing a wafer, wherein a crack point is arranged on the wafer, the crack point is a graph to be subjected to failure analysis, the diameter or the side length of the crack point can be 1 mu m-1 mm, and the graph to be subjected to failure analysis is in a micron order; then, by adopting the wafer splitting method provided by the invention, the pattern cross section at the splitting point is obtained, so that the splitting speed can be accelerated, and the accuracy and the stability of splitting are improved; and then, failure analysis is carried out on the cross section of the graph at the crack point, and the failure reason can be quickly analyzed due to the fact that the accuracy of the split is improved.
In summary, the wafer splitting method and the application thereof provided by the invention simplify the splitting process to shorten the splitting time, and simultaneously enable the splitting precision to reach the micron level, thereby enabling the wafer to be subjected to rapid and effective failure analysis.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (6)
1. A wafer cracking method is characterized by comprising the following steps:
providing a wafer, wherein a crack point is arranged on the wafer;
drawing marks around the split points, and breaking the wafer along the drawn marks to obtain chips containing the split points, wherein the drawn line on one side of the split points is marked as a short-distance side;
cracking a near side of the crack on the wafer and an opposite side of the near side to form a first crack on the near side of the crack on the wafer extending from a location near the crack to the wafer edge, and forming a second crack on the opposite side of the near side of the crack on the wafer extending from the location near the crack to the wafer edge, the first and second cracks having widths that gradually decrease from the wafer edge to the crack, and the first and second cracks being located on a same straight line; and the number of the first and second groups,
breaking the wafer from the first and second breaches such that the wafer breaks from the first and second breaches and passes through the break point to obtain a cross-section at the break point;
wherein the step of fracturing a near side of the fracture point and an opposite side of the near side on the wafer comprises:
placing the wafer on a laser calibration machine, and setting parameters of the laser calibration machine;
finding the position of the crack point on the laser calibration machine;
at the near side of the fracture point, fracturing a plurality of times from a location near the fracture point to a location at the edge of the wafer to form the first fracture; and the number of the first and second groups,
and multiple cracks are formed from the position close to the crack point to the edge of the wafer on the opposite side of the close distance side to form the second crack.
2. The wafer breaking method of claim 1, wherein the position of the breaking point is marked on the wafer before the wafer is broken.
3. The wafer splitting method of claim 1, wherein the distance between the edge of the chip at the close side and the splitting point is 0.5mm to 1 mm.
4. The wafer splitting method of claim 3, wherein an end of the first split and the second split close to the split point is spaced from the split point by 1-3 times the length of a single crack of the laser marking machine.
5. The wafer breaking method of claim 3, wherein the step of breaking the chip from the first and second fractures comprises:
providing a thimble;
placing the ejector pin on the close distance side and aligning the ejector pin with the first split; and the number of the first and second groups,
and applying force to the wafer and the thimble to enable the wafer to crack from the first split and the second split and pass through the crack point.
6. The application of the wafer cracking method is characterized by comprising the following steps:
providing a wafer, wherein a crack point is arranged on the wafer, and the crack point is a graph to be subjected to failure analysis;
obtaining a graphical cross section at the crack point by using the wafer cracking method of any one of claims 1 to 5; and the number of the first and second groups,
and carrying out failure analysis on the graphical cross section at the crack point.
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Effective date of registration: 20240321 Address after: 230012 No.88, xifeihe Road, Hefei comprehensive free trade zone, Xinzhan District, Hefei City, Anhui Province Patentee after: Nexchip Semiconductor Corporation Country or region after: China Address before: No.18-h1105, Yinchun Road, science and technology R & D base, Maigaoqiao entrepreneurship Park, Qixia District, Nanjing, Jiangsu Province, 210046 Patentee before: Nanjing crystal drive integrated circuit Co.,Ltd. Country or region before: China |