CN112103233A - Method for determining wafer breaking position - Google Patents
Method for determining wafer breaking position Download PDFInfo
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- CN112103233A CN112103233A CN202011025214.6A CN202011025214A CN112103233A CN 112103233 A CN112103233 A CN 112103233A CN 202011025214 A CN202011025214 A CN 202011025214A CN 112103233 A CN112103233 A CN 112103233A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/30—Computing systems specially adapted for manufacturing
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Abstract
The present disclosure provides a method for determining a wafer breaking position, comprising the following steps: s1, arranging a first wafer and a template, arranging a positioning edge on the first wafer, and arranging a positioning edge and a positioning hole on the template respectively; s2, setting a mark picture; s3, placing the first wafer on the marked picture, and making a positioning mark for positioning the subsequent wafer to be broken on the marked picture; s4, placing the wafer to be broken on the map, positioning the wafer to be broken by using the positioning marks in step S3, and marking positioning points on the wafer to be broken; s5, the template is placed on the wafer to be broken, so that the positioning points of the wafer to be broken coincide with the positioning holes of the template, and the wafer breaking position is obtained. The method for determining the wafer breaking position is simple to operate, the breaking position of each wafer can be accurately determined, and the quality of a wafer product is improved.
Description
Technical Field
The disclosure relates to the field of semiconductor substrate manufacturing, and in particular, to a method for determining wafer breaking position.
Background
Gallium arsenide is an important III-V group direct band gap compound semiconductor material, and is widely applied to the fields of microelectronics and photoelectronic devices due to the characteristics of high electron mobility, large forbidden band width, low power consumption and the like. Gallium arsenide has great development potential in the aspects of microwave devices and light emitting devices, and particularly in the field of red light LEDs and LD devices at present, gallium arsenide is still the mainstream substrate material.
During the processing, the wafer needs to be modified by using the breaking-off method for various reasons (such as special requirements of customers on positioning edges; defective large-size wafer/crystal modification processing small-size wafer … …), and in some cases, qualified regions need to be determined according to wafer defects, in which case, the qualified regions of the wafers need to be determined by using the head and tail of the crystal bar and marked on other wafers. If each wafer is to be qualified, the wafer breaking position of each wafer needs to be accurately determined.
Disclosure of Invention
In view of the need of the wafer processing process, an object of the present disclosure is to provide a method for determining wafer breaking positions, which can accurately determine the breaking positions of each wafer.
In some embodiments, the present disclosure provides a method for determining wafer breaking position, comprising the steps of: s1: arranging a first wafer and a template, arranging a positioning edge on the first wafer, arranging a positioning edge and a positioning hole on the template, and marking a sheet breaking area and a breaking center on the first wafer by using the template; s2: setting a marking picture, wherein the length and the width of the marking picture are larger than the diameter of the wafer to be broken, and the minimum scale in the marking picture is 1 mm; s3: placing the first wafer on the mark F, positioning the first wafer by utilizing the positioning edge on the first wafer, making a positioning mark for positioning the subsequent wafer to be subjected to the breaking-off in the mark diagram by utilizing the breaking-off center, and taking the first wafer down from the mark diagram; s4: positioning the wafer to be broken on the marking map by using the positioning mark in the step S3, and marking a positioning point on the wafer to be broken; s5: and placing the template on the wafer to be broken, positioning the wafer through the positioning edge on the template, simultaneously enabling the positioning point of the wafer to be broken to be superposed with the positioning hole of the template, and marking the region of the wafer to be broken on the wafer to be broken along the edge of the template to obtain the wafer breaking position.
In some embodiments, the first wafer has the same size as the wafer to be broken, the breaking region of the first wafer has the same size as the region to be broken, and the template has the same size as the region to be broken.
In some embodiments, in step S1, the first wafer has a first positioning edge and a second positioning edge thereon, and the template has a third positioning edge and a fourth positioning edge thereon; a round hole is dug in the center of the template to serve as a positioning hole.
In some embodiments, in step S3, the first positioning edge coincides with the first coordinate axis of the plot and the second positioning edge coincides with the second coordinate axis, completing the positioning of the first wafer.
In some embodiments, in step S3, a first parallel line is drawn through the breaking center in parallel with the first coordinate axis; drawing a second parallel line parallel to the second coordinate axis through the breaking center; the first parallel line extends to the marking diagram to obtain a first extension line and a second extension line; the second parallel line extends to the marking picture to obtain a third extension line and a fourth extension line.
In some embodiments, in step S4, the fifth positioning edge of the wafer to be broken coincides with the first coordinate axis, the sixth positioning edge of the wafer to be broken coincides with the second coordinate axis, the first extension line and the second extension line are connected to form a line segment, the third extension line and the fourth extension line are connected to form a line segment, and the intersection point of the two line segments is the positioning point for marking the wafer to be broken.
In some embodiments, in step S5, the third positioning edge of the template is parallel to the first coordinate axis, the circular hole of the template is overlapped with the positioning point, and the to-be-broken area is marked on the to-be-broken wafer along the edge of the template by a pen.
In some embodiments, the locating holes on the template are circular holes with a diameter of 1-3 mm.
In some embodiments, the length and width of the indicia views are at least 10mm greater than the diameter of the wafer to be broken
In some embodiments, in step 3, after the positioning of the first wafer is completed, the center coordinates of the breaking center are recorded as the positioning marks for positioning the subsequent wafer to be broken.
The beneficial effects of this disclosure are as follows: the method uses the first wafer 1 provided with the positioning edge and the positioning hole and takes the marking picture F as an auxiliary tool to make the positioning mark, positions the wafer 3 to be broken, and the minimum scale in the marking picture 3 is 1mm, thereby improving the positioning accuracy.
Drawings
Fig. 1 is a schematic view of a first wafer according to the present disclosure.
Fig. 2 is a schematic illustration of a template according to the present disclosure.
Fig. 3 is a schematic view of a first wafer having an off-set region and an off-set center made according to the present disclosure.
Fig. 4 is a schematic view of a wafer to be broken according to the present disclosure.
Fig. 5 is a schematic illustration of a map according to the present disclosure.
FIG. 6 is a schematic illustration of making a locating mark according to the present disclosure.
Fig. 7 is a schematic view of a wafer to be broken placed on a labeled graph according to the present disclosure.
Fig. 8 is a schematic diagram of determining an anchor point on a wafer to be broken according to the present disclosure.
Fig. 9 is a schematic diagram of determining wafer breaking positions according to the present disclosure.
Fig. 10 is a schematic view of a wafer to be off-cut after determining the wafer off-cut position according to the present disclosure.
Wherein the reference numerals are as follows:
1 first wafer
11 first positioning edge
12 second positioning edge
B1 breaking area
C1 breaking center
2 form board
21 third positioning edge
22 fourth alignment edge
C2 round hole
3 wafer to be broken
31 fifth positioning edge
32 sixth locating edge
B2 area to be broken off
F label graph
A1 first coordinate axis
A2 second coordinate axis
L1 first parallel line
L2 second parallel line
L11 first extension line
Second extension line of L12
L21 third extension line
Fourth extension line of L22
P positioning point
Detailed Description
The accompanying drawings illustrate embodiments of the present disclosure and it is to be understood that the disclosed embodiments are merely examples of the disclosure, which can be embodied in various forms, and therefore, specific details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present disclosure.
In the description of the present disclosure, unless otherwise indicated, the terms "first," "second," and the like are used for descriptive and component identification purposes only and are not to be construed as being of relative importance and in a relationship to one another.
Before breaking, firstly, selecting a crystal bar meeting the customer requirements, referring to fig. 1 and 2, cutting a head wafer or a tail wafer of the selected crystal bar to be used as a first wafer 1, and additionally, arranging a template 2 with the same size as that of a target wafer, namely, a to-be-broken region B2, wherein in an embodiment, the first wafer 1 is a four-inch wafer, the target wafer is a three-inch wafer, the size of the template 2 is three inches, and the material of the template 2 can be plastic, quartz, and the like.
After the first wafer 1 and the template 2 are arranged, the crystal bar is sliced to obtain a plurality of wafers 3 to be broken, then the positions of the broken wafers are determined, and whether the accuracy of the positions of the broken wafers is a key influencing the quality of the wafers.
A method of determining wafer breaking positions according to the present disclosure is described in detail below with reference to the accompanying drawings.
The method for determining the wafer breaking-off position according to the present disclosure comprises the steps of: s1, arranging the first wafer 1 and the template 2, arranging the positioning edge on the first wafer 1, arranging the positioning edge and the positioning hole on the template 2, and marking the breaking area B1 and the breaking center C1 on the first wafer by using the template 2; s2, setting a marking diagram F, wherein the length and the width of the marking diagram F are both larger than the diameter of the wafer 3 to be broken, and the minimum scale in the marking diagram F is 1 mm; s3, placing the first wafer 1 on the marked picture F, positioning the first wafer 1 by using the positioning edge on the first wafer 1, making a positioning mark for positioning the wafer 3 to be bent later on in the marked picture F by using the bending center C1, and taking the first wafer 1 off the marked picture F; s4, placing the wafer 3 to be broken on the map F, positioning the wafer 3 to be broken by using the positioning marks in step S3, and marking positioning points on the wafer 3 to be broken; s5, placing the template 2 on the wafer 3 to be broken, positioning the wafer by the positioning edge of the template 2, and simultaneously making the positioning point of the wafer 3 to be broken coincide with the positioning hole of the template 2, and marking a wafer breaking region B2 on the wafer 3 to be broken along the edge of the template 2 to obtain a wafer breaking position.
The first wafer 1 provided with the positioning edge and the template 2 provided with the positioning edge and the positioning hole are used, the positioning mark is made by taking the marking picture F as an auxiliary tool and is used for positioning the wafer 3 to be broken, the minimum scale in the marking picture 3 is 1mm, the positioning accuracy is improved, the template 2 and the marking picture F are used for determining the wafer area B2 to be broken of the wafer 3 to be broken, the operation is simple, the wafer breaking position of each wafer can be accurately determined, and the wafer product quality is improved.
In step S1, referring to fig. 1 and 4, the first wafer 1 and the wafer 3 to be broken are sliced from the same boule, so the first wafer 1 and the wafer 3 to be broken have the same size, and the template 2 and the target wafer, i.e., the region B2 to be broken have the same size, and referring to fig. 3, the breaking region B1 on the first wafer 1 determined by the template 2 has the same size as the region B2 to be broken.
In step S1, referring to fig. 1 and 3, the first wafer 1 is provided with a first positioning edge 11 and a second positioning edge 12, the template 2 is provided with a third positioning edge 21 and a fourth positioning edge 22, a circular hole C2 is cut in the center of the template 2 to serve as a positioning hole, the template 2 is placed on a qualified area on the first wafer 1, a snapping area B1 is marked on the first wafer 1 along the edge of the template 2 by a pen, and a snapping center C1 is marked on the first wafer 1 through the circular hole C2 on the template 2, wherein the positioning hole C2 is a circular hole with a diameter of 1-3 mm. The positioning edge is used for positioning the first wafer 1 and the template 2 and determining the breaking-off position subsequently, so that the positioning accuracy is improved, the size of the positioning hole is small, and the accuracy of the breaking-off position of each wafer is improved.
In step 2, referring to fig. 5 and 6, the length and width of the marked image F are at least 10mm larger than the diameter of the wafer 3 to be broken, which is convenient for operation and positioning marks.
In step 3, there are two methods for making the positioning mark in the map F, one is a line drawing method: referring to fig. 6, first, the first positioning edge 11 is aligned with the first coordinate axis a1 of the plot F, and the second positioning edge 12 is aligned with the second coordinate axis a2, thereby completing the positioning of the first wafer 1; then, a first parallel line L1 parallel to the first coordinate axis a1 is drawn through the breaking center C1; thirdly, a second parallel line L2 parallel to the second coordinate axis a2 is drawn through the snapping center C1; finally, the first parallel line L1 extends to the indication diagram F to obtain a first extension line L11 and a second extension line L12, and the second parallel line L2 extends to the indication diagram F to obtain a third extension line L21 and a fourth extension line L22, referring to fig. 7, the first extension line L11, the second extension line L12, the third extension line L21 and the fourth extension line L22 can be used as positioning marks for positioning the wafer 3 to be subsequently snapped. The other is a coordinate method: firstly, the first positioning edge 11 is superposed with the first coordinate axis A1 of the plot F, and the second positioning edge 12 is superposed with the second coordinate axis A2, so as to complete the positioning of the first wafer 1; after the positioning of the first wafer 1 is completed, the coordinates of the breaking center C1 in the plot F are recorded as positioning marks for the positioning of the subsequent wafer 3 to be broken.
In step S4, the process of marking the positioning points on the wafer 3 to be broken by the positioning marks made by the scribing method is: referring to fig. 7 and 8, the fifth positioning edge 31 of the wafer 3 to be broken coincides with the first coordinate axis a1, the sixth positioning edge 32 of the wafer 3 to be broken coincides with the second coordinate axis a2, the first extension line L11 and the second extension line L12 are connected to form a line segment, the third extension line L21 and the fourth extension line L22 are connected to form a line segment, and the intersection point of the two line segments is the positioning point P for the wafer 3 to be broken. The process of marking the positioning points on the wafer 3 to be broken by the positioning marks made by the coordinate method comprises the following steps: the fifth positioning edge 31 of the wafer 3 to be broken coincides with the first coordinate axis a1, the sixth positioning edge 31 of the wafer 3 to be broken coincides with the second coordinate axis a2, and the coordinate position recorded in step 3 is marked on the wafer 3 to be broken as the marking positioning point P of the wafer 3 to be broken.
In step S5, referring to fig. 9 and 10, the third positioning edge 21 of the template 2 is parallel to the first coordinate axis a1, and the to-be-broken wafer 3 is marked with a pen along the edge of the template 2 with the to-be-broken region B2 by coinciding the circular hole C2 of the template 2 with the positioning point P.
After the wafer breaking position is determined by the method, the wafer breaking process can be performed along the position. According to the method for determining the wafer breaking position, the uniformity and the accuracy of the wafer breaking position can be greatly improved, the product quality of the wafer is improved, and the occurrence that bad products flow to a client side is avoided.
The above detailed description describes exemplary embodiments, but is not intended to limit the combinations explicitly disclosed herein. Thus, unless otherwise specified, various features disclosed herein can be combined together to form a number of additional combinations that are not shown for the sake of brevity.
Claims (10)
1. A method for determining wafer breaking-off positions is characterized by comprising the following steps:
s1: arranging a first wafer (1) and a template (2), arranging a positioning edge on the first wafer (1), arranging a positioning edge and a positioning hole on the template (2), and marking a sheet breaking region (B1) and a breaking center (C1) on the first wafer (1) by using the template (2);
s2: setting a marking picture (F) so that the length and the width in the marking picture (F) are both larger than the diameter of the wafer (3) to be broken, and the minimum scale in the marking picture (F) is 1 mm;
s3: placing the first wafer (1) on the marked picture (F), positioning the first wafer (1) by utilizing the positioning edge on the first wafer (1), making a positioning mark for positioning a wafer (3) to be bent subsequently on the marked picture (F) by utilizing the bending center (C1), and taking the first wafer (1) off the marked picture (F);
s4: placing the wafer (3) to be broken on the mark picture (F), positioning the wafer (3) to be broken by using the positioning mark in the step S3, and marking a positioning point on the wafer (3) to be broken;
s5: the template (2) is placed on the wafer (3) to be broken, the template (2) is positioned through the positioning edge on the template (2), meanwhile, the positioning point of the wafer (3) to be broken is superposed with the positioning hole of the template (2), a wafer breaking area (B2) to be broken is marked on the wafer (3) to be broken along the edge of the template (2), and a wafer breaking position is obtained.
2. The method for determining wafer breaking positions according to claim 1, wherein the first wafer (1) and the wafer to be broken (3) have the same size, the breaking region (B1) of the first wafer (1) and the breaking region (B2) have the same size, and the template (2) and the breaking region (B2) have the same size.
3. The method for determining wafer breaking-off positions according to claim 1, wherein in step S1, the first wafer (1) has a first positioning edge (11) and a second positioning edge (12), and the template (2) has a third positioning edge (21) and a fourth positioning edge (22);
a round hole (C2) is dug in the center of the template (2) to be used as a positioning hole.
4. The method for determining wafer breaking position according to claim 3, wherein in step S3, the first positioning edge (11) coincides with the first coordinate axis (A1) of the plot (F), and the second positioning edge (12) coincides with the second coordinate axis (A2), completing the positioning of the first wafer (1).
5. The method for determining wafer breaking positions according to claim 4, wherein in step S3, a first parallel line (L1) parallel to the first coordinate axis (A1) is drawn through the breaking center (C1); drawing a second parallel line (L2) parallel to the second coordinate axis (a2) through the breaking center (C1); the first parallel line (L1) extends to the marking picture (F) to obtain a first extension line (L11) and a second extension line (L12); the second parallel line (L2) extends to the indicating picture (F) to obtain a third extension line (L21) and a fourth extension line (L22).
6. The method for determining wafer breaking positions according to claim 5, wherein in step S4, the fifth positioning side (31) of the wafer (3) to be broken coincides with the first axis (A1), the sixth positioning side (32) of the wafer (3) to be broken coincides with the second axis (A2), the first extension line (L11) and the second extension line (L12) are connected as a line segment, and the third extension line (L21) and the fourth extension line (L22) are connected as a line segment, and the intersection point of the two line segments indicates the location point (P) for the wafer (3) to be broken.
7. The method for determining wafer breaking positions according to claim 6, wherein in step S5, the third positioning edge (21) of the template (2) is parallel to the first coordinate axis (a1), and the circular hole (C2) of the template (2) is coincident with the positioning point (P), and the wafer to be broken (3) is marked with a pen along the edge of the template (2) with a region to be broken (B2).
8. The method for determining wafer breaking-off positions according to claim 1, wherein the positioning holes on the template (2) are circular holes (C2) with a diameter of 1-3 mm.
9. The method for determining wafer breaking positions according to claim 1, wherein the length and width of the index graph (F) are at least 10mm larger than the diameter of the wafer (3) to be broken.
10. The method for determining wafer breaking positions according to claim 4, characterized in that, in step 3, after the positioning of the first wafer (1) is completed, the coordinates of the breaking center (C1) are recorded as positioning marks for the positioning of the wafer (3) to be subsequently broken.
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| CN202011025214.6A CN112103233B (en) | 2020-09-25 | 2020-09-25 | Method for determining wafer breaking position |
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| EP0580895A2 (en) * | 1992-07-24 | 1994-02-02 | Fujitsu Limited | Method of mapping a tested semiconductor device |
| CN101128928A (en) * | 2005-02-22 | 2008-02-20 | Oc欧瑞康巴尔斯公司 | Method for positioning a wafer |
| CN201089195Y (en) * | 2007-08-31 | 2008-07-23 | 中芯国际集成电路制造(上海)有限公司 | Auxiliary appliance for sheet severing |
| CN104779191A (en) * | 2014-01-10 | 2015-07-15 | 株式会社迪思科 | Mark detecting method |
| CN108975671A (en) * | 2018-10-12 | 2018-12-11 | 广东工业大学 | A kind of dual robot glass breaks piece work planning method and system |
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2020
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0580895A2 (en) * | 1992-07-24 | 1994-02-02 | Fujitsu Limited | Method of mapping a tested semiconductor device |
| CN101128928A (en) * | 2005-02-22 | 2008-02-20 | Oc欧瑞康巴尔斯公司 | Method for positioning a wafer |
| CN201089195Y (en) * | 2007-08-31 | 2008-07-23 | 中芯国际集成电路制造(上海)有限公司 | Auxiliary appliance for sheet severing |
| CN104779191A (en) * | 2014-01-10 | 2015-07-15 | 株式会社迪思科 | Mark detecting method |
| CN108975671A (en) * | 2018-10-12 | 2018-12-11 | 广东工业大学 | A kind of dual robot glass breaks piece work planning method and system |
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