CN112084736B - USB3.0 physical layer transceiver based on FPGA - Google Patents
USB3.0 physical layer transceiver based on FPGA Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F30/347—Physical level, e.g. placement or routing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
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- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
Abstract
The invention discloses a USB3.0 physical layer transceiver device and a method based on an FPGA, wherein the device is configured with a physical layer interface module, a Serdes IP core module, an initialization management module, a parameter configuration module, a data conversion module, an Rx filtering module, an Elastic buffer module and an LFP generation module; after the initial reset operation is completed, parameter initial configuration of the Serdes IP core is carried out; generating an LFP signal and sending the LFP signal to opposite-end USB equipment, converting the LFP signal of the opposite-end USB equipment, and then performing filtering operation to generate an LFP signal which can be identified by a USB3.0 controller; buffering the data packet sent by the opposite-end USB device, compensating and correcting the data packet, and then converting the data packet into a data format and sending the data format to the USB3.0 controller, or converting the data packet sent by the USB3.0 controller into the data format and then sending the data packet to the opposite-end USB device; the invention executes the method by the device, realizes the USB3.0 physical layer transceiver device of each module in the FPGA, simplifies the complexity of the design of the PCB hardware system, improves the stability of the high-speed system and reduces the cost.
Description
Technical Field
The invention relates to the technical field of high-speed data signal transmission, in particular to a USB3.0 physical layer transceiver based on an FPGA.
Background
USB (Universal Serial Bus ), which is an external bus standard for standardizing the connection and communication of computers to external devices. Formulating and maintaining by the USB official organization USB-IF; USB1.1, USB2.0, USB3.0, USB3.1 and USB3.2 are in five versions, and the new version is forward compatible with the old version. The maximum transmission rate distribution supported by each version is: USB1.1:12Mbps; USB2.0:480Mbps; USB3.0:5Gbps; USB3.1:10Gbps; USB3.2:20Gbps.
As USB3.0 technology is increasingly used, embedded devices with USB3.0 interfaces, such as surveillance cameras, multimedia handsets, smartphones, digital cameras, portable media players, and personal navigation devices, are increasingly used. The FPGA internally contains abundant high-speed transceiver resources, has high data processing speed and has great advantages in the field of data transmission; the current communication scheme of the USB3.0 based on the FPGA, such as an SOPC processor, realizes 32-bit RISC (RISC: reduced Instruction Set Computing, reduced instruction set) processing, is connected with a USB3.0 controller through an AXI interconnection bus, and the USB3.0 controller is generally connected with an externally mounted USB3.0 physical layer transceiver chip, such as a TUSB1310A chip of TI company, through a PIPE interface to construct a complete USB3.0 communication scheme.
The prior art has the following defects: the externally hung USB3.0 physical layer transceiver chip is connected onto a PCB (Printed Circuit Board ) through 40 250Mhz high-speed signal wires, so that the complexity of the development of a PCB hardware system is increased, the stability of the system is reduced, and the cost is increased.
Disclosure of Invention
Aiming at the technical problem that the hardware system design is complex in the prior art, the invention provides a USB3.0 physical layer transceiver based on an FPGA.
The technical scheme for solving the technical problems is as follows:
in one aspect, an embodiment of the present invention provides a USB3.0 physical layer transceiver based on FPGA, configured:
the physical layer interface module is used for data transmission with the USB3.0 controller;
the LFP generation module is used for encoding the control signal generated by the USB3.0 controller and converting the control signal to generate an LFP signal;
the Serdes IP core module converts the output high-speed parallel data into serial data for transmission, and converts the received high-speed serial data of the opposite-end USB equipment into parallel data;
the Rx filtering module is used for carrying out filtering operation on the control signal fed back by the Serdes IP core module and generating an LFPS signal which accords with the identification of the USB3.0 controller; the control signal fed back by the Serdes IP core module is obtained by converting an LFPS signal sent by the opposite-end USB device;
the initialization management module is used for carrying out initial reset operation on each module before data transmission and carrying out control management on the parameter configuration module;
the parameter configuration module is used for the initial configuration of the Serdes IP core module parameters; the Serdes IP core parameters include, but are not limited to, SSC parameters and CDR parameters;
an Elastic buffer module, configured to buffer a data packet sent by the opposite end USB device and automatically adapt to insert and delete SKP Order set;
and the data format conversion module is used for carrying out data format conversion on the data packet sent by the opposite-end USB device and the data packet sent by the USB3.0 controller.
On the other hand, the embodiment of the invention provides a USB3.0 physical layer transceiving method based on FPGA, which comprises the following steps:
step 1, performing initial reset operation before data transmission;
step 2, completing initial configuration of Serdes IP core parameters; the Serdes IP core parameters include, but are not limited to, SSC parameters and CDR parameters;
step 3, coding a control signal input by the USB3.0 controller, converting the control signal to generate an LFPS signal, and transmitting the LFPS signal to opposite-end USB equipment;
step 4, receiving the LFP signal of the opposite-end USB device, converting the LFP signal of the opposite-end USB device, and then performing filtering operation to generate an LFP signal which can be identified by the USB3.0 controller;
and step 5, caching the data packet sent by the opposite-end USB device, automatically adapting to insert and delete the SKP Order set, converting the data format and sending the data packet to the USB3.0 controller, or converting the data packet sent by the USB3.0 controller into the data format and sending the data packet to the opposite-end USB device.
The embodiment of the invention provides a USB3.0 physical layer transceiving device and method based on an FPGA, which integrate each module in the FPGA directly in an IP core mode, realize the complete USB3.0 physical layer transceiving process, dispense with externally mounting a USB3.0 physical layer transceiving chip, simplify the design complexity of a PCB hardware system, improve the stability of a high-speed system and reduce the cost.
Drawings
FIG. 1 is a schematic diagram of a USB3.0 physical layer transceiver based on an FPGA according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the overall structure of an embodiment of the present invention;
FIG. 3 is a schematic flow chart of a method for receiving and transmitting USB3.0 physical layer based on FPGA according to an embodiment of the invention;
reference numerals:
1. initialization management module 3, serdes IP core module 2 and parameter configuration module
4. Physical layer interface module 5, LFPS generation module 6, rx filtering module
7. A data format conversion module 8 and an Elastic buffer module.
Detailed Description
The principles and features of the present invention are described below with reference to the drawings, the examples are illustrated for the purpose of illustrating the invention and are not to be construed as limiting the scope of the invention.
FIG. 1 is a schematic diagram of a USB3.0 physical layer transceiver based on an FPGA according to an embodiment of the present invention; as shown in fig. 1, the configuration:
the physical layer interface module 4 is used for data transmission with the USB3.0 controller;
the LFPS generation module 5 is used for encoding a control signal generated by the USB3.0 controller and converting the control signal to generate an LFPS signal;
the Serdes IP core module 3 converts the output high-speed parallel data into serial data for transmission, and converts the received high-speed serial data of the opposite-end USB equipment into parallel data;
the Rx filtering module 6 is used for carrying out filtering operation on the control signal fed back by the Serdes IP core module 3 to generate an LFPS signal which accords with the identification of the USB3.0 controller; the control signal fed back by the Serdes IP core module 3 is obtained by converting an LFPS signal sent by the opposite-end USB device;
the initialization management module 1 is used for performing initial reset operation on each module before data transmission and performing control management on the parameter configuration module 2;
the parameter configuration module 2 is used for initial configuration of parameters of the Serdes IP core module 3; serdes IP core module 3 parameters include, but are not limited to, SSC parameters and CDR parameters;
an Elastic buffer module 8, configured to buffer a data packet sent by the USB device at the opposite end and automatically adapt to insert and delete SKP Order set;
and the data format conversion module 7 is used for carrying out data format conversion on the data packet sent by the opposite-end USB device and the data packet sent by the USB3.0 controller.
Specifically, the physical layer interface module 4 is connected with the USB3.0 controller through the PIPE32 interface, and the physical layer interface module 4 is integrated into the communication system of the USB3.0 in the form of an IP core, so as to realize the communication of a data link and the communication of the management control signals related to the transceiver of the USB3.0 physical layer. The Serdes IP core module 3 is a high-speed transceiver resource in the FPGA, and when data are output and data are input, the high-speed parallel data are verified to be converted into serial data through the internal Serdes IP core, the high-speed serial data are converted into parallel data, and two pairs of high-speed differential signal lines of TxP/N and RxP/N are connected with the opposite-end USB equipment. The parameter configuration module 2 initially configures SSC (spread spectrum clock) parameters, CDR (clock data recovery circuit) parameters and other parameters required by the Serdes IP core module 3 to meet the high-speed signal transmission requirement specified by the USB3.0 protocol, thereby realizing stable high-speed signal transceiving and preventing EMI (Electromagnetic Interference electromagnetic interference) problems. The initialization management module 1 performs initial reset operation on each module of the USB3.0 physical layer transceiver, and resets and initializes each module to a default state before use, so that the working function of the USB3.0 transceiver is ensured; the initialization management module 1 controls and manages the parameter configuration module 2, and the control parameter configuration module 2 writes configuration values such as SSC parameters, CDR parameters and the like into the Serdes IP core module 3. The LFPS generating module 5 is configured to implement a bypass low-speed negotiation protocol specified by the USB3.0 protocol, the USB3.0 controller inputs TxElecIdle and txdielectrxloopbk control signals through the PIPE32 interface of the physical layer interface module 4, the LFPS generating module 5 encodes the TxElecIdle and txdielectrxloopbk control signals, and converts the signals into signals inside the Serdes IP core module, and the hardware generates LFPS (Low Frequency Period Singal, low-frequency periodic signals) signals. The Rx filtering module 6 performs filtering operation on the control signal fed back by the SerdinP core module 3 to generate an LFPS signal which accords with the identification of the USB3.0 controller; specifically, the Serdes IP core module 3 receives the LFPS signal sent by the opposite-end USB device, converts the signal into an RxElecIdle signal through the internal Serdes IP core, and because the RxElecIdle signal cannot be directly used, the Rx filter module 6 is required to perform a filtering operation on the RxElecIdle signal, so as to generate the LFPS signal which accords with the identification of the USB3.0 controller. The Elastic buffer module 8 buffers the received data packet of the opposite end USB device, and implements the insertion of SKP ordered Set and the deletion of SKP ordered Set, so as to solve the problem of data asynchronous between the USB3.0 physical layer transceiver and the opposite end USB device caused by the offset and jitter of the local clock, and prevent the occurrence of overflow and underflow of the received data. The data format conversion module 7 converts the data format of the data packet sent by the USB3.0 controller through the physical layer interface module 4 and the data packet of the receiving opposite-end USB device according to the data transmission format requirement of the Serdes IP core module 3.
FIG. 2 is a schematic diagram of the overall structure of an embodiment of the present invention, as shown in FIG. 2, in which the embodiment of the present invention preferably employs Kintex-7 series XC7K325T manufactured by Xilinx corporation to implement a complete USB3.0 communication scheme within the FPGA; the SOPC processor is connected with the USB3.0 controller through an AXI interconnection bus, and the USB3.0 controller is connected with the USB3.0 physical layer transceiver device through the physical layer interface 4; the USB3.0 physical layer transceiver is directly integrated into the FPGA in an IP core mode, wherein the physical layer interface 4 is a PIPE (The Phy Interface for the USB Architectures) bus interface and is connected with the USB3.0 controller, and the PIPE bus interface supports a 32Bit SDR mode working at 125 Mhz. The GTX high-speed serial transceiver of the Xilinx is preferably mapped to the Serdes IP core module 3 in the USB3.0 physical layer transceiver, and two pairs of high-speed differential signal wires of TxP/N and RxP/N are connected with opposite-end USB equipment through a standard USB3.0 connector.
Further, the serbesip core module 3 includes several types; such as the GTH IP core of Xilinx, the IP core of GTY, the IP core of GTX, etc.; the type of the SerdinP core module 3 is specifically configured according to the type of the FPGA.
Further, according to the type of the Serdes IP core module 3, the parameter configuration module completes the initial configuration of the corresponding Serdes IP core module 3 parameters; and configuring parameters such as SSC parameters, CDR parameters and the like of the corresponding Serdes IP core modules 3 in different types of FPGAs so as to meet the high-speed signal transmission requirements of the Serdes IP core modules 3 in different types under the specification of a USB3.0 protocol.
Further, the initialization management module further comprises a switching operation for the data transmission rate; USB3.0 only supports 5Gbps at present, while USB3.2 supports 10Gbps; the switching of the data transfer rate eliminates the need for redesign when upgrading the transceiver to USB 3.2. Specifically, the upgrade to the USB3.2 data transceiving function includes:
the initialization management module 1 starts a reset operation to reset the device of the invention. Receiving the pipe_rate rate control signal, the parameter configuration module 2 starts the rate switching function, adjusts the SSC parameter configuration value and CDR parameter configuration value to 10Gbps mode, and configures the relevant parameters to the corresponding serbesip core module 3.
An LFP generation module 5 for receiving TxEleIdle and TxDetectRxLoopbk signal control signals, generating LFP signals of SCD1/SCD2 type, and LBPM (SuperSpeedPlus LFPS Based PWM Message, pwm information based on ultra-high speed LFPS) signal, performing out-of-band low speed negotiation of USB 3.2; the SerdinP core module 3 converts the LBPM signal of the opposite terminal equipment into a corresponding control signal and sends the corresponding control signal to the Rx filtering module 6 for filtering operation, and the information negotiation of the channel and the rate of the USB3.2 is completed. If the LFPS generating module 5 performs the out-of-band low-speed negotiation of the USB3.2, the initialization management module 1 restarts the rate switching function, adjusts the SSC number configuration value and the CDR parameter configuration value to be in 5Gbps mode, and configures the relevant parameters to the Serdes IP core module 3, and the LFPS generating module 5 generates an LFPS signal to enter the out-of-band low-speed negotiation of the USB 3.0.
The data format conversion module 7 encodes 128b/132b according to the data required to be transmitted by the Serdes ip core module 3, and transmits the data to the data format conversion module 7 after buffer correction is carried out on the data transmission Elastic buffer module 8 of the opposite-end USB device received by the Serdes ip core module 3, and the data format conversion module 7 decodes 128b/132b of the corrected data, so that the data communication of USB3.2 is upgraded.
The embodiment of the invention provides a USB3.0 physical layer transceiving device based on an FPGA, which integrates all modules in the FPGA directly in an IP core mode, realizes a complete USB3.0 physical layer transceiving process, does not need to externally mount a USB3.0 physical layer transceiving chip, simplifies the design complexity of a PCB hardware system, improves the stability of a high-speed system and reduces the cost; the high-speed signal transmission requirements of different types of Serdes IP cores under the specification of the USB3.0 protocol can be met; the transceiver does not need to be redesigned when being upgraded to the USB3.2, and the design work difficulty is reduced.
Based on the above embodiments, fig. 3 is a schematic flow chart of a USB3.0 physical layer transceiving method based on FPGA according to an embodiment of the present invention; as shown in fig. 3, the method comprises the following steps:
step 1, performing initial reset operation before data transmission;
step 2, completing initial configuration of Serdes IP core parameters; serdes IP core parameters include, but are not limited to, SSC parameters and CDR parameters; the Serdes ip core is written via the Serdes configuration interface with SSC (spread spectrum clock parameter) configuration values, CDR (clock data recovery circuit) parameter configuration values, and other parameter configuration values required by Serdes.
Step 3, coding a control signal input by the USB3.0 controller, converting the control signal into a Serdes IP core internal signal, generating an LFPS signal, and outputting the LFPPS signal through a TxP/N differential line to negotiate with an opposite-end USB device;
step 4, the SerdinP checks RxP/N differential lines to detect, receives the LFP signals of the opposite-end USB equipment, converts the LFP signals of the opposite-end USB equipment into RxEleIdle signals, then carries out filtering operation, generates LFP signals which can be identified by the USB3.0 controller, and completes bypass negotiation specified by the USB3.0 protocol;
and step 5, caching the data packet sent by the opposite-end USB equipment, automatically adapting to insert and delete the SKP Order set, converting the data format, and sending the data packet to the USB3.0 controller, or converting the data packet sent by the USB3.0 controller into the data format, and sending the data packet to the opposite-end USB equipment. Specifically, during data transmission, the USB3.0 controller transmits a data packet to be transmitted through the PIPE32 interface in a 32-bit wide manner; according to the data transmission format requirement of the Serdes IP core, converting the data format of the data packet into an internal 32-bit wide data format, completing parallel-to-serial conversion through the Serdes IP core, and outputting to the opposite-end USB device through the TxP/N differential line; during data receiving, the SerdinP core completes serial-to-parallel conversion by inputting signals to RxP/N differential lines, then converts the data format of the received data packet into a data format with 32-bit width, writes the received data packet into an Elastic buffer, and corrects the received data packet by inserting and deleting SKP ordered Set in an automatic adaptation mode so as to prevent data receiving errors. The controller reads the valid received data packet from the Elastic buffer through the PIPE32 interface, and converts the valid received data packet into a 32-bit wide data format of the PIPE32 interface.
Further, the Serdes IP core includes several types, such as a GTH IP core of Xilinx, an IP core of GTY, an IP core of GTX, etc.; the type of SerdinP core is specifically configured according to the type of FPGA.
Further, according to the type of the Serdes IP core, the initial configuration of the corresponding Serdes IP core parameters is completed. And according to the corresponding Serdes IP cores in the different types of FPGA, completing the corresponding parameter configuration such as SSC parameters, CDR parameters and the like so as to meet the high-speed signal transmission requirements of the Serdes IP cores of different types under the specification of the USB3.0 protocol.
Further, a switching operation for the data transmission rate is also included; USB3.0 only supports 5Gbps at present, while USB3.2 supports 10Gbps; the switching of the data transfer rate eliminates the need for redesign when upgrading the transceiver to USB 3.2. Specifically, the step flow of upgrading to the USB3.2 data receiving and transmitting function is as follows:
a. starting a reset operation to reset the device;
b. receiving a pipe_rate rate control signal, starting a rate switching function, adjusting SSC parameter configuration values and CDR parameter configuration values to be in a 10Gbps mode, and configuring relevant parameters to corresponding SerdinP cores;
c. receiving TxEleIdle and TxDetectRxLoopbk signal control signals, generating an LFPS signal of the SCD1/SCD2 type and an LBPM (SuperSpeedPlus LFPS Based PWM Message, pwm information based on ultra-high speed LFPS) signal;
d. converting LBPM out-of-band modulation signals of the opposite-end USB equipment into corresponding control signals for filtering operation, and completing information negotiation of a channel and a rate of USB 3.2; if the out-of-band low-speed negotiation of the USB3.2 is unsuccessful, restarting a rate switching function, adjusting SSC number configuration values and CDR parameter configuration values to be in a 5Gbps mode, configuring relevant parameters to a Serdes IP core, and carrying out-of-band low-speed negotiation of the USB3.0 with the opposite-end USB equipment through LFPS signals;
e. and the sent transmission data format is encoded according to 128b/132b of data required to be sent by the Serdes ip core module 3, and the Serdes ip core module 3 receives data buffer correction of the opposite-end USB equipment and then decodes the 128b/132b, so that the data communication to the USB3.2 is upgraded.
The embodiment of the invention provides a USB3.0 physical layer transceiving method based on an FPGA, which is executed on the device, and each module is directly integrated in the FPGA in an IP core mode, so that the complete USB3.0 physical layer transceiving process is realized, one USB3.0 physical layer transceiving chip is not required to be externally mounted, the complexity of the design of a PCB hardware system is simplified, the stability of a high-speed system is improved, and the cost is reduced; the high-speed signal transmission requirements of different types of Serdes IP cores under the specification of the USB3.0 protocol can be met; the transceiver does not need to be redesigned when being upgraded to the USB3.2, and the design work difficulty is reduced.
The apparatus embodiments described above are merely illustrative, wherein elements illustrated as separate elements may or may not be physically separate, and elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (8)
1. The USB3.0 physical layer transceiver based on the FPGA is characterized in that: the physical layer interface module is used for data transmission with the USB3.0 controller;
the LFP generation module is used for encoding the control signal generated by the USB3.0 controller and converting the control signal to generate an LFP signal;
the Serdes IP core module converts the output high-speed parallel data into serial data for transmission, and converts the received high-speed serial data of the opposite-end USB equipment into parallel data;
the Rx filtering module is used for carrying out filtering operation on the control signal fed back by the Serdes IP core module and generating an LFPS signal which accords with the identification of the USB3.0 controller; the control signal fed back by the Serdes IP core module is obtained by converting an LFPS signal sent by the opposite-end USB device;
the initialization management module is used for carrying out initial reset operation on each module before data transmission and carrying out control management on the parameter configuration module;
the parameter configuration module is used for the initial configuration of the Serdes IP core module parameters; the Serdes IP core parameters include, but are not limited to, SSC parameters and CDR parameters;
an Elastic buffer module, configured to buffer a data packet sent by the opposite end USB device and automatically adapt to insert and delete SKP Order set;
and the data format conversion module is used for carrying out data format conversion on the data packet sent by the opposite-end USB device and the data packet sent by the USB3.0 controller.
2. The USB3.0 physical layer transceiver device based on FPGA of claim 1, wherein the serbesip core module comprises several types; the type of the SerdinP core module is specifically configured according to the type of the FPGA.
3. The FPGA-based USB3.0 physical layer transceiver of claim 2, wherein the parameter configuration module completes initial configuration of corresponding Serdes IP core module parameters according to the type of the Serdes IP core module.
4. A USB3.0 physical layer transceiver device based on FPGA as claimed in any one of claims 1 to 3 wherein the initialisation management module further comprises a switching operation for the data transfer rate.
5. A physical layer transceiving method using the FPGA-based USB3.0 physical layer transceiving device as defined by any of claims 1-4, comprising the steps of:
step 1, performing initial reset operation before data transmission;
step 2, completing initial configuration of Serdes IP core parameters; the Serdes IP core parameters include, but are not limited to, SSC parameters and CDR parameters;
step 3, coding a control signal input by the USB3.0 controller, converting the control signal to generate an LFPS signal, and transmitting the LFPS signal to opposite-end USB equipment;
step 4, receiving the LFP signal of the opposite-end USB device, converting the LFP signal of the opposite-end USB device, and then performing filtering operation to generate an LFP signal which can be identified by the USB3.0 controller;
and step 5, caching the data packet sent by the opposite-end USB device, automatically adapting to insert and delete the SKP Order set, converting the data format and sending the data packet to the USB3.0 controller, or converting the data packet sent by the USB3.0 controller into the data format and sending the data packet to the opposite-end USB device.
6. The method for transmitting and receiving data in a physical layer according to claim 5, wherein the serdes ip core includes several types; the type of the SerdinP core is specifically configured according to the type of the FPGA.
7. The method for receiving and transmitting physical layer according to claim 6, wherein the initial configuration of the corresponding Serdes IP core parameters is completed according to the type of the Serdes IP core.
8. A method for transmitting and receiving data in a physical layer according to any one of claims 5 to 7, further comprising a switching operation of a data transmission rate.
Priority Applications (1)
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| CN117056259A (en) * | 2023-08-08 | 2023-11-14 | 广东高云半导体科技股份有限公司 | Data processing device and method |
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