CN106303759A - A kind of high speed serialization transceiver interface based on FPGA and method of work thereof - Google Patents
A kind of high speed serialization transceiver interface based on FPGA and method of work thereof Download PDFInfo
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Abstract
The present invention relates to a kind of high speed serialization transceiver interface based on FPGA and method of work thereof.Described interface is used for parallel data and the conversion of serial data, including: Custom MAC end, Custom IP end；Described Custom MAC end, for carrying out parallel data transmitting-receiving with described Custom IP end；Described Custom IP end, for carrying out serial data transmitting-receiving with opposite end Custom IP end；Described Custom IP end is connected with each other by coaxial cable with opposite end Custom IP end.Described high speed serialization transceiver interface is based on FPGA technology, it is achieved circuit be pure hardware circuit；Take hardware space little；Data transparent transmission can be realized；By the multiplexing of PHY passage, possesses certain extended capability；Environmental suitability is strong, and stability is high.
Description
Technical field
The present invention relates to interfacing field, particularly relate to a kind of high speed serialization transceiver interface based on FPGA and work thereof
Method.
Background technology
Traditional data transceiver interface can be divided into parallel interface and serial line interface two kinds, and parallel interface transmission speed is fast, single
Bit time contains much information, but big to the demand of hardware resource；Serial line interface to hardware resource requirements is low but speed is relatively slow.With
The development of science and technology, people are more and more higher to the requirement of information processing and transmission, meet the requirement of resource and speed the most simultaneously
Increasingly being paid attention to by industry, the serial line interface after various improvement arises at the historic moment.
The most general serial line interface mainly has the data-interfaces such as USB, SATA, PCI-E, RapidIO, SDI, wherein；
USB 3.0 is to add 4 on the basis of data wire 4 line structure (power supply, ground wire, 2 data) of USB2.0
Circuit, is used for receiving and transmitting signal, and bus bandwidth is up to 5.0Gbps full duplex, owing to adding 4 circuits, USB's 3.0
Cable can more " thick ", be limited to mainboard interface, storage medium simultaneously；
SATA 3.0 bus bandwidth is promoted to 6Gbps, but needs the support of hardware chip；
PCI-E 3.0 bus bandwidth has reached 10Gbps, but PCI-E interface agreement is huge, hardware interface area occupied
Greatly, some application scenarios is not suitable for, and is mainly used in hard disk and video card interface；
RapidIO 2.x standard supports the transfer rate of 5GHz and 6.25GHz, but is interconnection based on packet-switching
Architecture, configuration complexity, be mainly used in embedded system intraconnection, support chip to the communication between chip, plate to plate,
Backboard (Backplane) mainly as embedded device connects, it is adaptable to bursty communication, is not suitable for long message, session
The communication of formula；
SDI interface uses coaxial cable transmission, and hardware configuration is succinct, and SDI interface can be divided by the serial digital of 270Mbps
Amount signal, for 16:9 format-pattern, can transmit the signal of 360Mbps, but SDI interface is to aim to set up digital audio/video net
Network and design, use synchronizing network technology, and unlike computer network, use Handshake Protocol.
Visible, above-mentioned existing serial line interface also exist equilibrium problem between the key elements such as space, cost, ability, autgmentability with
And the restricted problem of application.Accordingly, it would be desirable to one compares other existing serial line interfaces, cost is suitable, performance is high, hardware accounts for
Little with space, bag conveying length is not limited, the aspect such as Simultaneous Stabilization, autgmentability, maintainability all preferably data transmit-receive
Interface.
Summary of the invention
In view of above-mentioned analysis, it is desirable to provide a kind of high speed serialization transceiver interface based on FPGA and work side thereof
Method, in order to solve existing HSSI High-Speed Serial Interface data transceiver interface balance between the key elements such as space, cost, ability, autgmentability
Problem.
The purpose of the present invention is mainly achieved through the following technical solutions:
A kind of high speed serialization transceiver interface based on FPGA, described interface is used for parallel data and the conversion of serial data,
Including: Custom MAC end, Custom IP end；It is characterized in that,
Described Custom MAC end, for carrying out parallel data transmitting-receiving with described Custom IP end；
Described Custom IP end, for carrying out serial data transmitting-receiving with opposite end Custom IP end；
Described Custom IP end is connected with each other by coaxial cable with opposite end Custom IP end.
Wherein, every described coaxial cable is as a passage；Each Custom IP end transmitting-receiving both direction respectively has
Many 32 passages.
Wherein, Custom MAC end includes: transmit/receive buffer area FIFO, IP kernel initializes and configuration circuit, bell idles self-inspection
Circuit, step-out recovery protection circuit, transmitting-receiving parallel drive circuit, passage entangle a yard circuit, overtime protection circuit.
Wherein, IP kernel initializes and configuration circuit is used for: powers on and resets IP kernel and initialization operation, to depositor
Carry out parameter configuration；Before and after initialization, channel is carried out block protection.
Wherein, transmitting-receiving parallel drive circuit includes sending out parallel drive circuit and receiving parallel drive circuit；Generate parallel drive electricity
The data sent out in caching FIFO are increased feature field according to channel parallel data bit width by road, then by using PHY core to provide
Transmitted in parallel clock is transported in PHY core parallel entry；Receive parallel drive circuit parallel for PHY core outlet data to be carried with PHY core
The parallel clock that receives of confession is for entangling a yard module with reference to feeding passage, and after process, caching FIFO is received in write, extracts for outside.
Wherein, Custom IP end includes: PCS Physical Coding Sublayer, PMA physical media adaptation layer.
Wherein, PCS Physical Coding Sublayer be responsible for 8b/10b coding and CRC check, and be integrated with responsible channel binding and
The elastic buffer of clock correction.
Wherein, PMA physical media adaptation layer carries out parallel-serial conversion to the parallel data after change, is converted to serial data
Stream.
The data transmission method for uplink of a kind of high speed serialization transceiver interface based on FPGA, it is characterised in that comprise the following steps:
Step one, Custom MAC end, Custom IP end initialize；
Step 2, Custom MAC end are from external reception data, and transmitted in parallel is to Custom IP end；
Step 3, Custom IP end receive parallel data, and are converted to serial data stream, are sent by FPGA transceiver
To opposite end FPGA transceiver.
Described Custom IP kernel initializes and farther includes:
1.1, IP kernel initializes and configuration circuit powers on, and resets Custom IP kernel and initializes；Resetting and first
Channel guard is carried out during beginningization；
1.2, after Custom IP end initializes, the real-time self-inspection of bell idles and correction are carried out.
The real-time self-inspection of described bell idles and correction include:
When there being data, receive data；When no data, carry out self-inspection, receive idle self demarking code, monitor passage free time shape
State is the most abnormal；
If passage idle condition is abnormal, enters re-synchronization mechanism and repair；If passage idle condition is normal,
Monitoring Data transmission is the most abnormal further；
If data transmission exception, enter data synchronization processing mechanism and repair；If data transmission is normal, continue
Data send until completing this data receiver；
Self-inspection, repeat the above steps is again carried out after completing this data receiver.
The step 2 of the data transmission method for uplink of described high speed serialization transceiver interface based on FPGA farther includes:
Custom MAC end passes through FPGA inner peripheral logic from host receiving data；
Transmit/receive buffer area fifo module and write enable, the write of the data received from main frame is transmitted/received buffer area FIFO mould
Block；
Send out parallel drive circuit, according to channel parallel data bit width, the data that transmit/receive in buffer area fifo module are increased spy
Levying field, the transmitted in parallel clock then provided by Custom IP end is sent to the parallel entry of Custom IP end.
The step 3 of the data transmission method for uplink of described high speed serialization transceiver interface based on FPGA farther includes:
The PCS Physical Coding Sublayer parallel data to receiving carries out 8B/10B conversion；
PMA physical media adaptation layer carries out parallel-serial conversion to the parallel data after change, is converted to serial data stream and passes through
Coaxial cable sends.
A kind of data receiver method of high speed serialization transceiver interface based on FPGA, it is characterised in that comprise the following steps:
Step one, Custom MAC end, Custom IP end initialize；
Step 2, Custom IP end receive serial data stream by FPGA transceiver from opposite end Custom IP end；To connect
The converting serial data streams received is parallel data, and is sent to Custom MAC end；
Step 3, Custom MAC end receive data parallel from Custom IP end, are sent to outside.
Described Custom IP kernel initializes and farther includes:
1.1, IP kernel initializes and configuration circuit powers on, and resets Custom IP kernel and initializes；Resetting and first
Channel guard is carried out during beginningization；
1.2, after Custom IP end initializes, the real-time self-inspection of bell idles and correction are carried out.
The real-time self-inspection of described bell idles and correction include:
When there being data, receive data；When no data, carry out self-inspection, receive idle self demarking code, monitor passage free time shape
State is the most abnormal；
If passage idle condition is abnormal, enters re-synchronization mechanism and repair；If passage idle condition is normal,
Monitoring Data transmission is the most abnormal further；
If data transmission exception, enter data synchronization processing mechanism and repair；If data transmission is normal, continue
Data send until completing this data receiver；
Self-inspection, repeat the above steps is again carried out after completing this data receiver.
The step 2 of the data receiver method of described high speed serialization transceiver interface based on FPGA farther includes:
Serial data stream is received by coaxial cable；
PMA physical media adaptation layer carries out serioparallel exchange；
PCS Physical Coding Sublayer carries out 10B/8B decoding to parallel data；
Transmission data are exported parallel by PHY core；
The step 3 of the data receiver method of described high speed serialization transceiver interface based on FPGA farther includes:
The transmitted in parallel clock that receiving parallel drive output circuit provides with Custom IP end goes out for reference parallel from PHY core
Mouth receives parallel data；Send into passage and entangle a yard circuit；
Passage entangles yard circuit and processes described parallel data；Solve interchannel due to when the time of advent, order was with transmission
Inconsistent and that there is randomness problem；
Transmitting/receiving buffer area fifo module and write enable, the write of the data after processing transmits/receives buffer area fifo module；
Custom MAC end sends data by FPGA inner peripheral logic to main frame.
The present invention has the beneficial effect that:
Described interface is based on FPGA technology, it is achieved circuit be that (FPGA simultaneously can do auxiliary activities logic to pure hardware circuit
Process)；Take hardware space little；Data transparent transmission can be realized；By the multiplexing of PHY passage, there is certain propagation energy
Power；Environmental suitability is strong, and stability is high.
Other features and advantages of the present invention will illustrate in the following description, and, becoming from description of part
Obtain it is clear that or understand by implementing the present invention.The purpose of the present invention and other advantages can be by the explanations write
Structure specifically noted in book, claims and accompanying drawing realizes and obtains.
Accompanying drawing explanation
Accompanying drawing is only used for illustrating the purpose of specific embodiment, and is not considered as limitation of the present invention, at whole accompanying drawing
In, identical reference marks represents identical parts.
Fig. 1 is the disclosed high speed serialization transceiver interface hardware macrostructure figure based on FPGA of the embodiment of the present invention；
Fig. 2 is the embodiment of the present invention disclosed high speed serialization transceiver interface system based on FPGA composition structural representation；
Fig. 3 is the disclosed high speed serialization transceiver interface modular structure schematic diagram based on FPGA of the embodiment of the present invention.
Fig. 4 be self-inspection in the disclosed high speed serialization transceiver interface initialization procedure based on FPGA of the embodiment of the present invention with
Selfreparing flow chart；
Fig. 5 is passage error correction stream during the disclosed high speed serialization transceiver interface based on FPGA of the embodiment of the present invention receives
Cheng Tu.
Detailed description of the invention
Specifically describing the preferred embodiments of the present invention below in conjunction with the accompanying drawings, wherein, accompanying drawing constitutes the application part, and
Together with embodiments of the present invention for explaining the principle of the present invention.
Abbreviation and Key Term definition
Customization PHY (Custom PHY, a kind of IP kernel, the ethernet PHY transceiver of customizable use)；
PCS (PHYsical Coding Sublayer, Physical Coding Sublayer)；
PMA (PHYsical Medium Attachment, physical media adaptation layer).
A specific embodiment according to the present invention, discloses a kind of high speed serialization transceiver interface based on FPGA, described
Interface achieves the conversion of parallel data and serial data, including: Custom MAC end, Custom IP end；Wherein,
Described Custom MAC end, for carrying out parallel data transmitting-receiving with described Custom IP end；
Described Custom IP end, for carrying out serial data transmitting-receiving with opposite end Custom IP end；
Described Custom IP end is connected with each other by coaxial cable with opposite end Custom IP end；Every coaxial cable conduct
One serial-port；Each Custom IP end transmitting-receiving both direction respectively has most 32 passages, each passage supports 8,16,
The bit width modes such as 32bit, single channels maximum capacity 3.125Gbit.
In the present embodiment, described interface has 6 times of extended capabilities, and by the value that configures lanes (number of vias), (1 to 6 is whole
Number), configure single pass bit width mode, then simultaneously parallel port bit wide is " port number is multiplied by single channel bit width values ", goes here and there simultaneously
Row port number is lanes (port number).
Described Custom IP end is customization PHY, is internally provided with a source clock compensation and drives the work of all cascade channels
Make mode.Each service aisle is actually independent, bundles and the total capacity of macroscopic path is significantly improved.After cascade
PHY interface ability to work ladder between 0 to 2 ten thousand million is adjustable, and reflects the Tiao Shuo district of only coaxial cable on hardware circuit
Not, only need to reserve serial line interface according to the planning of extension, subsequent upgrade need not redesign hardware just can be to letter
Road ability promotes, and reduces cost consumption and construction cycle.Ability as required can be entered by module in actually used
The corresponding configuration of row, hardware environment only increases and decreases number of coaxial cables, and remaining operation is by FPGA programming realization, operation letter
Victory, the construction cycle is short, and effect is notable.
As it is shown on figure 3, described Custom MAC end includes: transmit/receive buffer area FIFO, IP kernel initialize and configuration circuit,
Bell idles self-checking circuit, step-out recovery protection circuit, transmitting-receiving parallel drive circuit, passage entangle a yard circuit, overtime protection circuit；Its
In,
Transmitting-receiving caching FIFO mainly has two big functions: one is clock zone isolation, because the clock frequency of application scenario is with high
Speed interface arranges incoming frequency and there may be difference, and increasing transmitting-receiving caching FIFO can not be affected by cross clock domain.Two is buffering
Data, conveniently carry out the frame operations such as feature head insertion, can increase data transmission guarantee ability.
IP kernel initializes and configuration circuit: one is a powering up resetting IP kernel and initialization operation, to necessary depositor
Carry out parameter configuration；Two be initialize before and after channel carried out the block protection of a period of time, generally 2 seconds.
Bell idles self-checking circuit: after system initialization, bell idles self-checking circuit was made a start to the channel non-usage time
Section cycles through hexadecimal " BC " bell idles, veritifies idle code word in receiving end channel non-use periods simultaneously, is just returning code word
Normal and abnormal two states.
Step-out recovers protection circuit: starts step-out when bell idles detection is returned as abnormality and recovers protection circuit, right
Whole high-speed interface drives and customization PHY core quickly resets, and automatic guarantee channel recovers normal.(experiment shows, passage is different
The startup stage that often state always possibly be present at, not occurring step-out after starting normally, step-out recovers protection circuit can be had
Imitate the normally startup of guarantee channel, can be that during normally working, offer insurance is supported simultaneously.)
Transmitting-receiving parallel drive circuit: send out the number that parallel drive circuit will be sent out in caching FIFO according to channel parallel data bit width
According to increasing feature field, then it is transported in PHY core parallel entry by the transmitted in parallel clock using PHY core to provide；Receive parallel
The parallel clock that receives that parallel for PHY core outlet data provides with PHY core is entangled a yard module for reference feeding passage by drive circuit, place
After reason, caching FIFO is received in write, extracts for outside.
Passage entangles a yard circuit: mainly solve interchannel owing to the order time of advent is inconsistent with when sending and has randomness
Problem.
Overtime protection circuit: mainly suppose that channel keeps state in transmission for a long time, exceedes the setting time, it is believed that at a high speed
Passage occurs in that a kind of special state, i.e. channel externally show as the most occupied and refuse to accept new frame, and this state originates from
In start-up course.Owing to this state can weaken the monitoring dynamics of bell idles testing circuit, so needing to arrange time-out time in addition
Protection, occurs time-out to process by abnormal conditions, starts Restoration Mechanism.Time-out time needs designer according to the actual feelings of applied environment
Condition sets, and cancels as passage used then to need after the Initial Channel Assignment block 2 second time of protection completes with pattern of traffic again
Overtime protection circuit.
Described Custom IP end includes: PCS Physical Coding Sublayer, PMA physical media adaptation layer；Wherein,
PCS Physical Coding Sublayer is responsible for 8b/10b coding, it is to avoid occur in data stream that connecting 0 connects the situation of 1, it is simple to clock
Recover.The PCS Physical Coding Sublayer parallel data to receiving carries out 8B/10B conversion；Every 8bit increases the error-detecging code of 2bit；
One of characteristic of 8B/10B conversion is ensuring that DC balance, and i.e. after coding, in binary data stream, the quantity of " 0 " and " 1 " is basic
Keep consistent, because (so-called long even 0 He when the logic 1 of high speed serialization stream and logical zero have multiple position not produce change
Length connects 1), the conversion of signal will cause signal error because of the relation on rank, voltage position, and DC balance can overcome this to ask
Topic.The when of conversion, continuous print " 0 " or " 1 " quantity, less than 5, must be inserted into after the most every 5 continuous print " 0 " or " 1 "
One " 1 " or " 0 ", thus ensure that signal DC balances.So can ensure that serial data correctly can be restored at receiving terminal,
Utilize special code (K code) that receiving terminal can also be helped to carry out recovery operation simultaneously, and can find that data bit is transmitted in early days
Mistake, suppression mistake continues to occur.
PMA physical media adaptation layer carries out parallel-serial conversion to the parallel data after change, is converted to serial data stream and passes through
Coaxial cable sends；Judgement to link state and the function of carrier sense are provided.
In the present embodiment, PCS and PMA is realized by hardware logic, and the IP kernel part of whole customization PHY employs about 1%
FPGA resource.
A specific embodiment according to the present invention, discloses a kind of described high speed serialization transceiver interface based on FPGA
Data send method of work, comprise the following steps:
Step one, Custom MAC end, Custom IP end initialize；
Specifically, as shown in Figure 4,
Custom IP kernel initializes and farther includes:
1.1, IP kernel initializes and configuration circuit powers on, and resets Custom IP kernel and initializes；Resetting and first
Channel guard is carried out during beginningization；
Firstly, it is necessary to the entrance and exit at Custom IP end increases protection, unwanted for real system data are filtered
Fall, get rid of communicating pair and receive the mistake response that extraneous data in turn results in；
Secondly as customization PHY has the set-up procedure of a very short time after having resetted, but for high-speed interface
This time can not be ignored, and needs that it is had a simple protective；
Wherein, carrying out channel guard and farther including during resetting and initializing:
The block that IP kernel initializes and channel parallel outlet is done a period of time after system start-up resets by configuration circuit is protected
Protect, generally 2 seconds, improve PHY and initialize stability and initial synchronisation ability；
1.2, after Custom IP end initializes, start asynchronous problem for communicating pair Custom IP end during start and enter
The real-time self-inspection of row bell idles and correction；
When there being data, send data；When no data, carry out self-inspection, send idle self demarking code, monitor passage free time shape
State is the most abnormal；Specifically, bell idles self-checking circuit cycles through hexadecimal " BC " to the channel non-usage time period making a start
Bell idles, the normal and abnormal two states of code word simultaneously returned according to the bell idles self-checking circuit of receiving end channel；
If passage idle condition is abnormal, enters re-synchronization mechanism and repair；If passage idle condition is normal,
Monitoring Data transmission is the most abnormal further；
If data transmission exception, enter data synchronization processing mechanism and repair；If data transmission is normal, continue
Data send until completing this secondary data and sending；
Complete again to carry out self-inspection, repeat the above steps after this secondary data sends.
Multiple means is had to use for reparation problem, bell idles detection such as in real time and real time data status monitoring etc.,
Effectively grasping interface real-time status, the necessary means of the very first time anti symptom treatment that notes abnormalities, this means are used in various logical
The survival ability of equipment can be greatly improved among communication system.
State in channel keeps sending for a long time, exceedes the setting time, then it is assumed that occur in that special state, i.e. channel pair
Showing as outward the most occupied and refuse to accept new frame, this state originates from start-up course.Owing to this state can weaken bell idles
The monitoring dynamics of testing circuit, is protected by so needing to arrange time-out time, occurs time-out then to process by abnormal conditions, starts
Repair mechanism.Time-out time needs designer to set according to applied environment practical situation, as used passage with pattern of traffic
Then need to cancel overtime protection circuit again after the Initial Channel Assignment block 2 second time of protection completes.
Step 2, Custom MAC end are from external reception data, and transmitted in parallel is to Custom IP end；Specifically,
Custom MAC end passes through FPGA inner peripheral logic (such as PCI/PCIE interface) from host receiving data；
Transmit/receive buffer area fifo module and write enable, the write of the data received from main frame is transmitted/received buffer area FIFO mould
Block；Transmitting/receiving buffer area fifo module buffered data, convenient insertion feature first-class frame operation is carried out, and increases data transmission guarantee energy
Power；Definition transmission feature head, filters the hash in channel in conjunction with envelope, improves interface service efficiency and reduces fault and go out
Existing probability.Insert during transmission, judge during reception to use；It is in the receiving terminal screening to data that feature head add envelope to filter hash
Link, it is therefore an objective to prevent non-user protocol data from arriving and receive terminal, affect terminal processes process.
Send out parallel drive circuit, according to channel parallel data bit width, the data that transmit/receive in buffer area fifo module are increased spy
Levying field, the transmitted in parallel clock then provided by Custom IP end is sent to entering parallel of Custom IP end (i.e. PHY core)
Mouthful；
Step 3, Custom IP end receive parallel data, and are converted to serial data stream, are sent by FPGA transceiver
To opposite end FPGA transceiver.
Specifically, PCS Physical Coding Sublayer is responsible for 8b/10b coding and CRC check, and is integrated with responsible channel binding
Elastic buffer with clock correction.8b/10b coding can avoid data stream occurs even 0 even 1 situation, it is simple to clock extensive
Multiple.The PCS Physical Coding Sublayer parallel data to receiving carries out 8B/10B conversion；Every 8bit increases the error-detecging code of 2bit；8B/
One of characteristic of 10B conversion is ensuring that DC balance, and i.e. after coding, in binary data stream, the quantity of " 0 " and " 1 " is protected substantially
Hold consistent, (so-called long by even 0 and long because when the logic 1 of high speed serialization stream and logical zero have multiple position not produce change
Connect 1), the conversion of signal will cause signal error because of the relation on rank, voltage position, and DC balance can overcome this problem.
The when of conversion, continuous print " 0 " or " 1 " quantity, less than 5, must be inserted into one after the most every 5 continuous print " 0 " or " 1 "
Position " 1 " or " 0 ", thus ensure that signal DC balances.So can ensure that serial data correctly can be restored at receiving terminal, with
Shi Liyong special code (K code) can also help receiving terminal to carry out recovery operation, and can find data bit transmission mistake in early days
By mistake, suppression mistake continues to occur.
PMA physical media adaptation layer carries out parallel-serial conversion to the parallel data after change, is converted to serial data stream, passes through
Coaxial cable sends；Judgement to link state and the function of carrier sense are provided.
According to another specific embodiment of the present invention, disclose the number of a kind of high speed serialization transceiver interface based on FPGA
According to receiving method of work, comprise the following steps:
Step one, Custom MAC end, Custom IP end initialize；Specifically,
As shown in Figure 4, Custom IP kernel initializes and farther includes:
1.1, IP kernel initializes and configuration circuit powers on, and resets Custom IP kernel and initializes；Resetting and first
Channel guard is carried out during beginningization；
Firstly, it is necessary to the entrance and exit at Custom IP end increases protection, unwanted for real system data are filtered
Fall, get rid of communicating pair and receive the mistake response that extraneous data in turn results in；
Secondly as customization PHY has the set-up procedure of a very short time after having resetted, but for high-speed interface
This time can not be ignored, and needs that it is had a simple protective；
Wherein, during resetting and initializing, carry out channel guard to farther include:
The block that IP kernel initializes and channel parallel outlet is done a period of time after system start-up resets by configuration circuit is protected
Protect, generally 2 seconds, improve PHY and initialize stability and initial synchronisation ability；
1.2, after Custom IP end initializes, start asynchronous problem for communicating pair Custom IP end during start and enter
The real-time self-inspection of row bell idles and correction；
When there being data, receive data；When no data, carry out self-inspection, receive idle self demarking code, monitor passage free time shape
State is the most abnormal；Specifically, receive opposite end bell idles self-checking circuit and the channel non-usage time period is cycled through hexadecimal
" BC " bell idles, bell idles self-checking circuit returns the normal and abnormal two states of code word to opposite end simultaneously；
If passage idle condition is abnormal, enters re-synchronization mechanism and repair；If passage idle condition is normal,
Monitoring Data transmission is the most abnormal further；
If data transmission exception, enter data synchronization processing mechanism and repair；If data transmission is normal, continue
Data send until completing this data receiver；
Self-inspection, repeat the above steps is again carried out after completing this data receiver.
Multiple means is had to use for reparation problem, bell idles detection such as in real time and real time data status monitoring etc.,
Effectively grasping interface real-time status, the very first time that notes abnormalities processes, and can improve the survival ability of equipment.
State in channel keeps receiving for a long time, exceedes the setting time, then it is assumed that occurs in that a kind of special state, i.e. believes
Road externally shows as the most occupied and refuses to accept new frame.Owing to this state can weaken the monitoring force of bell idles testing circuit
Degree, is protected by so arranging time-out time, occurs time-out to process by abnormal conditions, starts repair mechanism.Time-out time according to
Applied environment practical situation sets, as passage used then to need when Initial Channel Assignment block is protected 2 seconds with pattern of traffic
Between complete after cancel overtime protection circuit again.
Step 2, Custom IP end receive serial data by FPGA external transceiver from opposite end Custom IP end and flow to
FPGA internal transceiver；It is parallel data by the converting serial data streams that receives, and is sent to Custom MAC end；Specifically
Ground,
Serial data stream is received by coaxial cable；
PMA physical media adaptation layer carries out serioparallel exchange；
PCS Physical Coding Sublayer carries out 10B/8B decoding to parallel data；
Transmission data are exported parallel by PHY core；
Wherein, the serial data received is converted to parallel data by Custom IP end, and is sent to Custom MAC
End, farther includes:
Owing to passage arranges irregular under multibyte bit width mode between byte data, utilize the advantage that High-Speed Hardware processes
It being realized fully intermeshing process, in the restructuring Main Basis passage of data, each number of subchannels is carried out according to the time order and function occurred；With
Time refer to situation relatively independent between the byte that multibyte bit wide macroscopically shows due to described subchannel, a kind of virtual
Call.Due to PHY core receiving terminal decode after with byte for unit parallel output information, single channel is fictionalized some sons and is led to
Road comes.The byte envelope of each subchannel is relatively independent, needs to build corresponding new data after being integrated into multibyte bit wide
Effectively envelope.
Such as: data are field X " 11223344 " of a bit wide 32 before sending, and arrive opposite end decoding through high-speed interface
After draw X " BCBC3344 ", X " 1122BCBC " (note: BC is idle self demarking code, is likely to occur 16 kinds of combinations herein)；By extensive
Errorless for the originating data supply rear class that recovers, the envelope that rear class needs simultaneously also must be drawn by compound circuit in computing.
In addition to registration operations, recover make a start combination computing based on combinational circuit real-time operation, as it is shown in figure 5,
Step 1: the data that high-speed interface inputs are deposited 1 clock cycle by passage, respectively for data recombination；With
Time, passage envelope is deposited in a register 1 clock cycle；
Step 2: registered data sequence being recombinated for reference the time of advent with corresponding passage envelope, after restructuring, data are posted
Deposit, after waiting envelope computing, obtain corresponding envelope；
Step 3: check the envelope value in the former envelope value of the most each passage and depositor in each clock cycle T, with always
Line data mode checks (the corresponding bit of each passage)；Such as during 4 passage, former envelope value is only distinguished to be had with non-entirely completely without effect
Imitating two kinds of situations, depositor envelope value has 16 kinds.2 kinds of former envelope value and 16 kinds of depositor envelope value are done combination and judged: former bag
Network value completely without effect and depositor envelope value entirely effectively time, output envelope value is arbitrary channel register envelope value；Former envelope value is non-
During completely without effect, output envelope value is the depositor envelope value of the highest effective bit respective channel.Learn the envelope of current time
As the envelope output after restructuring after virtual value；(that is: actual output envelope be the latest that passage effective deposit bag
Network.)
Data after restructuring are added corresponding envelope, sends rear class to and process.
Step 3, Custom MAC end receive data parallel from Custom IP end, are sent to outside；Specifically,
The transmitted in parallel clock that receiving parallel drive output circuit provides with Custom IP end goes out for reference parallel from PHY core
Mouth receives parallel data；Send into passage and entangle a yard circuit；
Passage entangles yard circuit and processes described parallel data；Solve interchannel due to when the time of advent, order was with transmission
Inconsistent and that there is randomness problem；
Transmitting/receiving buffer area fifo module and write enable, the write of the data after processing transmits/receives buffer area fifo module；
Custom MAC end sends data by FPGA inner peripheral logic (such as PCI/PCIE interface) to main frame.
The present invention has the beneficial effect that:
Described high speed serialization transceiver interface is based on FPGA technology, it is achieved circuit be that (FPGA can do pure hardware circuit simultaneously
Auxiliary activities logical process)；Take hardware space little；Data transparent transmission can be realized；By the multiplexing of PHY passage, have one
Fixed extended capability；Environmental suitability is strong, and stability is high.
The above, the only present invention preferably detailed description of the invention, but protection scope of the present invention is not limited thereto,
Any those familiar with the art in the technical scope that the invention discloses, the change that can readily occur in or replacement,
All should contain within protection scope of the present invention.
Claims (10)
1. a high speed serialization transceiver interface based on FPGA, described interface is used for parallel data and the conversion of serial data, bag
Include: Custom MAC end, Custom IP end；It is characterized in that,
Described Custom MAC end, for carrying out parallel data transmitting-receiving with described Custom IP end；
Described Custom IP end, for carrying out serial data transmitting-receiving with opposite end Custom IP end；
Described Custom IP end is connected with each other by coaxial cable with opposite end Custom IP end.
High speed serialization transceiver interface based on FPGA the most according to claim 1, it is characterised in that
Every described coaxial cable is as a passage；Each Custom IP end transmitting-receiving both direction respectively has most 32 and leads to
Road；
Described Custom MAC end includes: transmit/receive buffer area FIFO, IP kernel initialize and configuration circuit, bell idles self-checking circuit,
Step-out recovery protection circuit, transmitting-receiving parallel drive circuit, passage entangle a yard circuit, overtime protection circuit；
Described Custom IP end includes: PCS Physical Coding Sublayer, PMA physical media adaptation layer.
High speed serialization transceiver interface based on FPGA the most according to claim 2, it is characterised in that
Described IP kernel initializes and configuration circuit is used for: powers on and resets IP kernel and initialization operation, carries out depositor
Parameter configuration；Before and after initialization, channel is carried out block protection；
Described transmitting-receiving parallel drive circuit includes sending out parallel drive circuit and receiving parallel drive circuit；Send out parallel drive circuit according to
Channel parallel data bit width will send out the data increase feature field in caching FIFO, parallel then provided by use PHY core
Clock is sent to be transported in PHY core parallel entry；Receive parallel drive circuit parallel for PHY core outlet data to be provided also with PHY core
Row receives clock and entangles a yard module for reference feeding passage, and after process, caching FIFO is received in write, for outside extraction.
High speed serialization transceiver interface based on FPGA the most according to claim 2, it is characterised in that
Described PCS Physical Coding Sublayer is responsible for 8b/10b coding and CRC check, and integrated responsible channel binding and clock are repaiied
Positive elastic buffer.
High speed serialization transceiver interface based on FPGA the most according to claim 2, it is characterised in that
Described PMA physical media adaptation layer carries out parallel-serial conversion to the parallel data after change, is converted to serial data stream.
6. the data transmission method for uplink of a high speed serialization transceiver interface based on FPGA, it is characterised in that comprise the following steps:
Step one, Custom MAC end, Custom IP end initialize；
Step 2, Custom MAC end are from external reception data, and transmitted in parallel is to Custom IP end；
Step 3, Custom IP end receive parallel data, and are converted to serial data stream, are sent to right by FPGA transceiver
End FPGA transceiver.
The data transmission method for uplink of high speed serialization transceiver interface based on FPGA the most according to claim 6, it is characterised in that
Described Custom IP kernel initializes and farther includes:
1.1, IP kernel initializes and configuration circuit powers on, and resets Custom IP kernel and initializes；Resetting and initializing
Period carries out channel guard；
1.2, after Custom IP end initializes, the real-time self-inspection of bell idles and correction are carried out；
The real-time self-inspection of described bell idles and correction include:
When there being data, receive data；When no data, carrying out self-inspection, receive idle self demarking code, monitoring passage idle condition is
No exception；
If passage idle condition is abnormal, enters re-synchronization mechanism and repair；If passage idle condition is normally, enter one
Step Monitoring Data transmission is the most abnormal；
If data transmission exception, enter data synchronization processing mechanism and repair；If data transmission is normal, continue data
Send until completing this data receiver；
Self-inspection, repeat the above steps is again carried out after completing this data receiver.
The data transmission method for uplink of high speed serialization transceiver interface based on FPGA the most according to claim 6, it is characterised in that
Described step 2 farther includes:
Custom MAC end passes through FPGA inner peripheral logic from host receiving data；
Transmit/receive buffer area fifo module and write enable, the data received from main frame write is transmitted/received buffer area fifo module；
Send out parallel drive circuit, according to channel parallel data bit width, the data that transmit/receive in buffer area fifo module are increased tagged word
Section, the transmitted in parallel clock then provided by Custom IP end is sent to the parallel entry of Custom IP end；
Described step 3 farther includes:
The PCS Physical Coding Sublayer parallel data to receiving carries out 8B/10B conversion；
PMA physical media adaptation layer carries out parallel-serial conversion to the parallel data after change, is converted to serial data stream；By coaxially
Cable sends.
9. the data receiver method of a high speed serialization transceiver interface based on FPGA, it is characterised in that comprise the following steps:
Step one, Custom MAC end, Custom IP end initialize；
Step 2, Custom IP end receive serial data stream by FPGA transceiver from opposite end Custom IP end；To receive
Converting serial data streams be parallel data, and be sent to Custom MAC end；
Step 3, Custom MAC end receive data parallel from Custom IP end, are sent to outside；
Described Custom IP kernel initializes and farther includes:
1.1, IP kernel initializes and configuration circuit powers on, and resets Custom IP kernel and initializes；Resetting and initializing
Period carries out channel guard；
1.2, after Custom IP end initializes, the real-time self-inspection of bell idles and correction are carried out；
The real-time self-inspection of described bell idles and correction include:
When there being data, receive data；When no data, carrying out self-inspection, receive idle self demarking code, monitoring passage idle condition is
No exception；
If passage idle condition is abnormal, enters re-synchronization mechanism and repair；If passage idle condition is normally, enter one
Step Monitoring Data transmission is the most abnormal；
If data transmission exception, enter data synchronization processing mechanism and repair；If data transmission is normal, continue data
Send until completing this data receiver；
Self-inspection, repeat the above steps is again carried out after completing this data receiver.
The data receiver method of high speed serialization transceiver interface based on FPGA the most according to claim 9, its feature exists
In；
Described step 2 farther includes:
Serial data stream is received by coaxial cable；
PMA physical media adaptation layer carries out serioparallel exchange；
PCS Physical Coding Sublayer carries out 10B/8B decoding to parallel data；
Transmission data are exported parallel by PHY core；
Described step 3 farther includes:
Receive transmitted in parallel clock that parallel drive output circuit provides with Custom IP end to export parallel from PHY core for reference and connect
Receive parallel data；Send into passage and entangle a yard circuit；
Passage entangles yard circuit and processes described parallel data；Solve interchannel owing to differing when the order time of advent is with transmission
The problem caused and there is randomness；
Transmitting/receiving buffer area fifo module and write enable, the write of the data after processing transmits/receives buffer area fifo module；
Custom MAC end sends data by FPGA inner peripheral logic to main frame.
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