JP2007233993A - Data transfer control device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transfer control device and an electronic apparatus that can implement an efficient compliance test. <P>SOLUTION: The data transfer control device includes a pattern generator 52 for generating a test pattern of a compliant pattern, a scrambler 54 for performing scrambling, and a data scrambler 56 for scrambling and outputting transmission data. The scrambler 54 scrambles the test pattern from the pattern generator 52 at a compliance test using a compliant pattern. The data scrambler 70 scrambles and outputs the scrambled test pattern from the scrambler 54 at the compliance test. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data transfer control device and an electronic device.

  In recent years, a standard called Serial ATA (Serial AT Attachment) has been spotlighted as a serial interface for storage devices and the like. This serial ATA is a standard having compatibility at the software level with ATA (IDE) which is a parallel interface. The data transfer rate of the first standard, Serial ATA I, was 1.5 Gbps, but the next standard, Serial ATA II, has increased the data transfer rate to 3.0 Gbps. Serial ATA II also defines external connections.

  In this serial ATA, a compliant pattern is defined in order to perform a compliance test of the serial interface. This compliant pattern is composed of an SOF (Start Of Frame) primitive, a test pattern (specified test pattern) following the SOF primitive, a CRC (Cyclic Redundancy Check) following the test pattern, and an EOF (End Of Frame) primitive. The This test pattern is a pattern for confirming the compliance and signal integrity of the serial ATA interface.

In the serial ATA standard, the test pattern of the compliant pattern needs to appear on the serial ATA cable (serial bus) in a state where the pattern is not scrambled. However, if a controller for the link layer or the tonlas port layer is designed based on the serial ATA standard, it is necessary to scramble the data to be transferred. For this reason, the test pattern generation process becomes complicated, and there is a problem that it is not suitable for a data transfer control device for embedded use.
JP 2004-233200 A

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a data transfer control device capable of realizing an efficient compliance test and an electronic apparatus including the data transfer control device.

  The present invention relates to a data transfer control device for transferring data via a serial bus, a pattern generator for generating a compliant pattern test pattern, a scrambler for scramble processing, and scramble processing for transmission data. A data scrambler that performs and outputs the scrambler, the scrambler performs a scramble process on the test pattern from the pattern generator during a compliance test in which a test is performed using a compliant pattern, and the data scrambler The present invention relates to a data transfer control device that performs scramble processing on a test pattern after scramble processing from the scrambler and outputs the test pattern during the compliance test.

  According to the present invention, during a compliance test, the pattern generator generates a compliant pattern test pattern, and the scrambler scrambles the generated test pattern. Then, the data scrambler scrambles the test pattern after the scramble process, and outputs the obtained test pattern. In this way, the test pattern generated by the pattern generator appears on the serial bus, and an appropriate compliance test can be realized. In addition, since the test pattern is automatically scrambled twice, returns to the original pattern, and is output from the data scrambler, an efficient compliance test can be realized.

  In the present invention, a CRC calculation unit for transmission that calculates a CRC of transmission data and outputs the CRC to the data scrambler is included, and the transmission CRC calculation unit includes a test pattern from the pattern generator during the compliance test. CRC may be calculated and output to the data scrambler.

  In this way, it is possible to calculate and add a CRC with a control flow similar to that during normal operation, thereby simplifying the processing.

  Further, in the present invention, a first selector in which transmission data is input to the first input terminal and a test pattern after scramble processing from the scrambler is input to the second input terminal, and the first selector The output of the first selector is input to the input terminal, the output of the CRC calculation unit for transmission is input to the second input terminal, and the data to the data scrambler is output to the output terminal. These selectors may be included.

  In this way, switching between the normal operation and the compliance test can be realized only by switching the first and second input terminals of the first and second selectors. Processing and configuration of the data transfer control device Can be simplified.

  In the present invention, the output of the data scrambler is input to the first input terminal, the output of the scrambler is input to the second input terminal, and data to the physical layer circuit is output to the output terminal. A third selector may be included.

  In this way, the scrambled data from the data scrambler and the scrambled data from the scrambler can be switched and output only by switching the first and second input terminals of the third selector.

  In the present invention, the scrambler may be a scrambler that generates scramble data following a continue primitive.

  In this way, the scrambler for continue primitives used during normal operation can be used effectively, so that the scale of the data transfer control device can be minimized.

  In the present invention, an 8b / 10b encoder that is provided between the data scrambler and the physical layer circuit and performs 8b / 10b encoding processing may be included.

  Further, the present invention may include a test control unit that instructs the pattern generator to generate a test pattern generated by the pattern generator from among a plurality of test patterns.

  In this way, an arbitrary test pattern can be generated from a plurality of test patterns and output to the serial bus only by an instruction from the test control unit, and processing such as a processing unit for controlling the data transfer control device The load can be reduced.

  The present invention may also include a data descrambler that performs descrambling processing of data received by the physical layer circuit, and a reception CRC calculation unit that calculates CRC of the data after descrambling processing.

  In this way, it is possible to realize descrambling processing and CRC calculation for the received data input via the physical layer circuit.

  The present invention may also include an 8b / 10b decoder provided between the physical layer circuit and the data descrambler and performing 8b / 10b decoding processing.

  In the present invention, the serial bus may be a serial ATA (Serial AT Attachment) bus.

  The present invention also relates to an electronic device including any of the data transfer control devices described above and a processing unit that controls the data transfer control device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Serial ATA
First, the Serial ATA (Serial AT Attachment) standard will be described. FIG. 1 shows a layer structure of serial ATA (hereinafter, SATA).

  In the physical layer, serial communication between the host and the device, conversion from serial data to parallel data, conversion from parallel data to serial data, and the like are performed. Specifically, the bit string is converted into serial bits and transferred as a differential signal with a small amplitude.

  In the link layer, data transmission / reception with the physical layer, control of the serial interface protocol, and application data (user data) transmission / reception with the transport layer are performed. Specifically, transmission path arbitration and flow control for frame transfer are performed, and FIS (Frame Information Structure) and 8b / 10b conversion for converting a control code into a bit string suitable for serial transmission are performed.

  The application layer accesses the transport layer through the same interface as the parallel ATA (IDE) standard host bus adapter (HBA). Register access and the like are compatible with the parallel ATA standard command protocol at the software level. The transport layer converts data transmitted / received to / from the link layer into a parallel ATA standard command protocol operation.

  These physical layer, link layer, and transport layer are realized by a physical layer circuit (PHY controller), link controller, and transport controller provided on the host side and device side. The application layer is realized by software on the host side and device side, buffer memory, DMA engine, and the like.

  In parallel ATA (IDE), all task file registers (TFR) which are control registers are mapped to the address space of the CPU (processing section in a broad sense). Software on the CPU reads / writes this register to control the device. This TFR is simultaneously referred to from the firmware on the device side.

  In SATA, compatibility at the software level with conventional parallel ATA (IDE) is maintained. SATA is characterized by the presence of the two TFRs described above. That is, the shadow task file register (shadow TFR) existing on the host (HBA) side and the original task file register (device TFR) on the device side. Only the shadow TFR is directly accessible from the software on the CPU, and only the device TFR is directly accessible from the firmware on the device side. The two TFRs are copied to each other by a Host to Device Register FIS, a Device to Host Register FIS, and a PIO Setup FIS when a command is issued and completed. In SATA, 8 frames (FIS) are defined to emulate a conventional IDE.

  2 and 3 show the flow of data processing in the transport layer, link layer, and physical layer. FIG. 2 shows the flow of data processing on the transmission side, and FIG. 3 shows the flow of data processing on the reception side.

  As shown in FIG. 2, in the transport controller (transport layer) on the transmission side, the FIS is generated by the command written in the shadow register and the data input in the data port. Here, FIS is a payload portion of a frame, and is configured in units of Dword (32 bits). The frame is an information unit exchanged between the host and the device. The SOF (Start Of Frame) primitive, the FIS, the CRC (Cyclic Redundancy Check) calculated for the FIS, and the EOF (End Of Frame) are used. ) Consists of primitives.

  In the link controller, the CRC for the FIS is calculated and added to the end of the FIS. Then, a scramble process is performed to obtain an exclusive OR (XOR) of the FIS and CRC and the scramble data. Then, 8b / 10b encoding is performed on the scrambled FIS and CRC. Here, 8b / 10b encoding is a data transmission encoding algorithm that converts 8-bit data into 10-bit transmission characters. The number of 1's and 0's in the code string is aligned to guarantee continuous transmission. Then, primitives such as SOF and EOF are added to the FIS and CRC after 8b / 10b encoding.

  In the physical layer circuit, parallel data from the link layer is converted into serial data and transmitted to the serial ATA bus as a differential signal with a small amplitude.

  As shown in FIG. 3, in the physical layer circuit on the receiving side, serial data received via the serial ATA bus is converted into parallel data.

  In the link controller, the primitive added to the FIS and CRC is decoded. In addition, 8b / 10b decoding for FIS and CRC is performed. That is, a 10-bit transmission character is converted into 8-bit data. Next, a descrambling process is performed to obtain an exclusive OR of the scrambled FIS and CRC and the scrambled data. Then, the CRC added at the end of the FIS is checked.

  In the transport controller, the FIS command is written to the shadow register, status and interrupt are output, and data is output via the data port.

2. Configuration FIG. 4 shows a configuration example of the data transfer control device of this embodiment. The data transfer control device includes a transport controller 10, a link controller 50, and a physical layer circuit 100. A test control unit 150 is also included. Note that the data transfer control device of the present embodiment is not limited to the configuration of FIG. 4, and some of the components may be omitted or other components may be added. For example, the physical layer circuit 100 may not be included. Alternatively, the transport controller 10 and the test control unit 150 may not be included. Alternatively, some of the components of the link controller 50 may be omitted or other components may be added.

  In SATA, data is processed in units of 32 bits. The 32-bit data is encoded at 8b / 10b by the link controller 50 to become 40-bit data, which is sent to the physical layer circuit 100. The physical layer circuit 100 serializes the 40-bit data and transmits it to the SATA cable. In the reverse order of reception, serial data is converted into 40-bit data by the physical layer circuit 100, converted into 32-bit data by the link controller 50, and sent to the transport controller 10.

  The transport controller 10 controls the transport layer. Specifically, the transport controller 10 performs the following processing when an FIS transmission request is received from an upper layer (application layer).

  First, the transport controller 10 collects the contents of the FIS based on the requirements of the FIS type. Information to be transmitted is arranged in a definition format for each type of FIS. Next, a transmission request is notified to the link controller 50. As a result, the link controller 50 performs X_RDY transmission processing. When the R_RDY from the partner node is received and an acknowledgment of reception is received from the link controller 50, the transport controller 10 transfers the FIS to the link controller 50. Then, the flow management of the transmission FIFO is performed, and necessary flow control is notified to the link controller 50. Thereafter, when a transmission result is received from the link controller 50, the transmission result is notified to an upper layer as necessary.

  When the transport controller 10 receives the FIS from the link controller 50, the transport controller 10 performs the following processing.

  When the transport controller 10 receives the FIS from the link controller 50, the transport controller 10 determines the type of the received FIS. Then, the data is transferred to an appropriate register or FIFO according to the type of FIS. Then, the flow management of the reception FIFO is performed, and necessary flow control is notified to the link controller 50. Thereafter, the reception result is notified to the link controller 50 and the upper layer (application layer).

  The link controller 50 controls the link layer. Specifically, the link controller 50 performs the following processing at the time of transmission.

  First, the link controller 50 receives data (FIS) from the transport controller 10. A FIS CRC is generated and added to the end of the FIS. Next, the data is scrambled, and then 8b / 10b encoding is performed. Then, the primitive and FIS are transmitted according to the SATA communication protocol. Then, the transmission result is notified to the transport controller 10.

  The link controller 50 performs the following processing at the time of reception. That is, the link controller 50 receives the 8b / 10b encoded character from the physical layer circuit 100. Then, the 8b / 10b encoded character is decoded, and the decoded primitive is notified to the processing unit or the like. Next, the decoded FIS is descrambled and the CRC is checked. Then, the data is passed to the transport controller 10. In addition, the transport controller 10 is notified of the decoding result and the CRC check result.

  A physical layer circuit (PHY) 100 is an analog front-end circuit that realizes a physical layer. The physical layer circuit 100 performs transmission / reception of serial data (serial stream), conversion from serial data to parallel data, and conversion from parallel data to serial data. It also detects 8b / 10b K28.5 characters and detects and transmits OOB (Out Of Band) signals. It also provides device status (device presence / absence, transfer status, power status) and communication control interface (transfer rate control, loopback). Optional power management.

  The physical layer circuit 100 includes a transmitter (driver) 110 and a receiver 120. The transmitter 110 transmits serial data (packet) via a differential signal line (differential signal line pair) TX +/−, and the receiver 120 via a differential signal line (differential signal line pair) RX +/−. Serial data (packet) is received. On the TX +/− and RX +/− SATA buses (serial bus in a broad sense), serial stream transfer is performed using an NRZ differential signal having an amplitude voltage of +/− 250 mV. A transfer rate of 1.5 Gbps (3.0 Gbps for SATA II Gen2) is prepared, and data is extracted from the serial stream. SSC (Spread Spectrum Clocking) and transmitter / receiver impedance are also measured.

  The SATA cable has 7 cores, and each pair of differential signal lines TX +/− and RX +/− is assigned to the transmitter 110 and the receiver 120. The rising signal connects TX +/− on the device side and RX +/− on the host (HBA) side, and the down signal connects TX +/− on the host side and RX +/− on the device side. SATA has a full-duplex specification, and data can only be transmitted in one direction. Therefore, during communication with TX +/−, protocol communication from the partner node can be performed with RX +/− as a back channel, which can be effectively used for flow control.

  The link controller 50 includes a TX (transmit) block and an RX (receive) block. The TX block includes a pattern generator 52, a scrambler 54, and a data scrambler 56. Further, a CRC calculation unit 58 for transmission and an 8b / 10b encoder 60 are included. Further, first, second, and third selectors 61, 62, and 63 are included. The RX block includes a data scrambler 70, a reception CRC calculation unit 72, and an 8b / 10b decoder 74. The link controller 50 is not limited to the configuration shown in FIG. 4, and some of the components may be omitted or other components may be added. For example, the pattern generator 52 may be provided outside the link controller 50.

  The pattern generator 52 generates a test pattern of a compliant pattern. The pattern generator 52 may be realized by a combinational logic circuit or a ROM. The pattern generator 52 generates and outputs a test pattern instructed by the test control unit 150. Since the test pattern of the compliant pattern is mainly the repetition of a predetermined pattern, the number of gates of the combinational logic circuit of the pattern generator 52 can be reduced by performing logical compression.

  The scrambler 54 performs scramble processing. As the scrambler 54, a scrambler for CONT primitive that generates scramble data following the CONT (continue) primitive can be used. That is, since the CONT primitive is not used during the test, the test pattern from the pattern generator 52 is It can be scrambled using a CONT primitive scrambler.

The data scrambler 56 scrambles the transmission data from the transport controller 10 and outputs the scrambled data (FIS, CRC) to the physical layer circuit 100. The scramble processing can be realized by a linear feedback shift register (LFSR) using a generator polynomial such as G (X) = X ¹⁶ + X ¹⁵ + X ¹³ + X ⁴ +1. A specific implementation method of the scramble processing is described in detail in A.2 of serial ATA revision 1.0a.

  FIG. 5A shows a configuration example of the data scrambler 56. The data scrambler 56 includes a scramble data generation unit 200 and an EXOR 202 (exclusive OR). 1 Dword DATA [32: 0] is input to the first input terminal of the EXOR 202, and the scrambled data from the scramble data generation unit 200 is input to the second input terminal of the EXOR 202, and the exclusive OR of these is calculated. And output as scrambled data.

  In this embodiment, the scrambler 54 (CONT primitive scrambler) performs a scramble process on the test pattern from the pattern generator 52 during a compliance test in which a test is performed using a compliant pattern. The data scrambler 56 performs a scramble process on the test pattern after the scramble process from the scrambler 54 at the time of the compliance test, and outputs the obtained test pattern to the physical layer circuit 100. By performing the scramble process twice in this way, the original unscrambled test pattern is output from the data scrambler 56.

The CRC calculator 58 calculates the CRC of the transmission data and outputs it to the data scrambler 56 (selector 62) during normal operation. That is, the CRC of the transmission data is calculated, and a CRC code is added immediately before the EOF primitive. This CRC operation is performed on all FIS transport data between the SOF primitive and the EOF primitive, and no CRC operation is performed on intervening primitives and CONT stream contents. This CRC is, for example, a linear feedback shift register using a generator polynomial such as G (X) = X ³² + X ²⁶ + X ²³ + X ²² + X ¹⁶ + X ¹² + X ¹¹ + X ¹⁰ + X ⁸ + X ⁷ + X ⁵ + X ⁴ + X ² + X + 1 LFSR). In this case, the CRC value is initialized to a value of, for example, 52325032h before CRC calculation.

  In the present embodiment, the CRC calculation unit 58 calculates the CRC for the test pattern (test pattern after the scramble process) from the pattern generator 52 and outputs it to the data scrambler 56 during the compliance test.

  In the selector 61 (first selector), transmission data is input to the first input terminal, and the test pattern after the scramble processing from the scrambler 54 is input to the second input terminal. In the normal operation, the first input terminal is selected, and in the compliance test, the second input terminal is selected. The output of the selector 61 is input to the CRC calculation unit 58 and the selector 62.

  The selector 62 (second selector) receives the output of the selector 61 at its first input terminal and the output of the CRC calculation unit 58 at its second input terminal. The first input terminal is selected at times other than the CRC calculation, and the second input terminal is selected at the CRC calculation. Data to the data scrambler 56 is output to the output terminal of the selector 62.

  The selector 63 (third selector) receives the output of the data scrambler 56 at its first input terminal and the output of the scrambler 54 at its second input terminal. When the CONT primitive scramble data (junk data) is not output, the first input terminal is selected, and when the CONT primitive scramble data is output, the second input terminal is selected. Data to the physical layer circuit 100 is output to the output terminal of the selector 63.

  The 8b / 10b encoder 60 is provided between the data scrambler 56 (selector 63) and the physical layer circuit 100, and performs 8b / 10b encoding processing. In the 8b / 10b encoding, 8-bit byte data is code-converted into 10-bit data. Specifically, a running disparity is added to 256 types of data in a 10-bit bit string, and the remaining code is assigned as a K character for control. In SATA, only K28.3 and K28.5 codes are used. Each SATA primitive is composed of one K28.3 or K28.5 code and three data codes. In the transfer by the link controller 50, 1-Dword (32 bits) frame data or primitives are converted into 40-bit bit strings and sent to the physical layer circuit 100. Here, primitives include ALIGN, CONT, DMAT, SOF, EOF, HOLD, HOLDA, R_ERR, R_RDY, R_IP, R_OK, X_RDY, SYNC, and the like.

  The data descrambler 70 of the RX block performs a descrambling process on the data (RX +/−) received by the physical layer circuit 100. That is, the scrambled data is returned to the original unscrambled data.

  FIG. 5B shows a configuration example of the data descrambler 70. The data descrambler 70 includes a scramble data generator 210 and an EXOR 212 (exclusive OR). Then, 1 Dword DATA [32: 0] is input to the first input terminal of the EXOR 212, the scrambled data from the scramble data generating unit 210 is input to the second input terminal of the EXOR 212, and the exclusive OR of these is calculated. And output as scrambled data.

  The CRC calculation unit 72 of the RX block calculates the CRC of the data after descrambling and checks the CRC. That is, the CRC of the received data is calculated, and it is checked based on the CRC code whether the received data is correct data. The 8b / 10b decoder 74 of the RX block is provided between the physical layer circuit 100 and the data descrambler 70, and performs 8b / 10b decoding processing. That is, the 10-bit code is decoded into 8-bit data.

  The test control unit 150 performs test processing such as control of the pattern generator 52. Specifically, a test pattern generated by the pattern generator 52 is selected from a plurality of test patterns (LTDP, HTDP, LFSCP, LBP, SSOP, etc.). The pattern generator 52 is instructed to generate the selected test pattern.

3. Compliance Test As a test for evaluating the SATA physical layer circuit 100, there is a compliance test. In this compliance test, a compliant pattern recommended by SATA is output onto a SATA cable, and a signal waveform or the like is evaluated. Specifically, for example, a SATA connector is converted into an SMA cable, and a signal is measured with an oscilloscope of 10 GHz or more to evaluate signal jitter, eye pattern, and the like.

  FIG. 6A shows the format of the compliant pattern. The compliant pattern includes an SOF primitive, a test pattern (specified test pattern), a CRC, and an EOF primitive. FIGS. 6B, 6C, 7A, 7B, and 7C show examples of test patterns described in the SATA II standard.

  FIG. 6B is an example of a low transition density bit pattern (LTDP) starting from RD-, which is negative running disparity. LTDP is a low transition test pattern in which 0 and 1 continue for a long time, and is a test pattern intended to create high frequency jitter due to intersymbol interference. There is also an LTDP that starts from RD +, which is positive running disparity.

  FIG. 6C is an example of HTDP (High Transition Density bit Pattern) starting from RD-. HTDP is a high transition test pattern in which 0 and 1 change in a short cycle, and is a test pattern intended to create high frequency jitter due to intersymbol interference. Some HTDPs start from RD +.

  FIG. 7A shows an example of LFSCP (Low Frequency Spectral Content Pattern) starting from RD +. LFSCP is a test pattern suitable for an input test of a high-pass filter circuit. In a transmitter having low performance, signal degradation occurs due to transmission of this test pattern.

  FIG. 7B is an example of LBP (Lone-Bit Pattern) starting from RD− or RD +. The LBP is a test pattern including a continuous combination of predetermined 10-bit patterns.

  FIG. 7C is an example of SSOP (Simultaneous Switching Outputs Bit Pattern) starting from RD− or RD +. SSOP is a test pattern suitable for testing a receiver by causing differential noise or the like on a substrate. In addition to the test patterns shown in FIGS. 6B to 7C, various patterns such as COMP (Composite Pattern) can be considered.

  The test control unit 150 in FIG. 4 selects and instructs a test pattern generated by the pattern generator 52 from the test patterns in FIGS. 6B to 7C. Then, the pattern generator 52 generates a test pattern instructed to be selected. The scrambler 54 scrambles the test pattern, and the scrambled test pattern is input to the data scrambler 56 via the selectors 61 and 62. Then, the data scrambler 56 performs the scramble process again on the test pattern after the scramble process, so that the scrambled test pattern returns to the original unscrambled test pattern. Also, the CRC calculation unit 58 calculates the CRC of the test pattern after the scramble process, and adds a CRC (CRC code) to the end of the test pattern as shown in FIG. A primitive generator (not shown) adds SOF and EOF primitives to generate a compliant pattern as shown in FIG. 6A and output it to the physical layer circuit 100.

  FIG. 8 shows a configuration example of a data transfer control device of a comparative example. If a compliance test is to be realized with the configuration of the comparative example of FIG. 8, there are the following problems.

  That is, in the SATA standard, the compliant pattern test pattern needs to appear on the SATA cable (serial bus) as a bit string having a pattern that is not scrambled. On the other hand, in the SATA standard, transmission data is scrambled.

  As a first method for realizing the compliance test with the configuration of the comparative example in FIG. 8, a method in which a CPU or the like inputs a test pattern to the link controller 550 from the outside of the link controller 550 can be considered. However, according to this first method, the input test pattern is scrambled by the data scrambler 556, and the bit string of the test pattern as expected as shown in FIGS. Will no longer appear on the cable. Therefore, it is necessary to generate a test pattern so that the test patterns shown in FIGS. 6B to 7C appear on the SATA cable in a scrambled state, and the test pattern generation process is complicated. become. Therefore, an unnecessary load is applied to the processing of the CPU and the like, and a data transfer control device suitable for an electronic device such as a home appliance cannot be realized.

  On the other hand, as a second method for realizing the compliance test with the configuration of the comparative example of FIG. 8, a method of directly inputting an unscrambled test pattern to the physical layer circuit 500 of FIG. 8 using a test circuit or the like. Can be considered. However, in the case of a compliant pattern, as shown in FIG. 6A, it is necessary to calculate the CRC and add it to the end of the test pattern. Therefore, with this second method, CRC calculation becomes extremely difficult.

  In this regard, in the present embodiment of FIG. 4, the pattern generator 52 generates a compliant pattern test pattern, and the scrambler 54 performs scramble processing of the generated test pattern. Then, the data scrambler 56 performs the scramble process again on the test pattern after the scramble process, so that the scrambled test pattern returns to the original unscrambled test pattern. Therefore, the original test pattern as expected as shown in FIGS. 6B to 7C appears on the SATA cable, and an appropriate compliance test can be realized.

  In the present embodiment of FIG. 4, the CRC calculation unit 58 calculates the CRC of the test pattern after the scramble process and adds it to the tail. Therefore, it is possible to realize a process of calculating and adding a CRC with the same control flow as in the case of normal transmission data, and to simplify the CRC calculation process and the control flow.

  For example, it is assumed that the data transfer control device is set to the loopback mode and the TX block receives the transmission data of the TX block. In this case, the data descrambler 70 performs a descrambling process on the unscrambled test pattern, so that the data descrambler 70 eventually outputs a scrambled test pattern. The CRC calculator 72 calculates the CRC of the scrambled test pattern and performs a CRC check. Therefore, the CRC calculation results on the transmission side (TX block) and the reception side (RX block) match, so that a correct CRC check can be performed.

4). CONT Primitive In this embodiment, as shown in FIG. 4, a scrambler for CONT primitive is effectively used as the scrambler 54. Thereby, an increase in the circuit scale of the data transfer control device can be minimized.

  First, the primitive will be described. The primitive is a Dword entity for providing serial line control and status, and starts with a control character. Specifically, primitives other than the ALIGN primitive start with a control character of K28.3, and K28.5 becomes a control character dedicated to the ALIGN primitive. In the primitive, following these control characters, three data characters for completing Dword are added.

  In SATA, a CONT primitive is prepared to avoid the occurrence of EMI following the same control code. With this CONT primitive, repetition of the same primitive is removed, and EMI can be reduced. The receiving side that has received the CONT primitive ignores all data received following the CONT primitive until it receives other primitives (except for the ALIGN primitive). After transmitting the primitive, the transmitting side transmits scrambled data (junk data) until the next primitive is transmitted.

  For example, in A1 of FIG. 9, the transmission side makes a transmission request to the reception side by the X_RDY primitive. Since the X_RDY primitive continues two or more times, a CONT primitive is transmitted as indicated by A2. Thereafter, as shown in A3, scramble data (junk data) is transmitted.

  The receiving side accepts reception by the R_RDY primitive as shown at A4. Since the R_RDY primitive continues two or more times, a CONT primitive is transmitted as shown in A5.

  Next, as shown in A6, A7, and A8, the transmitting side first transmits an SOF primitive, then transmits DATA including the FIS type indicated by TYPE informing the FIS type, and then transmits FIS DATA. To do.

  The receiving side transmits an R_IP primitive informing that reception is in progress as indicated by A9, and transmits a CONT primitive because the R_IP primitive continues two or more times as indicated by A10. In A11, the transmission side issues a pause request using the HOLD primitive, and then transmits a CONT primitive as shown in A12. As shown at A13, the receiving side returns an acknowledge with a HOLDA primitive.

  Thereafter, the transmission side transmits a HOLD primitive as shown in A14 to cancel CONT, and resumes the transmission of DATA as shown in A15. Then, the CRC of DATA is calculated and output as indicated by A16, and the EOF primitive is transmitted as indicated by A17. Then, while waiting for the reception status from the reception side, the WTRM primitive is transmitted. Since the WTRM primitive continues twice or more, a CONT primitive is transmitted as shown in A19. As shown in A21, the receiving side transmits an R_OK primitive notifying that the payload has been normally received without error. Then, as shown in A22 and A23, when the transmitting side sends a SYNC primitive and the receiving side also sends a SYNC primitive, the state shifts to an idle state. Also at this time, since the SYNC primitive continues twice or more, the CONT primitive is transmitted as shown in A24 and A25.

  When the CONT primitive is used in this way, it is necessary to generate scramble data to be transmitted following the CONT primitive. Therefore, in the present embodiment of FIG. 4, the scrambler 54 generates scramble data following the CONT primitive during normal operation, thereby realizing the function of the CONT primitive scrambler 554 of FIG. That is, the scrambler 54 outputs scramble data (junk data) to the selector 63 after the CONT primitive is output.

  On the other hand, the CONT primitive is not required during testing. Therefore, in this embodiment, the CONT primitive scrambler 54 is effectively used as a test pattern scrambler. That is, the scramble process for the test pattern from the pattern generator 52 is performed using the scramble data generated for the CONT. This eliminates the need to newly provide a test pattern scrambler, thereby minimizing the increase in the circuit scale of the data transfer control device.

  According to the data transfer control device of the present embodiment as described above, the test pattern conforming to the standard is generated by the pattern generator 52 realized by random logic or ROM. Therefore, the compliance test can be realized without requiring complicated control by software, and the processing load of the CPU or the like can be reduced.

  In addition, by automatically scrambling the test pattern twice, the expected test pattern appears on the SATA cable. Further, since the circuit for scrambling the test pattern reuses the CONT primitive circuit originally provided in the data transfer control device, it is possible to prevent an increase in hardware scale and cost.

  In addition, the present embodiment has an effect that a compliance test and evaluation can be realized with simple control and a small number of terminals.

5). Electronic Device FIG. 10 shows a configuration example of the electronic device of the present embodiment. This electronic device includes the data transfer control device 310, the processing unit 330 (CPU), the ROM 340, the RAM 350, the display unit 360, and the operation unit 370 described in the present embodiment. Moreover, the device 320 connected with the data transfer control apparatus 310 via SATA can be included. Note that the configuration of the electronic device of the present embodiment is not limited to that shown in FIG. 10, and modifications may be made by omitting some of the components shown in FIG. 10 or adding other components.

  In FIG. 10, a device 320 is a storage device such as an HDD (hard disk drive). However, the device 320 is not limited to a storage device such as an HDD.

  The processing unit 330 (CPU) performs overall control of the data transfer control device 310 and the electronic device. A processing unit that controls the data transfer control device 310 and a processing unit that controls the electronic device may be provided separately. The ROM 340 stores control programs and various data. The RAM 350 functions as a work area and a data storage area for the processing unit 330 and the data transfer control device 310. The display unit 360 displays various information to the user. The operation unit 370 is for the user to operate the electronic device.

  Various electronic devices such as an HDD recorder, a video camera, an audio device, a portable music player, a portable video player, a game device, or a portable game device can be considered as electronic devices to which the present embodiment can be applied.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are included in the scope of the present invention. For example, a term (SATA, CPU, etc.) described together with a different term (serial bus, processing unit, etc.) in a broader sense or the same meaning at least once in the specification or drawing is used in any place of the specification or drawing. Can be replaced with a different term. Further, the configuration and operation of the data transfer control device and the electronic device are not limited to those described in the present embodiment, and various modifications can be made. In the present embodiment, the application example of the present invention to SATA has been described. However, the present invention is based on a standard based on the same idea as SATA, a standard developed from SATA (SATA I, SATA II, SAS), or the like. It can also be applied to.

Explanatory drawing of the layer structure of the SATA protocol. Explanatory drawing of the data processing of the transmission side of SATA. Explanatory drawing of the data processing by the side of SATA reception. 1 is a configuration example of a data transfer control device according to the present embodiment. 5A and 5B are configuration examples of a data scrambler and a data descrambler. 6A shows an example of a compliant pattern format, and FIGS. 6B and 6C show examples of a test pattern of a compliant pattern. 7A, 7B, and 7C are examples of compliant pattern test patterns. 2 is a configuration example of a data transfer control device of a comparative example. Explanatory drawing of CONT primitive etc. Configuration example of an electronic device.

Explanation of symbols

10 transport controller, 50 link controller,
52 pattern generator, 54 scrambler, 56 data scrambler,
60 8b / 10b encoder, 61, 62, 63 first, second, third selector,
70 data descrambler, 72 CRC calculation unit, 74 8b / 10b decoder,
100 physical layer circuit, 110 transmitter, 120 receiver

Claims (11)

A data transfer control device for transferring data via a serial bus,
A pattern generator that generates compliant pattern test patterns;
A scrambler that performs scramble processing;
Including a data scrambler that scrambles the transmission data and outputs the scrambled data,
The scrambler is
When performing a compliance test using a compliant pattern, the test pattern from the pattern generator is scrambled,
The data scrambler is
A data transfer control device, wherein the test pattern after scramble processing from the scrambler is scrambled and outputted at the time of the compliance test. In claim 1,
A CRC calculation unit for transmission that calculates a CRC of transmission data and outputs the CRC to the data scrambler;
The CRC calculation unit for transmission is
A data transfer control device that calculates a CRC of a test pattern from the pattern generator and outputs the CRC to the data scrambler during the compliance test. In claim 2,
A first selector in which transmission data is input to the first input terminal, and a test pattern after scramble processing from the scrambler is input to the second input terminal;
The output of the first selector is input to the first input terminal, the output of the CRC calculation unit for transmission is input to the second input terminal, and the data to the data scrambler is output to the output terminal. A data transfer control device comprising a second selector. In claim 3,
The output of the data scrambler is input to the first input terminal, the output of the scrambler is input to the second input terminal, and the data to the physical layer circuit is output to the output terminal. A data transfer control device comprising a selector. In any one of Claims 1 thru | or 4,
The scrambler is
A scrambler that generates scrambled data following a continue primitive. In any one of Claims 1 thru | or 5,
A data transfer control device comprising an 8b / 10b encoder which is provided between the data scrambler and the physical layer circuit and performs 8b / 10b encoding processing. In any one of Claims 1 thru | or 6.
A data transfer control device comprising: a test control unit that instructs a test pattern generated by the pattern generator to a pattern generator from a plurality of test patterns. In any one of Claims 1 thru | or 7,
A data descrambler that performs descrambling of the data received by the physical layer circuit;
A data transfer control device comprising a reception CRC calculation unit for calculating a CRC of data after descrambling. In claim 8,
A data transfer control device comprising an 8b / 10b decoder provided between a physical layer circuit and the data descrambler and performing 8b / 10b decoding processing. In any one of Claims 1 thru | or 9,
The data transfer control device, wherein the serial bus is a serial ATA (Serial AT Attachment) bus. A data transfer control device according to any one of claims 1 to 10,
A processing unit for controlling the data transfer control device;
An electronic device comprising:

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