JP5252292B2 - Interface device and electronic device - Google Patents

Description

  The present invention relates to an interface device and an electronic device, and more particularly to an interface device and an electronic device having a serial interface using the PCI Express (PCIe) standard.

  A PC (personal computer) is provided with various I / Fs (interfaces) corresponding to each device so that various peripheral devices can be connected inside and outside and the storage capacity and functions can be increased. Motherboards, which are the main components of PCs, have various I / Fs for connection to external devices. Typical examples are portable music players, memory devices, external hard disks, printers, scanners. USB (Universal Serial Bus) that performs data transfer with a PCI bus that can add various I / F functions in the form of an interface card in response to low-speed to high-speed data transfer. In addition to F, there are dedicated I / Fs for limited applications such as SATA (Serial ATA) for adding HDDs and LAN connection.

  PCs often use interface cards when connecting to various peripheral devices, networks, etc., but as the mainstream interface card standards, desktop-type PCs include board-shaped PCI buses and PCIs. A PCI-X bus that has been upgraded to a higher speed and a PCIe that is further increased in speed by serialization can be used. PCIe is a serial-based I / O (input / output) standard, like USB, IEEE1394, SATA, Hiper-Transport, InfiniBand, and the like.

  The PCI standard is an industry standard architecture developed by PCI Special Interest Group (PCI-SIG) and has been continuously improved since version 2 of 1993, for 32-bit buses and 64-bit CPUs. This is a parallel bus that also includes the definition of a 64-bit bus, the bus clock is 33 MHz at the maximum, and the transfer rate is 132 bytes / second (peak value) with a 32-bit data bus. As an interface card for a PC, an example such as Patent Document 1 is sometimes seen.

  The PCI Express (PCIe) standard is a conventional parallel transfer PCI bus, which is a PCI bus that has been expanded from the PCI-X bus, which has been expanded to expand the PCI bus standard. This is the biggest difference. The PCIe standard employs a low-voltage differential serial signal system of 0.8V and connects devices by point-to-point (one-to-one). The number of pairs called lanes can be increased as needed, and the standard has a one-way 2.5 Gbps transfer capability per lane, and a configuration up to 32 lanes is specified, making the bandwidth scalable. The physical layer (PHY) that can be expanded has its characteristics.

  The PCIe standard employs a hierarchical architecture that was not found in the conventional PCI standard, and has a configuration similar to the structure of the network standard, such as serial transfer and transfer in packet units. The specifications of the medium and the implementation (mechanism) are changed from those defined collectively, and are defined by being divided into a transaction layer, a data link layer, and a physical layer. The transaction layer prescribes message transmission / reception and interrupts, the data link layer prescribes CRC (cycle redundancy check), packet loss, and retry in case of error, and the physical layer sends / receives and initializes packets, which are the minimum transfer unit. Specifies the configuration.

  When connecting an external device (peripheral device to be externally connected) with such an interface card, the interface card generally includes a circuit for interfacing with the inside of the PC and a circuit for connecting with the external device. (Application part). Conventionally, the interface portion with the PC has been transferred with parallel signals such as a PCI bus or a PCI-X bus. However, in the PCIe standard, the interface with the PC is a physical layer called PHY (Serize Deserialize). This is done by serial transfer defined by the lowest layer (first layer) of the OSI hierarchical model.

  The case where data is transmitted / received between an external device and a PC will be described. Data transmitted from an external device to a PC is transferred to an interface card mounted on the PC through a cable connection, and transmitted from the interface card mounted on the PC. Sent to the motherboard of the PC. In the opposite case, data is transmitted from the PC motherboard to the external device via the interface card. At that time, as an application, if an interface card for a network, IEEE802.3 is mounted, and if it is a digital video, an interface such as IEEE1394 is incorporated. If the application is video compression, a video data compression circuit is mounted on the interface card, and the data is transferred to a necessary memory or the like via the motherboard of the PC.

  When listing examples of combinations of these main interface cards, in the case of a network card, the external device is a LAN, a HUB, or the like, and the cable transfer method is IEEE802.3ab (1000Base-T) or the like. In the case of a SATA-compatible RAID (Redundant Array of Inexpensive Disks) card, the external device is an HDD (Hand Disk Drive), and the cable transfer system is SATA (serial system such as 1.5G). In the case of a video capture card, the external device is an analog VTR, the cable transfer method is RS-170 / NTSC, etc., and the interface card performs Video MPEG2 (Moving Picture Experts Group phase 2) conversion. In the case of a DVC capture card, the external device is a DVC (digital video camera), and the cable transfer method is IEEE1394. In the case of industrial camera capture, the external device is an industrial camera, and the cable transfer method is mostly a dedicated method, and the interface card encodes and decodes data of this dedicated method and connects to the PC. In the medical X-ray apparatus, the external device is a medical X-ray apparatus, the cable transfer method is a dedicated method using an optical cable, and the interface card is a dedicated method for encoding and decoding data and optical-electrical signal conversion. To connect to a PC.

  As described above, such an interface card is often used to connect an external device and a PC, and is used as an external input / output (I / O) of the external device to connect the external device and the PC. It can also be said that various electric signals, communication methods, and the like are converted into PCI or PCIe, which is I / O of a PC, by an interface card. The PC interface card mounting method is large: (1) a single-chip LSI system in which simple network protocols such as NIC are integrated into a single-chip LSI and mounted as an interface card, and (2) a PC side of PCI or PCIe. (3) A built-in application system in which an application part is mounted on one FPGA by using an FPGA (programmable logic circuit: program rewritable ASIC), etc. 4) The I / O portion and the application can be divided into device separation methods realized by separate LSIs and FPGAs. When the interface on the PC side is PCIe, generally, an expensive device equipped with high-speed SerDes is required to mount the physical layer with FPGA.

  On the other hand, since the PC interface card connects the PC and the external device with a cable, it can be considered that the I / O of the external device is converted to perform processing for each application and interface with the PC. When connecting a dedicated external device such as an HDD or monitor, the interface card has a cable transfer method and protocol compatible with SATA for HDD and DVI for monitor and liquid crystal display, and each processing (processing by application) Connected to the PC via the PCI or PCIe.

  Therefore, in the case of transferring data and control signals via a cable in a PC or an external device, if the cable length is long, a network transfer method such as LAN or the like uses a protocol with high transfer reliability such as TCP / IP. In many cases, the PATA connection between the above-mentioned SATA, DVI, various peripheral devices, external devices, etc. and the PC does not use a protocol that requires a retransmission request, and only transfers data by physical connection. There are many cases to do.

  For example, when a DVI monitor is connected by inserting a PCIe standard graphic card into a PC, data transfer according to the DVI standard used for connecting a liquid crystal display is based on the physical layer (TMDS: differential serial transfer) of the graphic card. Although video data is mainly transferred and there is a communication protocol for automatically determining what kind of monitor is connected, there is no advanced communication protocol for performing data retransmission by collision detection or the like. In such a case, it should be noted that the connection between the graphic card and the liquid crystal display is a connection between physical layers that perform cable transfer.

  The physical layer used for this transfer uses a differential serial transfer method called TMDS in the DVI standard, and the differential serial transfer method is also used in iLINK (IEEE 1394), but the video signal of STD-TV is When connecting to an external device, such as analog NTSC or composite, etc., match the I / O specification of the device, or if adopting a new specification, use, distance, transfer speed, cable cost to be used, etc. Depending on the type of transfer, which transfer method to use is determined.

Japanese Patent Laid-Open No. 08-288877

  By adopting PCIe in the PC, it becomes possible to mount an interface card that can realize high-performance and high-speed signal transfer, although the cost is rather high. However, in the method of mounting the interface card on the PC in the conventional form as described above, it is necessary to overlap the physical layer for cable connection on both the interface card and the external device. There is a problem that the configuration is useless, the system is complicated, and the cost is increased.

  Therefore, the present invention intends to improve efficiency by using the PCIe standard physical layer for signal transfer between an interface card mounted on a PC (or control device) and an external device (an externally connected electronic device). In particular, a control signal such as a reset signal from a PC (or control device), which was separately required from a conventional PCIe standard signal, is superimposed and transferred in a PCIe standard packet signal. An object of the present invention is to provide an interface device and an electronic device having a PCIe interface that can realize high-speed and high-efficiency signal transfer while simplifying the configuration of the interface card.

  In order to achieve the above object, an interface device according to the present invention is connected to a first interface unit having at least a physical layer of a PCIe (PCI Express) standard connected to the first electronic device, and to the second electronic device. A second interface unit having at least a PCIe standard physical layer and a metal cable connector for transferring a signal by an electrical signal for connecting between the first and second interface units, or a signal transfer by optical communication At least an optical transmission module including an optical transceiver and an optical communication cable connector, and the first interface unit transmits a second signal other than the PCIe standard serial signal from the first electronic device. The PCIe standard serial signal received from the first electronic device. Signal superimposing means for incorporating the second signal into a packet signal and transmitting the packet signal on which the second signal is superimposed to the second interface unit, wherein the second interface unit includes the second interface unit When the packet signal received from one interface unit is read and the second signal is detected in the packet signal, the second signal is extracted and the second signal is sent to the second electronic device. It has the signal extraction means to transmit, It is characterized by the above-mentioned.

  An interface device according to the present invention made to achieve the above object includes a first interface unit having at least a physical layer of PCIe (PCI Express) standard connected to the first electronic device, and a second electronic device. A second interface unit having at least a PCIe standard physical layer to be connected to the connector and a metal cable connector for transferring a signal by an electrical signal for connecting between the first and second interface units, or a signal by optical communication And an optical transmission module including an optical transceiver for transferring and an optical communication cable connector, and the first interface unit detects the reset signal from the first electronic device when the first electronic device detects the reset signal. Incorporate the reset signal into the packet signal received from the Reset signal superimposing means for transmitting the folded packet signal to the second interface unit; the second interface unit reads the packet signal received from the first interface unit; And a reset signal generating means for generating a reset signal for resetting the second electronic device when a reset signal is detected.

Furthermore, an interface device according to the present invention made to achieve the above object includes a first interface unit having at least a physical layer of a PCIe (PCI Express) standard connected to the first electronic device, and a second electronic device. A second interface unit having at least a PCIe standard physical layer to be connected to the connector and a metal cable connector for transferring a signal by an electrical signal for connecting between the first and second interface units, or a signal by optical communication And an optical transmission module including an optical transceiver for transferring and an optical communication cable connector, and the first interface unit detects a reset signal superimposed on a packet signal and transmitted from the first interface unit An inquiry signal as to whether or not it can be transmitted to the second interface unit A reset detection inquiry means for receiving the response signal, and a response indicating that the reset detection inquiry means can detect the reset signal from the second interface unit, and the reset signal is detected from the first electronic device. A reset signal superimposing unit that incorporates the reset signal in the packet signal received from the first electronic device and transmits the packet signal superimposed with the reset signal to the second interface unit. It is characterized by.
Here, when the second interface unit receives the inquiry signal from the first interface unit, a response indicating that a reset signal superimposed on a packet signal received from the first interface unit can be detected. A reset signal for transmitting a signal to the first interface unit and generating a reset signal for resetting the second electronic device when a reset signal is detected in the packet signal received from the first interface unit It has the generation means.
In addition, the second interface unit includes clock recovery means for recovering and generating a clock signal based on the packet signal and the external reference signal.
Further, the first and second interface units include a transmission compensation circuit for extending a transmission distance in signal transfer.
In addition, the first and second interface units have a multilink function of performing signal transfer with a single electronic device using a plurality of lanes.
The first or second interface unit may further include a PCIe standard-compliant HUB device that is connected to a plurality of electronic devices and performs signal transfer of a plurality of channels.

  In order to achieve the above object, an electronic device according to the present invention includes a PCIe standard physical layer connected to a control device, an interface unit having at least a PCIe control unit for controlling signal transfer based on the PCIe standard, and an electronic device main body. And a main body control unit for connecting and transferring signals by mutually converting communication standards between the interface unit and the interface unit, and the PCIe control unit receives packets from the control unit via the interface unit When the signal is read and the reset signal is detected in the packet signal, the apparatus has a reset signal generating means for generating a reset signal for resetting the electronic apparatus main body.

According to the present invention, the interface configuration of an interface card or external device can be simplified by connecting and transmitting signals between a PC and an external device (an externally connected electronic device) using a PCIe standard physical layer. It can be simplified as a connector board type that can reduce the logic on the interface card mounted on the PC, and the interface card can be a common card unrelated to the types of various external devices.
In addition, the transmission system between the PC and the external device is speeded up by superimposing and transmitting a control signal such as a reset signal not included in the PCIe standard on the packet signal of the PCIe standard between the PC and the external device. However, there is an effect that the configuration can be simplified in the cable connection. At that time, it is determined whether or not to superimpose the sideband signal depending on whether or not the external device has a function capable of detecting a sideband signal such as a reset signal superimposed on the packet signal. The possibility of malfunctioning can be eliminated.
Furthermore, when an optical communication cable is used, the anti-noise performance can be improved and a long-distance connection between devices can be achieved.

1 is a configuration diagram of an interface device and an electronic device according to an embodiment of the present invention. It is a block diagram of the interface part (1) shown in FIG. It is a block diagram of the interface part (2) shown in FIG. It is another block diagram of the interface part (1) shown in FIG. It is another block diagram of the interface part (2) shown in FIG. It is a block diagram using a transmission compensation circuit. It is a block diagram of the PtoN transmission system using PCIe corresponding | compatible HUB. It is the block diagram which aggregated the PCIe signal. It is a block diagram of the camera system by one Example of this invention. It is a schematic block diagram of the conventional camera system. It is a block diagram which superimposes a reset signal on the camera system shown in FIG. It is a block diagram of the conventional camera system.

Explanation of symbols

1, 11 Interface (I / F) unit having physical layer of PCIe standard 2, 12 PCIe control unit 3, 13 Serial-parallel conversion unit 4, 4a Reset K code conversion unit 5, 15 Parallel-serial conversion unit 6, DESCRIPTION OF SYMBOLS 16 Electrical-optical conversion part 7, 17 Optical-electrical conversion part 10 Signal transmission cable 10a Optical communication cable 10b Coaxial cable 14, 14a Idle K code conversion part 18 PCIe device 19 Main body control part 21 Optical transceiver 22 Transmission compensation circuit 23 Coaxial Connector 24 PCIe HUB
25 PCIe x 4 in 10 Gbps conversion 26 10 Gbps optical transceiver or InfiniBand x 4 connector 101 PCIe compatible interface card 102 Electronic device (external device)
103 Industrial CCD camera 104, 112 Camera control unit 105 Oscillator (OSC)
106 Power-on reset circuit 107 Reset switch 110 Conventional PCIe compatible interface card 111 PCIe control and conversion unit 113, 114 LVDS driver & receiver

The best mode for carrying out the present invention will be described below with reference to the drawings.
1 is a configuration diagram of an interface device and an electronic device according to an embodiment of the present invention, FIG. 2 is a configuration of the interface unit (1), and FIG. 3 is a configuration of the interface unit (2). . In the present embodiment, a reset signal (control signal) is taken as an example of the second signal other than the PCIe standard signal, and the second electronic device (with the reset signal superimposed on the PCIe standard serial signal packet) is used. A case of transmission to an external device will be described.

  In FIG. 1, reference numeral 101 denotes a PCIe compatible interface card connected to a PCIe bus mounted on a control device (first electronic device) configured by a PC or a computer system. The first interface unit (on the card) 1) It has 1. Reference numeral 102 denotes a second electronic device (external device) that is externally connected to a PC or a control device via a signal transmission cable 10 such as an optical communication cable, a coaxial cable, or a twist cable via an interface card 101. Interface unit (2) 11, a PCIe device 18 that transmits and receives PCIe signals, and a main body control unit 19 that controls the main body of the electronic apparatus. The first interface unit (1) 1 includes a first PCIe control unit (1) 2 for transmitting a reset signal (to be described later) superimposed on a packet signal, and a second interface unit (2) 11 Has a second PCIe control unit (2) 12 for extracting a superimposed reset signal from the packet signal transmitted from the first interface unit (1) 1 and received via the signal transmission cable 10. .

  The functions in the first interface unit (1) 1 and the second interface unit (2) 2 corresponding to the PCIe standard are all functions including the main body control unit 19 of the electronic device 102, or a combination of individual functions. And implemented by one or a plurality of LSIs or FPGAs. Also, according to the PCIe standard (standard established in July 2002 ver. 1.1a), high-speed differential serial transfer of 2.5 Gbps per lane is performed. However, because of high speed, the total extension distance is extended with a metal cable. There are limits. Therefore, to increase cable transmission efficiency, adopt cables and connectors with high transmission efficiency, adopt optical transmission modules that perform OE (optical-electrical) conversion, and add transmission compensation circuits etc. in cable transmission. Thus, stable cable transmission can be realized.

  As shown in FIG. 2, the first interface unit (1) 1 according to the present embodiment has a first PCIe control unit (1) 2 and a second interface unit (2) provided on the electronic device 102 side. And an electrical-optical conversion unit 6 and an optical-electrical conversion unit 7 for communication connection via the optical communication cable 10a. The PCIe interface card 101 having the first interface unit (1) 1 inserted into the PCIe bus of the PC includes a PCIe signal (Tx) of a serial packet signal transmitted from the PC and received by the electronic device 102, and the electronic device In addition to the PCIe signal (Rx) of the serial packet signal transmitted from 102 and received by the PC, each sideband signal of a reference clock RefCLK signal and a reset Reset signal not included in the PCIe standard signal is supplied.

  The physical layer of PCIe can be divided into two logical sub-blocks that perform coding and link control and electrical sub-blocks that perform signaling. In the logical sub-block, the data sub-layer is passed from the data link layer by framing processing. A special code (K code) indicating a packet boundary is added to the TLP (Transaction Layer Packet) or DLLP (Data Link Layer Packet) at the beginning and end. In the case of TLP, the STP (Start of TLP) added to the beginning. ) To 1 end of the END appended to the end, there are cases where 1 to 3 K codes called PADs are inserted between TLP and END.

  The data divided into each lane is scrambled and 8b / 10b converted (8 bits / 10 bits converted) for each lane, and transmitted as serial data. 8b / 10b conversion has the demerit that the effective transfer amount will be 80%, but the continuous “0” and “1” will not continue for a long time without a crosspoint. Thus, it has features such that clock reproduction can be performed easily and AC coupling is possible because of DC balance. The code space is expanded by the 8b / 10b conversion, and a control code called a K code can be added here.

  Here, in the 8b / 10b conversion, each 8-bit bit is referred to as ABCDEFGH from the least significant bit (LSB) to the most significant bit (MSB), and is divided into two groups of EDCBA and HGF. The data is Dx. y, K code is changed to Kx. If y is, for example, when the data is 00110000b (binary) and the K code is 01111100b, the data is HGF = 001b and EDCBA = 10000b, so it can be expressed as D16.1, and the K code is HGF = 011b, Since EDCBA = 1100b, it can be expressed as K28.3.

  In the embodiment of the present invention, an undefined K code in the PCIe standard is assigned as a reset code. As shown in FIG. 2, the first PCIe control unit (1) 2 performs serial transmission of the PCIe standard. A PCIe signal (Tx) that is a signal is received, converted into a parallel signal by the serial-parallel converter 3, and a reset signal that is one of sideband signals not included in the serial signal transmitted in the PCIe standard. Is received from the PCIe bus, and this reset signal is converted into a K code defined for resetting in the K code portion and inserted as, for example, K24.4. Here, the PCIe signal (Tx) transmitted from the PC is a serial signal obtained by converting 8 bits of data by 8b / 10b, and the serial-parallel converter 3 performs parallel conversion to a 10 bits pattern including a K code into a D code. I do.

  The reset K code conversion unit 4 monitors the reset signal and the K code, and when detecting that the reset signal is active, an IDL (idle) K code indicating that there is no data to be transmitted on the serial bus (example: K28.3) is assigned and replaced with a K code (for example, K24.4) undefined in the PCIe standard, and this reset K code is superimposed on the Tx signal. The 10-bit pattern D code obtained by converting the K code and the transmission signal including the K code are converted back to a serial signal by the parallel-serial conversion unit 5 at the subsequent stage. The converted serial signal is converted into an optical signal suitable for the optical communication cable 10a by the electro-optical conversion unit 6, and is connected to the outside via the optical communication cable connector and the optical communication cable 10a (external device). ) 102 (reset signal superimposing means or signal superimposing means).

  As shown in FIG. 3, the optical signal that has reached the electronic device 102 is converted into an electric signal by the photoelectric conversion unit 17 provided in the interface unit (2) 11 provided on the electronic device 102 side. A reset signal is extracted from the converted serial signal by the PCIe control unit (2) 12, converted into the original serial signal, and delivered to the PCIe device 18 and the main body control unit 19. The PCIe control unit (2) 12 converts the received serial signal into a 10-bit pattern parallel code by the serial-parallel conversion unit 13, and delivers the signal to the idle K code conversion unit 14.

  The idle K code conversion unit 14 monitors the K code and, when detecting the K code assigned for reset, generates a reset signal for the PCIe device 18 or the main body control unit 19 and activates the signal. The reset K code (eg, K24.4) is replaced with the original IDL K code (eg, K28.3) and sent to the parallel-serial converter 15. The 10-bit pattern signal replaced with the original IDL K code is converted to the original serial signal via the parallel-serial conversion unit 15 and sent to the PCIe device 18. As a result, the PCIe device 18 can receive the PCIe signal (Tx) and perform an appropriate operation (reset signal generation means or signal extraction means).

  On the other hand, the PCIe signal (Rx) output from the PCIe device 18 side of the electronic apparatus 102 is converted into an optical signal by the electro-optical conversion unit 16 of the interface unit (2) 11, and the PC signal is transmitted via the optical communication cable 10a. It is transmitted to the interface card 101 side. The optical signal reaching the interface card 101 is converted into an electrical signal by the optical-electrical conversion unit 7 of the interface unit (1) 1 and delivered to the PCIe bus. Accordingly, the PC (or control device) can receive the PCIe signal (Rx) from the electronic device (external device) 102 and perform an appropriate operation.

  The reference clock (RefCLK, RefClock: 100 MHz) of the sideband signal shown in FIG. 1 and FIG. 2 is used as a clock signal for serial-parallel conversion and parallel-serial conversion of the PCIe control unit (1) 2. Although not shown, a clock signal actually required is generated by a DLL (Delay Locked Loop) or PLL (Phase Locked Loop) configuration.

  2 and 3, the serial-parallel conversion units 3 and 13, the reset or idle K code conversion units 4 and 14, and the parallel-serial conversion units 5 and 15 are configured by a FIFO (Firstst) using a shift register. Using the -In First-Out) buffer, the above-described reset signal superimposition or extraction processing is performed.

  On the electronic device 102 side, a clock signal is reproduced from the received serial signal and used as a clock signal for serial-parallel conversion and parallel-serial conversion of the PCIe control unit (2) 12, and the clock and data at that time are used. The recovery circuit and its operation are omitted (not shown in FIG. 3).

  When detecting a K code assigned for resetting, a function that activates a reset signal only when a K code is detected consecutively a predetermined number of times in order to avoid erroneous detection due to noise on the transmission path, etc. You may have it.

  Next, with reference to FIG. 4 and FIG. 5, a configuration and processing in the case of dealing with the electronic device 102 that cannot extract a sideband signal such as a reset signal superimposed in the received serial packet signal will be described.

  2 and 3 described above is whether or not the sideband signal superimposed in the serial packet signal can be detected before the sideband signal such as the reset signal is superimposed in the serial packet signal. Is inquired of the electronic device 102. In this way, it is possible to connect to an unspecified electronic device 102 by inquiring in advance whether or not the serial packet signal on which the sideband signal is superimposed can be processed. In this case, the present invention can be applied to a case where only a part of the sideband signals can be recognized, not whether or not all the sideband signals can be recognized. That is, the present invention can also be applied to the case where the K code assigned to the reset signal can be recognized but the unrecognizable K code assigned to another sideband signal cannot be processed. Hereinafter, a reset signal will be described as an example of the sideband signal.

  FIG. 4 shows a reset K code conversion in which the reset K code conversion unit 4 shown in FIG. 2 is replaced with a reset detection inquiry signal transmission function and a reset detection confirmation function (reset detection inquiry means) based on the response signal. It is one Example of the part 4a. Therefore, a detailed description of the same functions as those in FIG. 2 is omitted.

  The PCIe control unit (1) 2 on the PC side according to the present embodiment is connected for communication with the electronic device 102 via the optical communication cable 10a. The PCIe control unit (1) 2 receives a PCIe signal (Tx), which is a PCIe standard serial transmission signal, from the PC and converts the PCIe signal (Tx) into a parallel signal by the serial-parallel conversion unit 3. At this time, as a first packet signal transmitted from the PC side, an inquiry signal for inquiring whether or not a reset signal superimposed as a K code on the PCIe signal (Tx) can be detected is transmitted. When a response signal (ACK (Acknowledgement), etc.) cannot be obtained even after a predetermined time has elapsed from the electronic device 102 that has received the inquiry signal, or when a reference signal cannot be interpreted (NACK (Negative Acknowledgment), etc.) The reset K code conversion unit 4a does not superimpose the reset signal on the subsequent packet signal, and returns the original signal from the parallel signal to the serial packet signal by the parallel-serial conversion unit 5 and transmits it as it is.

  Here, the inquiry signal may be transmitted as a K code defined as the inquiry signal, or may be added before or after the first serial packet signal. Unlike the example of FIG. 4, it may be incorporated in the communication protocol as the first packet signal transmitted from the PC side. When the reset signal is not superimposed, the serial-parallel conversion unit 3 and the parallel-serial conversion unit 5 of the PCIe control unit (1) 2 may be passed.

  The electronic device 102 that has received the reset detection inquiry signal from the PC side transmits a reset detection response signal to the PC side in response to the inquiry signal from the PC side when it has a reset signal detection function. When the reset detection response signal is received from the electronic device 102 and it is determined that the electronic device 102 has a reset signal detection function, the reset K code conversion unit 4a on the PC side then transmits a serial signal transmitted in accordance with the PCIe standard. When a reset signal not included in the signal is received from the PCIe bus, a K code defined for reset is inserted into the K code portion in the serial packet signal transmitted from the PC and transmitted to the electronic device 102.

  Details of the confirmation of the reset detection response signal are not shown in FIG. 4, but are converted into parallel data by the serial-parallel conversion unit in the same manner as the processing on the electronic device 102 side shown in FIG. There are a method of returning to the original serial packet signal by the parallel-serial conversion unit and a method of directly interpreting the serial packet signal by a separately provided circuit. In the case of a configuration similar to the method shown in FIG. 3, a response signal can be assigned to the K code portion. Unlike the example of FIG. 4, the serial packet signal received on the PC side may be incorporated in the transmission / reception protocol so that it can be directly interpreted.

  FIG. 5 shows an idle K code conversion unit 14a in which the idle K code conversion unit 14 shown in FIG. 3 is replaced with a reset detection inquiry signal receiving function and a reset detection response function for generating the response signal. This is an example. Therefore, a detailed description of the same functions as those in FIG. 3 is omitted.

  The PCIe control unit (2) 12 on the electronic device 102 side according to the present embodiment is connected for communication from the PC side via the optical communication cable 10a. The optical signal that has reached the electronic device 102 is converted into an electric signal by the photoelectric conversion unit 17 on the electronic device 102 side, and converted into a parallel signal by the serial-parallel conversion unit 13 of the PCIe control unit (2) 12. In response to the reset detection inquiry signal, the idle K code conversion unit 14a of the electronic device 102 shown in FIG. 5 receives the reset detection inquiry signal as to whether or not the reset signal superimposed on the packet signal can be detected. A reset detection confirmation response signal is transmitted to the PC side. If a signal other than the reset signal that cannot be interpreted is received, NACK is returned. As described above, in the case of the electronic device 102 that does not have the function of detecting the reset signal superimposed in the received packet signal and cannot respond to the reset detection inquiry signal, the PC side has a response signal to the reset detection inquiry signal. Since it cannot be obtained even after a predetermined time has elapsed, the reset signal is not superimposed on the subsequent transmission packet signal.

  The PCIe control unit (2) 12 on the electronic device 102 side that has transmitted the reset detection confirmation response signal in response to the reset detection inquiry signal received from the PC side detects the reset signal superimposed in the packet signal received thereafter. Then, the reset signal superimposed on the packet signal is extracted by the idle K code conversion unit 14a shown in FIG. 5, and the reset K code is replaced with the idle K code and delivered to the PCIe device 18. When a K code assigned for resetting is detected, a reset signal for the PCIe device 18 or the main body control unit 18 is generated and the signal is activated. Here, the inquiry signal may be assigned as a K code, or may be configured to be added before or after the first serial packet signal. Further, unlike the example of FIG. 5, it may be incorporated in the communication protocol as the first packet signal at the time of transmission / reception with the PC side.

  FIG. 6 is a configuration diagram using a transmission compensation circuit for transmission of the above-mentioned PCIe standard serial signal, and shows a case where the transmission compensation circuit 22 adapted to the transmission speed and transmission distance of the PCIe standard is used. The transmission compensation circuit 22 is connected between the PCIe control unit (1) 2 of the interface unit (1) 1 and the coaxial connector 23, and between the coaxial connector 23 of the interface unit (2) 11 and the PCIe control unit (2) 12. By using such a transmission compensation circuit 22, the cable transmission distance can be extended even when the coaxial connector 23 and the coaxial cable 10b are used for signal transmission. In the embodiment shown in FIG. 6, the coaxial cable 10b is used for the transmission of the serial signal. However, when the optical communication cable 10a is used, the transmission compensation circuit can be applied by optimizing the optical communication cable. Is possible.

  In the PCIe standard, as described above, code conversion by 8b / 10b encoding is adopted so that a state where a cross point does not exist for a long time does not continue due to continuous “0” or “1”. Although the above restrictions have been relaxed, even if code conversion by 8b / 10b encoding is performed, a maximum of 5 consecutive “0” s or “1” s may continue. In the following case, when the second signal is transmitted, it is stipulated that de-emphasis transfer is performed on the transmission side so that the transmission side reduces the amplitude and increases the noise margin of the signal received on the reception side.

  FIG. 7 shows a case where signals are transmitted to a plurality of electronic devices 102 # 1 to # 4 using a plurality of lanes, and is a configuration diagram of a PtoN transmission method using a PCIe-compatible HUB device, and is compatible with PCIe. 1 shows a configuration in which one PC and a plurality (four in the figure) of electronic devices 102 # 1 to 4 are connected by using the HUB device. A PCIe compatible HUB 24 is mounted between the PCIe control unit (1) 2 on the interface card 101 side and the four optical transceivers 21 # 1 to 4, and the PCIe compatible HUB 24 transfers to the four optical transceivers 21 # 1 to 4 #. It branches and controls each electronic device 102 # 1-4 via each optical transceiver 21 in optical communication cable 10a and electronic device (external device) 102 # 1-4. Here, although the optical transceiver 21 and the optical communication cable 10a are used as the transmission method, a transmission method using the coaxial cable 10b can be realized. In this case, the reset signal may be transmitted by being superimposed on the packet signals for each of the four lanes, or may be transmitted only to the electronic devices 102 # 1 to 102 # 4 that are required.

  7 shows the PtoN configuration in which the PCIe compatible HUB 24 is provided on the PC interface card 101 side. However, the PCIe compatible HUB 24 is mounted on the electronic device 102 side, and each optical transceiver 21 # 1-4 ( 4) and connected to the optical transceiver 21 of the PCIe interface card 101 inserted into each PC # 1-4 via the optical communication cable 10a, and the data is transferred to each PC # 1-4. As opposed to FIG. 7, one electronic device 102 and one PC may be applied to a plurality of configurations.

FIG. 8 is a configuration diagram in which PCIe signals are aggregated, and is a configuration in which transmission using an optical communication cable or transmission based on the InfiniBand standard is used for serial transmission.
In the InfiniBand standard (communication standard promoted by an industry group), a composite cable and a high transmission efficiency connector that can extend 2.5 Gbps transmission per lane by 10 m are employed in order to increase the speed. Such commercially available collective cables and connectors can be used for PCIe cable transmission. The InfiniBand standard currently defines x1ch, x4ch, and x12ch composite cables and connectors. As an example of cable aggregation using this, in the case of FIG. 8, PCIe 4 (Tx +/−, Rx +/− × 4 ch) is transmitted using 4 channels of the InfiniBand standard, and InfiniBand × It is configured using a 4-channel aggregate cable.

  As a transmission using an InfiniBand standard cable, the case where a PCIe signal is directly placed on the cable has been described. However, in the case of using a high-speed interface, a signal of 2.5 Gbps per lane of PCIe is used using a plurality of lanes. The number of channels is collected, converted to a high-speed interface with an expanded signal band, and the signal is transmitted to the electronic device 102.

  For example, when 4ch of 2.5 Gbps signals are input, PCIe × 4 can be transmitted using the PCIe × 4 in 10 Gbps conversion 25 that is a high-speed interface that can be combined and converted into 10 Gbps differential serial data. In order to transmit 10 Gbps, OE (optical-electrical) conversion is performed by the optical transceiver 26 and transmission is performed by the optical communication cable 10a. However, since technological progress is fast, it may be possible to transmit 10 Gbps by a metal cable in the near future. It is expected enough. In this case, the reset signal does not need to be superimposed on the packet signals of all four lanes, and may be superimposed on any one lane.

  FIG. 10 is a block diagram of a conventional industrial CCD camera system connected to a conventional PCIe interface card 110 having a PCIe interface provided on the PC side for comparison. Up to now, general cable transmission has been described, but transmission using an interface having a physical layer of PCIe of the present invention is performed with a PC (or control device) using a specific product such as an industrial CCD camera 103. By using it for cable transmission to and from the electronic device 102, it is verified which part is actually cost-saving.

  FIG. 10 shows that when a conventional PCIe interface card (industrial camera capture card) 110 is configured, for example, an industrial CCD camera 103 that outputs a video of 2048 × 1024 dots × 30 fps × YUV 16 bits is captured by a PC using an optical transceiver. 2 is a general block diagram in the case of connection with a PCIe compatible interface card (PCIe standard) 110 for use.

  In this case, the video data from the industrial CCD camera 103 is 960 Mbps (120 MB / sec) by simple calculation of data that is easy to calculate. If 8b / 10b conversion for reducing errors in serial transmission is added, a transfer rate of 1.2 Gbps (150 MB / sec) is required at a minimum.

  An outline of the control operation along the data flow will be described. First, the industrial CCD camera 103 images the image sensor CCD sensor by driving the CCD with a CCD controller. The transmission control unit performs control so that the captured moving image data can be transmitted. In the 1.25 Gbps interface unit, the moving image data is converted into differential serial that drives the optical transceiver 21. A differential serial signal is transmitted from the optical transceiver 21 on the industrial CCD camera 103 side to the optical transceiver 21 of the PCIe interface card 110 on the PC side via the optical communication cable 10a. The PCIe compatible interface card 110 converts the differential serial signal into LVTTL (Low Voltage TTL) or the like through the 1.25 Gbps interface, and controls the transmission control unit so that the moving image data can be received. The bridge control unit performs control so that it can be transferred to the PCIe bridge, and the PCIe bridge performs PCIe conversion and transmits a PCIe standard signal to the PCIe connector of the PC motherboard on the PC side.

FIG. 9 is a block diagram of an embodiment in which the circuit of FIG. 10 is improved by moving the PCIe interface to the external device side, that is, the industrial CCD camera 103 side according to the present invention. The industrial CCD camera 103 shown in FIG. 9 takes an image by controlling an image sensor CCD sensor by a CCD controller. The bridge control unit performs control so that the imaging signal can be transferred to the PCIe bridge, the PCIe bridge performs PCIe conversion, and the PCIe interface signal is transmitted from the optical transceiver 21 via the optical communication cable 10a to the interface card 101 on the PC side. Transmit to the optical transceiver 21. The interface card 101 on the PC side transmits to the PC motherboard via the PCIe connector of the PC.
As described above, when the conventional configuration of FIG. 10 is compared with the components of FIG. 9 according to the present invention, the PC-side interface card 101 has a configuration of only an optical transceiver, so that significant cost savings can be realized.

Finally, an embodiment in which a reset signal is incorporated in signal transmission with the industrial CCD camera 103 described with reference to FIGS. 9 and 10 will be described with reference to the drawings.
FIG. 12 is a block diagram of a conventional camera system including a reset circuit, and FIG. 11 is a block diagram of a camera system according to an embodiment incorporating the reset circuit according to the present invention.
The PCIe standard itself allows signal transmission using only a total of four transmission / reception two signals, and as described above, a signal for clock transfer is not particularly required. A clock signal and a reset signal are provided as signals, and can be used as necessary. 11 and 12 show an example in which a camera system is configured using such a clock signal and reset signal.

  As shown in FIG. 12, in the conventional example, a PCIe control unit and conversion unit 111, a camera control unit 112 configured with an FPGA, an LVDS (Low Voltage Differential Signaling) driver and receiver 113 are installed in a camera-side interface card. It is provided as a camera capture card including a control unit, and is connected to an LVDS driver & receiver 114 also provided on the camera side by being extended by a camera cable of a proprietary standard.

  As shown in FIG. 11, the interface card 101 on the PC side includes a PCIe control unit (1) that superimposes a reset signal on the PCIe signal and an optical transceiver, and the OE (optical-electrical signal) conversion is the same as that on the camera side. Are connected to the optical transceiver 21 having a portion by the optical communication cable 10a. The signal based on the PCIe standard converted by the OE conversion unit of the optical transceiver 21 is transferred to the PCIe control unit (2) that extracts the reset signal and the conversion unit 12.

  The PCIe control unit (2) and the conversion unit 12 interpret the received packet sent from the PC side, and when a reset signal is detected in the received packet, extract the reset signal and generate it. At this time, the clock signal is reproduced based on the signal from the external oscillator (OSC 100 MHz) 105 and the received signal to receive the packet signal. The received packet signal is delivered to the camera control unit 104 through the local I / F (interface) together with the extracted reset signal.

  A reset signal from the PC (or control unit) extracted along with the received packet signal is transferred from the PCIe control unit (2) and the conversion unit 12 to the camera control unit 104. It has a function of generating a reset signal and resetting the camera control unit 104 itself. The camera control unit 104 is provided with a power-on reset circuit 106 and a reset switch 107 when the power is turned on. 4 and 5, first, a reset detection inquiry signal is transmitted from the PC side to the camera side, and a reset detection confirmation response signal is transmitted from the camera side to the PC side in response to the reset detection inquiry signal. Of course, it can be comprised.

  As described above, in the above-described embodiments, the case where the reset signal (sideband signal) is superimposed and transmitted as an example of the second signal other than the PCIe standard serial signal in the PCIe standard packet signal has been described. Besides this, it is possible to transmit a plurality of necessary control signals (sideband signals), and from the first electronic device (PC) to the second electronic device (external device) side. In addition to the transmission of signals, it is possible to superimpose and transmit necessary signals from the second electronic device (external device) to the second electronic device (PC), and also to superimpose both signals on the transmission and reception sides. It is also possible to make it bidirectional.

Claims (9)

A first interface unit having at least a physical layer of a PCIe (PCI Express) standard connected to the first electronic device;
A second interface unit having at least a PCIe standard physical layer connected to the second electronic device;
A metal cable connector for transferring a signal by an electrical signal for connecting between the first and second interface units, or an optical transmission module comprising an optical transceiver and a connector for an optical communication cable for transferring a signal by optical communication; At least,
When the first interface unit transmits a second signal other than the PCIe standard serial signal from the first electronic device, the PCIe standard serial signal packet signal received from the first electronic device. A signal superimposing means for incorporating the second signal therein and transmitting a packet signal on which the second signal is superimposed to the second interface unit;
The second interface unit interprets the packet signal received from the first interface unit, and when the second signal is detected in the packet signal, extracts the second signal and extracts the second signal. An interface device comprising signal extraction means for transmitting the second signal to the electronic device. A first interface unit having at least a physical layer of a PCIe (PCI Express) standard connected to the first electronic device;
A second interface unit having at least a PCIe standard physical layer connected to the second electronic device;
A metal cable connector for transferring a signal by an electrical signal for connecting between the first and second interface units, or an optical transmission module comprising an optical transceiver and a connector for an optical communication cable for transferring a signal by optical communication; At least,
When the first interface unit detects a reset signal from the first electronic device, the first interface unit incorporates the reset signal in a packet signal received from the first electronic device, and the packet signal on which the reset signal is superimposed A reset signal superimposing means for transmitting to the second interface unit,
The second interface unit reads the packet signal received from the first interface unit, and generates a reset signal for resetting the second electronic device when a reset signal is detected in the packet signal. An interface device comprising reset signal generating means for performing A first interface unit having at least a physical layer of a PCIe (PCI Express) standard connected to the first electronic device;
A second interface unit having at least a PCIe standard physical layer connected to the second electronic device;
A metal cable connector for transferring a signal by an electrical signal for connecting between the first and second interface units, or an optical transmission module comprising an optical transceiver and a connector for an optical communication cable for transferring a signal by optical communication; At least,
The first interface unit includes:
Reset detection inquiry means for transmitting an inquiry signal to the second interface unit and receiving a response signal as to whether or not a reset signal transmitted from the first interface unit can be detected by being superimposed on a packet signal;
A packet received from the first electronic device when there is a response from the second interface unit that the reset signal can be detected by the reset detection inquiry means and a reset signal is detected from the first electronic device; An interface device comprising: a reset signal superimposing unit that incorporates the reset signal in a signal and transmits a packet signal on which the reset signal is superimposed to the second interface unit. The second interface unit includes:
When the inquiry signal is received from the first interface unit, a response signal indicating that a reset signal superimposed on the packet signal received from the first interface unit can be detected is transmitted to the first interface unit. ,
4. A reset signal generating unit configured to generate a reset signal for resetting the second electronic device when a reset signal is detected in a packet signal received from the first interface unit. The interface device described in 1.   4. The interface device according to claim 1, wherein the second interface unit includes clock recovery means for recovering and generating a clock signal based on a packet signal and an external reference signal. 5.   The interface apparatus according to claim 1, wherein the first and second interface units include a transmission compensation circuit for extending a transmission distance during signal transfer.   4. The multi-link function according to claim 1, wherein the first interface unit and the second interface unit have a multilink function of performing signal transfer with a single electronic device using a plurality of lanes. Interface device.   The said 1st or 2nd interface part further has a HUB device corresponding to the PCIe standard which connects with a some electronic apparatus and performs the signal transmission of a some channel, The any one of Claim 1 thru | or 3 characterized by the above-mentioned. Interface device. An interface unit having at least a PCIe standard physical layer connected to the control device and a PCIe control unit for controlling signal transfer based on the PCIe standard;
A main body control unit that performs signal conversion by mutual conversion of communication standards between the electronic device main body and the interface unit; and
The PCIe control unit reads a packet signal received from the control device via the interface unit, and generates a reset signal for resetting the electronic device body when a reset signal is detected in the packet signal. An electronic device comprising signal generating means.