JP2012022477A - Communication unit and information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication unit which is provided between a first apparatus and a second apparatus and which can guarantee that a device for connecting the second apparatus to the first apparatus is in an operational state.SOLUTION: A PCI Express/optical cable conversion board comprises an electric type card edge 50, a PCI Express switch 51, two optical cable connectors 52a, 52b and a power supply delay circuit 53. The electric type card edge 50 is wired and connected to the PCI Express switch 51. The optical cable connectors 52 are connected to optical active cables 500 via optical transceivers 600. The power supply delay circuit 53 controls the start timings of the PCI Express switch 51, and the optical transceivers 600 connected to the optical active cables 500.

Description

  The present invention relates to a communication unit and an information processing apparatus.

  As a communication standard for data communication, for example, PCI Express (registered trademark) has been originally developed for the purpose of relatively short-distance host-device communication such as in the same housing of a computer such as a PC (Personal Computer). However, in recent years, applications for communication between different devices have been actively performed. For this reason, a communication standard (PCI Express External Cabling Specification) by cable connection has been established. However, in the communication based on the PCI Express External Cabling standard, an electric signal is transmitted as it is using a metal cable, so there is a restriction that the extendable distance is about 15 m at maximum. Therefore, it is already known that transmission over a longer distance can be realized by directly converting an electrical signal into an optical signal and transmitting the signal using an optical cable. However, if the distance over which signals can be transmitted is extended using an optical cable, a problem may occur in the reference clock. In order to solve such a problem, an optical conversion module that converts an electrical signal into an optical signal and has a PCI Express switch mounted on a conversion board to which an optical cable is connected has been developed (for example, Patent Document 1). reference).

  However, with a conversion board equipped with a conventional PCI Express switch, the PCI Express switch on the conversion board starts up and enters the link training sequence due to the difference in startup time between the PCI Express switch on the conversion board and the optical conversion module. In some cases, the optical conversion module was not ready for communication by the time it entered, and the PCI Express switch could not be linked up.

  This invention is made in view of the above, Comprising: In the communication unit provided between the 1st apparatus and the 2nd apparatus, For connecting a 2nd apparatus and a 1st apparatus It is an object of the present invention to provide a communication unit and an information processing apparatus that can guarantee that a device is operable.

  In order to solve the above-described problems and achieve the object, the present invention is a communication unit provided between a first device and a second device, which is connected to the first device, and A connection unit for supplying power supplied from the first device into the communication unit; a device for connecting the second device to the first device; and the second device via the device. A relay unit that relays a device and the first device via the connection unit, and an activation control unit that controls activation timing of the device and the relay unit.

  Moreover, this invention is an information processing apparatus, Comprising: Said communication unit is provided, It is characterized by the above-mentioned.

  According to the present invention, in the communication unit provided between the first device and the second device, the device for connecting the second device and the first device is in an operable state. Can be guaranteed.

FIG. 1 is a schematic configuration diagram of a print system according to the first embodiment. FIG. 2 is a diagram (part 1) for explaining a PCI Express tree in a server and a printer. FIG. 3 is a diagram (part 2) for explaining the PCI Express tree in the server and the printer. FIG. 4 is a diagram for explaining a transmission path between the server and the printer. FIG. 5 is a diagram illustrating an outline of the configuration of a PCI Express / optical cable conversion board used as the card adapter 300. FIG. 6 is a diagram illustrating an internal configuration of the power supply delay circuit 53. FIG. 7 is a diagram for explaining the activation timing of the PCI Express switch 51 and the optical transceiver 600 connected to the optical cable connector 52 when the power is turned on in the specification. FIG. 8 is a diagram for explaining the start timing of the PCI Express switch 51 and the optical transceiver 600 connected to the optical cable connector 52 when the power is turned on in the embodiment. FIG. 9 is a diagram illustrating the configuration of the power supply delay circuit 53 according to the second embodiment. FIG. 10 is a diagram for explaining the start timing of the PCI Express switch 51 and the optical transceiver 600 connected to the optical cable connector 52 when the power is turned on in the embodiment. FIG. 11 is a diagram illustrating the configuration of the power supply delay circuit 53 according to the third embodiment. FIG. 12 is a diagram for explaining the start timing of the PCI Express switch 51 and the optical transceiver 600 connected to the optical cable connector 52 when the power is turned on in the embodiment.

  Exemplary embodiments of a communication unit and an information processing apparatus according to the present invention will be explained below in detail with reference to the accompanying drawings.

[First embodiment]
FIG. 1 is a schematic configuration diagram of a print system 100 according to the present embodiment. The print system 100 according to the present embodiment includes a server 200, a printer 400, an optical active cable 500, a plurality of terminals 800, a network 900, and the like.

  The server 200 is a so-called print server, and is connected to a plurality of terminals (for example, PCs) 800 via a network 900. As shown in FIG. 2 as an example, each of the server 200 and the printer 400 includes a group of devices connected according to a tree structure topology defined by the PCI Express standard. As shown in FIG. 3 as an example, the tree-structure topology defined in the PCI Express standard is a tree-type configuration with the root complex at the apex, and a topology in which the root complex and the endpoint are connected. It is.

  As shown in FIG. 4, the server 200 has at least four sockets (PCI Express sockets 410) compliant with the PCI Express standard on its motherboard. Each PCI Express socket 410 is equipped with a card adapter 300 as a communication unit. Further, the printer 400 has at least four sockets (PCI Express socket 410) compliant with the PCI Express standard mounted on its motherboard. A card adapter 300 is attached to each PCI Express socket. Each card adapter 300 is attached with an optical transceiver 600 via a transceiver socket 312. The server-side optical transceiver 600 and the printer-side optical transceiver 600 are individually connected by an optical active cable 500. Here, in the present embodiment, the optical transceiver 600 has a function of transferring data via the optical active cable 500 and a function of converting an electrical signal that is a data transfer medium and an optical signal.

  Here, black image information, cyan image information, magenta image information, and yellow image information are individually transmitted from the server 200 to the printer 400 in the form of lossless compressed data of a raster image. The printer 400 forms a color image according to the received black image information, cyan image information, magenta image information, and yellow image information.

  Next, an outline of the configuration of the PCI Express / optical cable conversion board used as the card adapter 300 according to the present embodiment will be described with reference to FIG. The PCI Express / optical cable conversion board is an adapter provided between a communication medium and a device when performing data communication between the devices such as the server 200 and the printer 400 via the optical cable as a communication medium. As shown in the figure, the PCI Express / optical cable conversion board according to the present embodiment includes an electric card edge 50, a PCI Express switch 51, two optical cable connectors 52a and 52b, and a power supply delay circuit 53. Have. When there is no need to distinguish between the two optical cable connectors 52a and 52b, they are referred to as an optical cable connector 52. The electrical card edge 50 is a card edge connector compliant with the PCI Express communication standard. The electrical card edge 50 can be connected to a server-side or printer-side PCI Express socket 410, is connected to the motherboard of the server 200 or the motherboard of the printer 400, and transfers data communicated between the server 200 and the printer 400. It is a connection part which supplies electric power. Specifically, the electrical card edge 50 supplies power supplied from the motherboard to the PCI Express switch 51 and the optical cable connectors 52a and 52b, and sends electrical signals such as data transmitted from the motherboard to the PCI Express switch 51. Or an electrical signal such as data transmitted from the PCI Express switch 51 is transmitted to the motherboard. For example, PCI Express Gen2 × 8 is used as the electrical card edge 50 compliant with the PCI Express standard.

  A PCI Express switch 51 is wired to the electrical card edge 50. A signal line (referred to as a PCI Express signal line) connected from the electrical card edge 50 to the PCI Express switch 51 is connected to an upstream port of the PCI Express switch 51, and eight differential signals in the downstream port of the PCI Express switch 51. The wires are connected to the optical cable connectors 52a and 52b. The PCI Express switch 51 is connected to each of the optical cable connectors 52a and 52b by a serial signal, and supplies the electrical signal transmitted from the electrical card edge 50 to the optical cable connector 52 or the electrical signal transmitted from the optical cable connector 52. It is a relay unit that transmits a signal to the electrical card edge 50, and switches between connection and disconnection of the wiring lane between the electrical card edge 50 and the optical cable connectors 52a and 52b. The PCI Express switch 51 receives an interrupt signal (IntL signal) indicating that the state of the optical transceivers 600a and 600b has changed from each of the optical cable connectors 52a and 52b via the serial signal line, and the optical cable connectors 52a and 52b The communication states of the optical transceivers 600a and 600b are read as status information from the above memory, and sideband signals are generated based on the status information. The generated sideband signal is transmitted to the connected device via the electric card edge 50.

  The optical cable connector 52 is, for example, a connector to which an optical cable conforming to a communication standard of QSFP (Quad small form-factor pluggable) is connected. An optical active cable 500 is connected to the optical cable connector 52 via an optical transceiver 600. The optical cable connector 52 transmits the signal transmitted from the PCI Express switch 51 to the optical active cable 500 via the optical transceiver 600, and the data received from the optical transceiver 600 via the optical active cable 500 to the PCI Express switch 51. Or send to. The optical transceivers 600a and 600b of the optical active cable 500 are connected to the two optical cable connectors 52a and 52b, respectively, and a memory for storing its own state is provided therein. The data transmitted from the optical active cable 500 by the optical signal is converted into an electrical signal by the optical transceiver 600 and transmitted to the PCI Express switch 51 via the optical cable connector 52. The data transmitted via the PCI Express switch 51 and the optical cable connector 52 is converted into an optical signal by the optical transceiver 600 and transmitted via the optical active cable 500.

  The power supply delay circuit 53 is for controlling the start timing of the optical transceiver 600 connected to the PCI Express switch 51 and the optical active cable 500. In the present embodiment, the power supply delay circuit 53 delays the supply of power to the PCI Express switch 51 for a predetermined time with respect to the power supplied from the electrical card edge 50 from the supply of power to the optical cable connector 52. FIG. 6 is a diagram illustrating an internal configuration of the power supply delay circuit 53. The power supply delay circuit 53 includes a voltage detection circuit 60, a resistor (R) 61, a capacitor (C) 62, and a signal delay circuit including a switch (SW) 63. The terminal P1 shown in the figure is connected to the optical cable connector 52, and the terminal P2 is connected to the PCI Express switch 51. The voltage detection circuit 60 outputs a signal when the voltage value of the power supplied from the electric card edge 50 exceeds a certain value. This signal causes the switch 63 to close after a predetermined time determined by the resistor 61 and the capacitor 62. When the switch 63 is closed, power is supplied from the terminal P2 to the PCI Express switch 51. Therefore, according to the power supply delay circuit 53, power is supplied to the PCI Express switch 51 after a predetermined time from when power is supplied from the electrical card edge 50 to the optical cable connector 52.

  Here, the activation timing of the PCI Express switch 51 and the optical transceiver 600 connected to the optical cable connector 52 when the power is turned on will be described. First, the specification of the start timing at power-on based on the PCI Express CEM specification 2.0 and the QSFP + module specification (SFF-8436) will be described with reference to FIG. According to the PCI Express CEM specification, after the power supplied to the electrical card edge is stabilized, the motherboard connected to the electrical card edge outputs a reset (PERST) signal for releasing the reset state of the PCI Express switch. Is defined as 100 ms. The reset signal for releasing the reset state of the PCI Express switch is a high signal. In the PCI Express specification, the time until PCI ExpressLink becomes active after that is defined as 3.2us (16000UI). On the other hand, in the QSFP + module specification, the maximum time from turning on the power supply until the optical transceiver connected to the optical cable connector is activated and ready to operate is defined as 2000 ms. Due to this time difference, when the PCI Express switch and the optical transceiver are activated at the same time as the power to the PCI Express / optical cable conversion board is turned on, the optical transceiver can operate when the PCI ExpressLink of the PCI Express switch 51 becomes active. Since it is not in the state, the link up will fail.

  Next, in this embodiment, the start timing of the PCI Express switch 51 and the optical transceiver 600 connected to the optical cable connector 52 when the power is turned on will be described with reference to FIG. This figure shows the start timing when the rise of the power supplied to the PCI Express switch 51 by the power supply delay circuit 53 described above is delayed for a predetermined time from the rise of the power supplied from the electric card edge 50. When power is supplied to the PCI Express switch 51, a reset signal for releasing the reset state for the PCI Express switch 51 is output. Therefore, the PCI ExpressLink of the PCI Express switch 51 promptly receives the power after the start of power supply. Become active. On the other hand, the power supply to the optical transceiver 600 connected to the optical cable connector 52 is performed simultaneously with the power supply from the electric card edge 50. The predetermined time as the time difference in power supply is determined by the resistor 61 and the capacitor 62. Therefore, by appropriately setting this, the connection to the optical cable connector 52 is established when the link of the PCI Express switch 51 becomes active. It can be assured that the optical transceiver 600 being operated is operating reliably.

  As described above, in the PCI Express / optical cable conversion board equipped with the PCI Express switch 51, the power supply to the PCI Express switch 51 is delayed with respect to the optical transceiver 600 connected to the optical cable connector 52. Control start timing and start order. Thereby, it can be ensured that the optical transceiver 600 is in a communicable state when the PCI Express switch 51 is activated. As a result, the PCI Express switch 51 can reliably perform link-up.

[Second Embodiment]
Next, a second embodiment of the communication unit and the information processing apparatus will be described. In addition, about the part which is common in the above-mentioned 1st Embodiment, it demonstrates using the same code | symbol or abbreviate | omits description.

  In the present embodiment, the power supply delay circuit 53 starts the supply of power to the PCI Express switch 51 after the optical transceiver 600 connected to the optical cable connector 52 is started and starts operating. The start timing of the switch 51 and the optical transceiver 600 is controlled. FIG. 9 is a diagram illustrating the configuration of the power supply delay circuit 53 according to the present embodiment. The power supply delay circuit 53 includes a switch 63 and a signal detection circuit 64. The signal detection circuit 64 receives the interrupt signal (IntL signal) and status information transmitted after the optical transceiver 600 operates. The signal detection circuit 64 detects an interrupt signal (IntL signal) and status information, and outputs a signal according to the value set in the Data_not_Ready bit of the status information. This signal causes switch 63 to close. When the switch 63 is closed, power is supplied from the terminal P2 to the PCI Express switch 51. Therefore, according to the power supply delay circuit 53, as illustrated in FIG. 10, power is supplied to the PCI Express switch 51 after the optical transceiver 600 is activated and starts operating.

  Even with the above configuration, it is possible to ensure that the optical transceiver 600 is in a communicable state when the PCI Express switch 51 is activated. As a result, the PCI Express switch 51 can reliably perform link-up.

[Third embodiment]
Next, a third embodiment of the communication unit and the information processing apparatus will be described. In addition, about the part which is common in the above-mentioned 1st Embodiment or 2nd Embodiment, it demonstrates using the same code | symbol or abbreviate | omits description.

  In the present embodiment, the power supply delay circuit 53 outputs a reset signal for releasing the reset state for the PCI Express switch 51 after the optical transceiver 600 connected to the optical cable connector 52 is activated and starts operating. By outputting, the start timing of the PCI Express switch 51 and the optical transceiver 600 is controlled. FIG. 11 is a diagram illustrating the configuration of the power supply delay circuit 53 according to the present embodiment. The power supply delay circuit 53 includes a signal delay circuit including an AND circuit 65, a resistor 61, and a capacitor 62. A reset signal to the PCI Express switch 51 transmitted from the motherboard via the electric card edge 50 is input to the terminal P1. The terminal P3 is a terminal that outputs a reset signal to the PCI Express switch 51. An active signal is input to the terminal P2 as one piece of status information transmitted from the optical transceiver 600 connected to the optical cable connector 52. When the optical transceiver 600 is activated and starts operating, a high active signal is output from the optical transceiver 600. The AND circuit 65 outputs a high signal when the reset signal input to the terminal P1 is high and the active signal input to the terminal P2 is high. This signal is input to the terminal P3 after a predetermined time determined by the resistor 61 and the capacitor 62, and is output from the terminal P3 to the PCI Express switch 51. As a result, as illustrated in FIG. 12, a high reset signal is input to the PCI Express switch 51 with a predetermined time delay, that is, the PCI Express switch 51 is reset after the operation of the optical transceiver 600 is started. A reset signal for releasing the state is output.

  Even with the above configuration, it is possible to ensure that the optical transceiver 600 is in a communicable state when the PCI Express switch 51 is activated. As a result, the PCI Express switch 51 can reliably perform link-up.

[Modification]
Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Moreover, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined. Further, various modifications as exemplified below are possible.

  In the above-described embodiment, the PCI Express / optical cable conversion board including the PCI Express standard electrical card edge 50, the PCI Express switch 51, and the two optical cable connectors 52 has been described. The conversion board may not include the PCI Express switch 51 and the optical cable connector 52.

  In the above-described embodiment, the server 200 and the printer 400 are connected via the optical active cable 500. However, the present invention is not limited to this. For example, the server 200 and the printer 400 may be connected via a metal cable. The server 200 and the printer 400 may perform data communication wirelessly.

  In the embodiment described above, the case of performing data communication conforming to the PCI Express standard has been described, but the present invention is not limited to this.

  Further, although the optical transceiver 600 having a function of transferring data via the optical active cable 500 is handled as a device, the present invention is not limited to this as long as two devices are connected.

  In each of the above-described embodiments, the activation order of the PCI Express switch 51 and the optical transceiver 600 after power-on is controlled. However, the present invention is not limited to this. For example, when returning from hibernation or returning from hibernation. Similarly to the above-described embodiments, the activation order of the PCI Express switch 51 and the optical transceiver 600 may be controlled.

50 Electrical Card Edge 51 PCI Express Switch 52, 52a, 52b Optical Cable Connector 53 Power Delay Circuit 60 Voltage Detection Circuit 61 Resistor 62 Capacitor 63 Switch 64 Signal Detection Circuit 65 AND Circuit 600, 600a, 600b Optical Transceiver

JP 2007-121922 A

Claims (7)

A communication unit provided between the first device and the second device,
A connection unit connected to the first device and supplying power from the first device;
A device for connecting the second device and the first device;
A relay unit that relays between the second device via the device and the first device via the connection;
A communication unit comprising: an activation control unit that controls activation timing of the device and the relay unit. 2. The activation control unit controls supply of power supplied from the connection unit so that supply of power to the relay unit is delayed for a predetermined time from supply of power to the device. The communication unit described in 1. The start control unit controls the supply of power supplied from the connection unit so that power is supplied to the relay unit after the device is started and starts operating. The communication unit according to 1. The connection unit is a card edge connector to which a motherboard included in the first device is connected, and a reset signal transmitted from the motherboard to cancel the reset state for the relay unit is sent to the relay unit. Send
The activation control unit controls the activation timing of the device and the relay unit so that the reset signal is output to the relay unit after the device is activated and starts operating. The communication unit according to claim 1. The communication unit is provided between the first communication medium and the first apparatus when performing data communication between the first apparatus and the second apparatus via the first communication medium. Is,
The connection unit transfers data communicated between the first device and the second device,
2. The communication unit according to claim 1, wherein the device is a communication device to which the first communication medium is connected and performs data transfer via the first communication medium. The communication standard for the data communication is PCI Express,
The relay unit is a PCI Express switch that transmits data transferred from the connection unit to the first communication medium and transfers data transmitted from the first communication medium to the connection unit. The communication unit according to claim 5. An information processing apparatus comprising the communication unit according to claim 1.

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