CN112051496A - System for realizing SLT automatic multi-chip simultaneous measurement on wafer - Google Patents
System for realizing SLT automatic multi-chip simultaneous measurement on wafer Download PDFInfo
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- CN112051496A CN112051496A CN202010760161.6A CN202010760161A CN112051496A CN 112051496 A CN112051496 A CN 112051496A CN 202010760161 A CN202010760161 A CN 202010760161A CN 112051496 A CN112051496 A CN 112051496A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
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Abstract
The invention discloses a system for realizing SLT automatic multi-chip simultaneous testing on a wafer, belonging to the technical field of chip testing. This realize automatic multichip of SLT and survey system simultaneously on wafer, the on-line screen storage device comprises a base, the equal fixedly connected with bracing piece in four corners of base top surface, the top fixedly connected with plummer of bracing piece, the mounting groove has been seted up on the surface at plummer top. The invention can stably adsorb and position the wafer, automatically center the wafer and realize SLT automatic multi-chip simultaneous test on a plurality of wafers by arranging the vacuum pump, the connecting pipe, the bearing platform, the probe card, the automatic positioning arm, the connecting wiring board, the accommodating groove, the operating substrate, the control panel, the system mainboard and the central control center for matching use, thereby solving the problems that the SLT test system can not stably adsorb the wafer, can not automatically center the wafer and can not realize SLT automatic multi-chip simultaneous test on a plurality of wafers when in use, and greatly improving the test efficiency of the SLT test system.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a system for realizing SLT automatic multi-chip simultaneous testing on a wafer.
Background
SLT is system level test, generally install the chip on the mainboard, the memory has been configured, the peripheral hardware, start an operating system, then roast quick-witted test with the software, record result and comparison, generally adopt artifical test mode on the market, only survey a chip once, inefficiency, easy mistake, the output is low, in order to solve this difficult problem on the market, through the research of high accuracy wafer automatic positioning test technique, many sets of mainboard integration compatible technique, key technologies such as pincard wiring optimization technique, realize SLT automatic multichip simultaneous testing system on the development wafer, the efficiency and the output of SLT test have been showing and have been promoted.
Disclosure of Invention
The invention aims to solve the problems in the prior art, provides a system for realizing SLT automatic multi-chip simultaneous measurement on a wafer, has the advantages of stably adsorbing and positioning the wafer, automatically centering the wafer and realizing SLT automatic multi-chip simultaneous measurement on a plurality of wafers, and solves the problems that the SLT test system cannot stably adsorb the wafer, cannot automatically center the wafer and cannot realize SLT automatic multi-chip simultaneous measurement on the plurality of wafers when in use.
The purpose of the invention can be realized by the following technical scheme: the automatic multi-chip simultaneous measurement system for realizing SLT on a wafer comprises a base, wherein support rods are fixedly connected with four corners of the top surface of the base, a bearing table is fixedly connected with the top of each support rod, a mounting groove is formed in the surface of the top of the bearing table, a bearing screen plate is transversely and fixedly connected with the bottom of an inner cavity of the mounting groove, a storage chamber is formed in the surface of the bottom of the bearing table, a vacuum pump is fixedly connected to the left side of the surface of the top of the base and the right side of the support rod on the left side, a connecting pipe is fixedly communicated with the right side of the vacuum pump, one side, away from the vacuum pump, of the connecting pipe extends to the inner cavity of the storage chamber and is fixedly connected with an adsorption main pipe, the top of the adsorption main pipe is fixedly communicated with a sucker, adsorption holes are formed in the surface, the inner chamber fixedly connected with automatic positioning arm of holding tank, the equal fixedly connected with of both sides of operating substrate links the wiring board, one side fixedly connected with probe card that operating substrate was kept away from to the wiring board, control panel has been inlayed at the left top in operating substrate positive surface, control panel's the two-way electricity of output is connected with central control center, central control center has the system mainboard through digital test channel two-way connection, the input of system mainboard and the output signal connection of probe card, control panel's output respectively with vacuum pump and automatic positioning arm two-way electricity be connected.
Preferably, the top of the inner cavity of the storage chamber is communicated with the bottom of the inner cavity of the mounting groove, and the surface of the bottom of the bearing screen plate is in contact with the top of the inner cavity of the storage chamber.
Preferably, the outer side of the adsorption main pipe is fixedly connected with the inner wall of the storage chamber, and a gap is reserved between the surface of the top of the sucker and the surface of the bottom of the bearing screen plate.
Preferably, the center line of the control panel and the circle center of the accommodating groove are on the same straight line, the control panel is a liquid crystal touch screen, the central control center is a single chip microcomputer, and the central control center and the system main board are both installed on the back surface of the control panel.
Preferably, the four corners of the surface of the bottom of the base are fixedly connected with elastic supporting cushion blocks, and the surface of the bottom of each elastic supporting cushion block is provided with anti-skid grains.
Compared with the prior art, the invention has the following advantages:
1. the invention can stably adsorb and position the wafer and automatically center the wafer by matching the vacuum pump, the connecting pipe, the bearing table, the probe card, the automatic positioning arm, the connecting board, the accommodating groove, the operating substrate, the control panel, the adsorption hole, the sucking disc, the adsorption main pipe, the accommodating chamber, the bearing screen plate, the mounting groove, the system mainboard and the central control center, and can realize the SLT automatic multi-chip simultaneous test on a plurality of wafers, thereby solving the problems that the SLT test system can not stably adsorb the wafer, can not automatically center the wafer and can not realize the SLT automatic multi-chip simultaneous test on the wafers when in use, and greatly improving the test efficiency of the SLT test system.
2. The wafer placing platform is provided with the storage chamber, the adsorption main pipe and the sucker can be stored, the wafer is conveniently supported through the bearing screen plate, the gas flow is convenient, the base can be elastically supported through the elastic supporting cushion block, and the base is prevented from being in rigid contact with the placing platform.
Drawings
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a top view of the chuck structure of the present invention;
FIG. 3 is an enlarged view of A of FIG. 1 according to the present invention;
fig. 4 is a schematic diagram of the system of the present invention.
In the figure: the device comprises a base 1, a vacuum pump 2, a connecting pipe 3, a bearing table 4, a supporting rod 5, a probe card 6, an automatic positioning arm 7, a connecting plate 8, a containing groove 9, an operating substrate 10, a control panel 11, an adsorption hole 12, a sucker 13, an adsorption main pipe 14, a storage chamber 15, a bearing screen plate 16, a mounting groove 17, a system mainboard 18 and a central control center 19.
Detailed Description
The following are specific embodiments of the present invention and are further described with reference to the drawings, but the present invention is not limited to these embodiments.
As shown in fig. 1-4, the system for realizing SLT automatic multi-chip simultaneous measurement on a wafer includes a base 1, elastic supporting pads are fixedly connected to four corners of the bottom surface of the base 1, anti-slip patterns are formed on the surface of the bottom of the elastic supporting pads, the base 1 can be elastically supported by the elastic supporting pads to prevent the base 1 from being in rigid contact with a placement platform, supporting rods 5 are fixedly connected to four corners of the top surface of the base 1, a carrier table 4 is fixedly connected to the top of the supporting rods 5, a mounting groove 17 is formed on the surface of the top of the carrier table 4, a carrier net plate 16 is transversely and fixedly connected to the bottom of the inner cavity of the mounting groove 17, a storage chamber 15 is formed on the surface of the bottom of the carrier table 4, the top of the inner cavity of the storage chamber 15 is communicated with the bottom of the inner cavity of the mounting groove 17, the surface, can accommodate an adsorption main pipe 14 and a sucker 13, a vacuum pump 2 is fixedly connected on the left side of the top surface of a base 1 and on the right side of a left supporting rod 5, a connecting pipe 3 is fixedly communicated with the right side of the vacuum pump 2, one side of the connecting pipe 3, which is far away from the vacuum pump 2, extends to an inner cavity of a storage chamber 15 and is fixedly connected with the adsorption main pipe 14, the sucker 13 is fixedly communicated with the top of the adsorption main pipe 14, the outer side of the adsorption main pipe 14 is fixedly connected with the inner wall of the storage chamber 15, a gap is reserved between the surface of the top of the sucker 13 and the surface of the bottom of a bearing screen plate 16, a wafer is conveniently supported through the bearing screen plate 16, meanwhile, the gas flow is facilitated, an adsorption hole 12 is arranged on the surface of the top of the sucker 13, an operation substrate 10 is fixedly connected on the rear side of the top surface of the base, the both sides of operation base plate 10 all fixedly connected with even wiring board 8, one side fixedly connected with probe card 6 of operation base plate 10 is kept away from to wiring board 8, control panel 11 has been inlayed at the left top of operation base plate 10 obverse surface, control panel 11's output both-way electricity is connected with central control center 19, central control center 19 has system mainboard 18 through digital test channel both-way connection, the input of system mainboard 18 and the output signal connection of probe card 6, control panel 11's output respectively with vacuum pump 2 and automatic positioning arm 7 both-way electricity be connected.
By arranging the vacuum pump 2, the connecting pipe 3, the bearing table 4, the probe card 6, the automatic positioning arm 7, the connecting board 8, the accommodating groove 9, the operating substrate 10, the control panel 11, the adsorption hole 12, the sucker 13, the adsorption main pipe 14, the storage chamber 15, the bearing screen plate 16, the mounting groove 17, the system main board 18 and the central control center 19 for matching use, the wafer can be stably adsorbed and positioned, meanwhile, the wafer can be automatically centered, and the SLT automatic multi-chip simultaneous measurement can be realized for a plurality of wafers, so that the problems that the wafer cannot be stably adsorbed, the wafer cannot be automatically centered and the SLT automatic multi-chip simultaneous measurement cannot be realized for a plurality of wafers when the SLT testing system is used are solved, the testing efficiency of the SLT testing system is greatly improved, the central line of the control panel 11 and the center of the circle of the 9 are on the same accommodating groove straight line, the control panel 11 is a liquid crystal touch screen, the central control center 19 is a single chip microcomputer, and both the central control center 19 and the system main board 18 are installed on the back surface of the control panel 11.
When the system is used, the SLT automatic multi-chip simultaneous testing system is realized on a wafer, chips on the wafer are connected with a system mainboard 18 through a probe card 6, then a control panel 11 sends an instruction to provide a test starting signal and a receiving signal for the system mainboard 18 through a digital test channel under the action of a central control center 19, the system mainboard 18 starts a program to carry out system level test on the chips on the wafer after receiving the starting signal, a test result is fed back after the test is finished, and pass/fai judgment is carried out through a receiving channel, so that SLT test can be carried out on at least 64 chips at the same time generally due to a plurality of channels, and the efficiency is improved by 64 times compared with that of manual test.
All kinds of parts used in the application document are standard parts and can be purchased from the market, the specific connection mode of all parts adopts conventional means such as mature bolts, rivets, welding and the like in the prior art, the conventional models in the prior art are adopted for machinery, parts and electrical equipment, the conventional connection mode in the prior art is adopted for circuit connection, and detailed description is not given here.
In summary, the following steps: this realize automatic multichip of SLT and survey system simultaneously on wafer, through setting up vacuum pump 2, connecting pipe 3, plummer 4, probe card 6, automatic positioning arm 7, even wiring board 8, holding tank 9, operation base plate 10, control panel 11, adsorb hole 12, sucking disc 13, adsorb house steward 14, store up room 15, bear otter board 16, mounting groove 17, system mainboard 18 and central control center 19's cooperation is used, it is when using to have solved the SLT test system, can not adsorb the wafer stably, can not carry out automatic centering to the wafer, can not realize the automatic multichip of SLT and survey the problem simultaneously to a plurality of wafers.
The specific embodiments described herein are merely illustrative of the spirit of the invention. Various modifications or additions may be made to the described embodiments or alternatives may be employed by those skilled in the art without departing from the spirit or ambit of the invention as defined in the appended claims.
Although terms such as providing the base 1, the vacuum pump 2, the connection tube 3, the carrier 4, the support rod 5, the probe card 6, the robot arm 7, the connection board 8, the receiving groove 9, the handle substrate 10, the control panel 11, the suction hole 12, the suction cup 13, the suction manifold 14, the storage chamber 15, the carrier net plate 16, the mounting groove 17, the system main board 18, and the central control center 19 are used more frequently, the possibility of using other terms is not excluded. These terms are used merely to more conveniently describe and explain the nature of the present invention; they are to be construed as being without limitation to any additional limitations that may be imposed by the spirit of the present invention.
Claims (5)
1. Realize the automatic multichip of SLT on the wafer and survey system simultaneously, including base (1), its characterized in that: the four corners of the top surface of the base (1) are fixedly connected with supporting rods (5), the top of each supporting rod (5) is fixedly connected with a bearing table (4), the surface of the top of each bearing table (4) is provided with a mounting groove (17), the bottom of the inner cavity of each mounting groove (17) is transversely and fixedly connected with a bearing net plate (16), the surface of the bottom of each bearing table (4) is provided with a storage chamber (15), the left side of the top surface of the base (1) and the right side of the left supporting rod (5) are fixedly connected with a vacuum pump (2), the right side of each vacuum pump (2) is fixedly communicated with a connecting pipe (3), one side, away from the vacuum pump (2), of each connecting pipe (3) extends to the inner cavity of the storage chamber (15) and is fixedly connected with an adsorption main pipe (14), the top of each adsorption main pipe (14) is fixedly communicated with a sucker (13, the rear side of the top surface of the base (1) is fixedly connected with an operation substrate (10), the top of the center of the front surface of the operation substrate (10) is provided with an accommodating groove (9), the inner cavity of the accommodating groove (9) is fixedly connected with an automatic positioning arm (7), two sides of the operation substrate (10) are both fixedly connected with a connecting board (8), one side of the connecting board (8) far away from the operation substrate (10) is fixedly connected with a probe card (6), the top of the left side of the front surface of the operation substrate (10) is embedded with a control panel (11), the output end of the control panel (11) is electrically connected with a central control center (19) in a two-way manner, the central control center (19) is connected with a system mainboard (18) in a two-way manner through a digital test channel, and the input end of the system, the output end of the control panel (11) is respectively and electrically connected with the vacuum pump (2) and the automatic positioning arm (7) in a bidirectional way.
2. The system for realizing SLT automatic multi-chip simultaneous testing on wafers as claimed in claim 1, wherein the top of the inner cavity of the storage chamber (15) is communicated with the bottom of the inner cavity of the mounting groove (17), and the surface of the bottom of the bearing screen plate (16) is contacted with the top of the inner cavity of the storage chamber (15).
3. The system for realizing SLT automatic multi-chip simultaneous measurement on a wafer as claimed in claim 1, wherein the outer side of the adsorption main pipe (14) is fixedly connected with the inner wall of the storage chamber (15), and a gap is reserved between the surface of the top of the sucker (13) and the surface of the bottom of the bearing screen plate (16).
4. The system for realizing SLT automatic multi-chip simultaneous measurement on a wafer as claimed in claim 1, wherein the central line of the control panel (11) and the center of the circle of the accommodating groove (9) are on the same straight line, the control panel (11) is a liquid crystal touch screen, the central control center (19) is a single chip microcomputer, and the central control center (19) and the system main board (18) are both installed on the back surface of the control panel (11).
5. The system for realizing SLT automatic multi-chip simultaneous measurement on a wafer as claimed in claim 1, wherein four corners of the bottom surface of the base (1) are fixedly connected with elastic supporting cushion blocks, and the surface of the bottom of each elastic supporting cushion block is provided with anti-skid grains.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010760161.6A CN112051496A (en) | 2020-07-31 | 2020-07-31 | System for realizing SLT automatic multi-chip simultaneous measurement on wafer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010760161.6A CN112051496A (en) | 2020-07-31 | 2020-07-31 | System for realizing SLT automatic multi-chip simultaneous measurement on wafer |
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| CN112051496A true CN112051496A (en) | 2020-12-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202010760161.6A Pending CN112051496A (en) | 2020-07-31 | 2020-07-31 | System for realizing SLT automatic multi-chip simultaneous measurement on wafer |
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| CN202996827U (en) * | 2012-11-26 | 2013-06-12 | 上海华虹Nec电子有限公司 | Wafer capable of realizing simultaneous test for multiple chip |
| CN109814025A (en) * | 2019-03-18 | 2019-05-28 | 烟台睿创微纳技术股份有限公司 | Equipment that a kind of pair of wafer is tested, method and system |
| CN208970177U (en) * | 2018-09-30 | 2019-06-11 | 嘉兴威伏半导体有限公司 | The detection device of low capacity SPI FLASH chip |
| CN208985957U (en) * | 2018-09-30 | 2019-06-14 | 嘉兴威伏半导体有限公司 | The detection device of large capacity NAND FLASH chip |
| CN209028108U (en) * | 2018-08-28 | 2019-06-25 | 嘉兴威伏半导体有限公司 | A kind of wafer is same to survey probe card |
| CN209043569U (en) * | 2018-09-30 | 2019-06-28 | 嘉兴威伏半导体有限公司 | Installation positioning mechanism in the detection device of 8 high performance-price ratio MCU chips |
| CN209167478U (en) * | 2018-09-30 | 2019-07-26 | 嘉兴威伏半导体有限公司 | Adjusting positioning mechanism in the detection device of serial EEPROM chip |
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2020
- 2020-07-31 CN CN202010760161.6A patent/CN112051496A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202996827U (en) * | 2012-11-26 | 2013-06-12 | 上海华虹Nec电子有限公司 | Wafer capable of realizing simultaneous test for multiple chip |
| CN209028108U (en) * | 2018-08-28 | 2019-06-25 | 嘉兴威伏半导体有限公司 | A kind of wafer is same to survey probe card |
| CN208970177U (en) * | 2018-09-30 | 2019-06-11 | 嘉兴威伏半导体有限公司 | The detection device of low capacity SPI FLASH chip |
| CN208985957U (en) * | 2018-09-30 | 2019-06-14 | 嘉兴威伏半导体有限公司 | The detection device of large capacity NAND FLASH chip |
| CN209043569U (en) * | 2018-09-30 | 2019-06-28 | 嘉兴威伏半导体有限公司 | Installation positioning mechanism in the detection device of 8 high performance-price ratio MCU chips |
| CN209167478U (en) * | 2018-09-30 | 2019-07-26 | 嘉兴威伏半导体有限公司 | Adjusting positioning mechanism in the detection device of serial EEPROM chip |
| CN109814025A (en) * | 2019-03-18 | 2019-05-28 | 烟台睿创微纳技术股份有限公司 | Equipment that a kind of pair of wafer is tested, method and system |
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