CN202996827U - Wafer capable of realizing simultaneous test for multiple chip - Google Patents
Wafer capable of realizing simultaneous test for multiple chip Download PDFInfo
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- CN202996827U CN202996827U CN 201220632743 CN201220632743U CN202996827U CN 202996827 U CN202996827 U CN 202996827U CN 201220632743 CN201220632743 CN 201220632743 CN 201220632743 U CN201220632743 U CN 201220632743U CN 202996827 U CN202996827 U CN 202996827U
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Abstract
The utility model discloses a wafer capable of realizing simultaneous tests for multiple chips, comprising a wafer, wherein the wafer is provided with a plurality of bonding points for probe tests, and a metal layer is arranged above and/or surrounding each bonding point; the bonding points are connected with the metal layer; and the area of each bonding points is smaller than 50mu m * 50mu m. The wafer provided by the utility model increases the probe inserting area of the probe without increasing the chip area, and can effectively promote the design capability of the probe card for testing multiple chips simultaneously, thereby improving the testing efficiency of the wafer; in addition, the design of the multi-site probe card can be effectively conducted, the testing efficiency can be effectively improved, and the limitation that the wafer level test cannot be carried out because the bonding points of the wafer chip is too small; further, the wafer capable of realizing simultaneous tests for multiple chips successfully solves the problem of realizing the design and manufacturing of the multi-site probe card under the background of gradually reduced areas of the bonding points, so as to meet the requirements of increasing the testing efficiency and reducing the testing cost.
Description
Technical field
The utility model relates to a kind of test wafer, is specifically related to a kind of wafer that can realize the same survey of multi-chip.
Background technology
Along with the development of semiconductor technology, wafer area is from 3 inches, 4 inches to 6 inches and even 8 inches, 12 inches developments; In design process, constantly dwindle the area of modules in chip, in order to satisfy client's needs simultaneously.Pressure welding point area on chip is also along with this variation, and area constantly dwindles, from 150um * 150um to 100um * 100um, so that 70um * 70um, and even below 40um * 40um.
Wafer was to need test before encapsulation, was referred to as wafer-level test.In order to reduce testing expense, promote testing efficiency, wafer-level test company or wafer-level test relevant departments adopt the whole bag of tricks that test event is optimized, but still can not meet the demands.When carrying out wafer-level test, need to use probe, if promote the chip-count (touch down) of each test, can effectively promote the testing efficiency of wafer.
But, the design of probe, the number of plies of probe is arranged the restriction that is subjected to its intrinsic manufacturing technology,, can not satisfy the development that pressure welding point constantly dwindles and constantly realize more designs with surveying the number probe with the impact that is subjected to pressure welding point exposed metal/bare metal area that manufactures and designs of surveying probe (multi-site probe card) for multi-chip.Such as the pressure welding point area is 70um * 70um, probe can realize 128 with the design and manufacture of surveying under certain arrangement condition, but during to 40um * 40um, it is unworkable that perhaps the design and manufacture of 2 chip simultaneous test probe becomes, and let alone 128 chip simultaneous tests when the pressure welding point area reducing.
In the evolution that the pressure welding point area constantly dwindles, how to realize that the multi-chip of probe becomes very urgent with surveying.
The utility model content
Technical problem to be solved in the utility model is to provide a kind of wafer that can realize the same survey of multi-chip, and it can promote the probe multi-chip with the designed capacity of surveying.
For solving the problems of the technologies described above, the utility model can realize that multi-chip with the technical solution of the wafer of surveying is:
Comprise wafer, be provided with a plurality of pressure welding point for probe test on wafer, the top of each pressure welding point and/or periphery are provided with the layer of metal layer; Pressure welding point is connected with metal level; The area of described pressure welding point is less than 50um * 50um.
The described metal level that is positioned at the pressure welding point top, the thickness of metal level is between 5000A～12000A.Described metal level is rectangle; The area of metal level is between 60um * 60um to 150um * 150um.
The described metal level that is positioned at the pressure welding point periphery, metal level extends along the scriber direction of probe.The length of described metal level is between 60um to 150um.
Described pressure welding point comprises top layer metallic layer, the bottom connecting through hole of top layer metallic layer.The material of described top layer metallic layer is aluminium, copper.
The technique effect that the utility model can reach is:
The utility model is not increasing the acupuncture treatment area that has increased probe under the chip area prerequisite, can effectively promote the probe multi-chip with the designed capacity of surveying, thereby promotes wafer sort efficient.
The utility model can effectively carry out multi-chip with the design of surveying probe, effectively promotes testing efficiency, breaks through because the chip wafer pressure welding point is too small and possibly can't carry out the restriction of wafer-level test.
The utility model has successfully solved the same design and manufacture of surveying probe of inefficacy multi-chip under the background of the pressure welding point area that day by day reduces, to satisfy the demand that testing efficiency reduces testing cost that promotes.
Description of drawings
Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail:
Fig. 1 is that the utility model can realize that multi-chip is with the schematic diagram of the wafer of surveying; Metal level shown in figure is positioned at the top of pressure welding point;
Fig. 2 is the schematic diagram of another embodiment of the present utility model; Metal level shown in figure is positioned at the periphery of pressure welding point;
Fig. 3 is the schematic diagram that the utility model is tested; Arrow in figure is the scriber direction of probe.
Description of reference numerals in figure:
1 is pressure welding point, and 2 is metal level,
10 is wafer.
Embodiment
As shown in Figure 1, the utility model can realize that multi-chip with the wafer of surveying, comprises wafer 10, is provided with a plurality of pressure welding point 1 for probe test on wafer 10, and the top of each pressure welding point 1 or periphery are provided with layer of metal layer 2; Pressure welding point 1 is connected with metal level 2;
The area of pressure welding point 1 is less than 50um * 50um;
Be positioned at the metal level 2 of pressure welding point top, the thickness of metal level is between 5000A～12000A;
Metal level is rectangle; The areal extent of metal level is between 60um * 60um to 150um * 150um;
As shown in Figure 2 and Figure 3, be positioned at the metal level 2 of pressure welding point periphery, metal level extends along the scriber direction of probe; The length of metal level is between 60um to 150um; Can use cantilever probe to test this moment.
Be under the condition of 40um * 40um in pressure welding point, use existing probe card designs manufacturing technology can only realize the manufacturing of single-chip exploration card, test also is the single-chip test, if testing a chip required time is 20s, there are 30,000 chips to calculate on one piece of wafer, test one piece of wafer required time and be 20s * 30,000=166.7 hour, wafer-level test will become and can not realize; And after use the utility model, be that 128 same surveys are calculated by probe card designs, one piece of wafer sort required time is 20s * 30,000/128=1.3 hour, the contrast effect of its testing efficiency is significantly, and test also becomes pratical and feasible.
Claims (7)
1. can realize multi-chip with the wafer of surveying for one kind, it is characterized in that: comprise wafer, be provided with a plurality of pressure welding point for probe test on wafer, the top of each pressure welding point and/or periphery are provided with the layer of metal layer; Pressure welding point is connected with metal level; The area of described pressure welding point is less than 50um * 50um.
2. according to claim 1ly can realize that multi-chip with the wafer of surveying, is characterized in that: the described metal level that is positioned at the pressure welding point top, the thickness of metal level is between 5000A～12000A.
3. according to claim 2ly can realize multi-chip with the wafer of surveying, it is characterized in that: described metal level is rectangle; The area of metal level is between 60um * 60um to 150um * 150um.
4. according to claim 1ly can realize that multi-chip with the wafer of surveying, is characterized in that: the described metal level that is positioned at the pressure welding point periphery, metal level extends along the scriber direction of probe.
5. according to claim 4ly can realize multi-chip with the wafer of surveying, it is characterized in that: the length of described metal level is between 60um to 150um.
6. according to claim 1ly can realize multi-chip with the wafer of surveying, it is characterized in that: described pressure welding point comprises top layer metallic layer, the bottom connecting through hole of top layer metallic layer.
7. according to claim 6ly can realize multi-chip with the wafer of surveying, it is characterized in that: the material of described top layer metallic layer is aluminium, copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220632743 CN202996827U (en) | 2012-11-26 | 2012-11-26 | Wafer capable of realizing simultaneous test for multiple chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220632743 CN202996827U (en) | 2012-11-26 | 2012-11-26 | Wafer capable of realizing simultaneous test for multiple chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202996827U true CN202996827U (en) | 2013-06-12 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201220632743 Expired - Fee Related CN202996827U (en) | 2012-11-26 | 2012-11-26 | Wafer capable of realizing simultaneous test for multiple chip |
Country Status (1)
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108133921A (en) * | 2017-12-14 | 2018-06-08 | 深圳市金誉半导体有限公司 | Semiconductor chip and preparation method thereof |
| CN108133923A (en) * | 2017-12-18 | 2018-06-08 | 深圳市金誉半导体有限公司 | Semiconductor chip and preparation method thereof |
| CN108535621A (en) * | 2018-04-11 | 2018-09-14 | 上海华虹宏力半导体制造有限公司 | The crystal round test approach of discrete device chip |
| CN111106162A (en) * | 2019-12-23 | 2020-05-05 | 东莞市中晶半导体科技有限公司 | LED wafer with LED test points and transfer method |
| CN112051496A (en) * | 2020-07-31 | 2020-12-08 | 嘉兴威伏半导体有限公司 | System for realizing SLT automatic multi-chip simultaneous measurement on wafer |
| CN112582383A (en) * | 2019-09-27 | 2021-03-30 | 成都辰显光电有限公司 | Chip structure and chip detection method |
-
2012
- 2012-11-26 CN CN 201220632743 patent/CN202996827U/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108133921A (en) * | 2017-12-14 | 2018-06-08 | 深圳市金誉半导体有限公司 | Semiconductor chip and preparation method thereof |
| CN108133923A (en) * | 2017-12-18 | 2018-06-08 | 深圳市金誉半导体有限公司 | Semiconductor chip and preparation method thereof |
| CN108535621A (en) * | 2018-04-11 | 2018-09-14 | 上海华虹宏力半导体制造有限公司 | The crystal round test approach of discrete device chip |
| CN112582383A (en) * | 2019-09-27 | 2021-03-30 | 成都辰显光电有限公司 | Chip structure and chip detection method |
| CN112582383B (en) * | 2019-09-27 | 2022-12-20 | 成都辰显光电有限公司 | Chip structure and chip detection method |
| CN111106162A (en) * | 2019-12-23 | 2020-05-05 | 东莞市中晶半导体科技有限公司 | LED wafer with LED test points and transfer method |
| CN112051496A (en) * | 2020-07-31 | 2020-12-08 | 嘉兴威伏半导体有限公司 | System for realizing SLT automatic multi-chip simultaneous measurement on wafer |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131220 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20131220 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130612 Termination date: 20151126 |