CN209544341U - Semiconductor devices - Google Patents

Abstract

The utility model relates to technical field of semiconductors, the manufacturing method and test method of a kind of semiconductor devices, semiconductor devices are proposed.The semiconductor devices may include wafer, dicing lane and multiple clock multiplier circuits；Dicing lane is mutually perpendicular to distribution and wafer is separated into several chips；Multiple clock multiplier circuits are set to dicing lane, and output end is connect with chip.Can provide with the consistent high frequency clock of chip clock frequency, while not influencing the performance of chip, power consumption and area again；The wafer grade testing scheme of facilitating chip designs.

Description

Semiconductor devices

Technical field

The utility model relates to technical field of semiconductors more particularly to a kind of semiconductor devices.

Background technique

After chip production goes out, needs to test the chip operation electrical characteristic on wafer, see whether work normally And meet design requirement.

In the related art, it is surveyed usually using automatic test equipment (Automatic Test Equipment, ATE) Examination.But since the upper limit of automatic test equipment clock frequency in the related technology is many times unable to reach chip operation clock Frequency, so that automatic test equipment can not effectively test the die (single chip) on wafer.

Therefore, it is necessary to design a kind of new semiconductor devices.

Above- mentioned information disclosed in the background technology part are only used for reinforcing the understanding to the background of the utility model, therefore It may include the information not constituted to the prior art known to persons of ordinary skill in the art.

Utility model content

It is lower because providing clock frequency that the purpose of the utility model is to overcome above-mentioned automatic test equipment in the prior art The deficiency that validity test can not be carried out to the die (single chip) in wafer, provides and can produce high frequency clock signal to chip Effectively measuring semiconductor devices.

The additional aspect and advantage of the utility model will be set forth in part in the description, and partly will be from retouching It is apparent from stating, or the practice acquistion of the utility model can be passed through.

One aspect according to the present utility model, a kind of semiconductor devices, comprising:

Wafer；

Dicing lane, the dicing lane are mutually perpendicular to be distributed, and the wafer is separated into several chips；

Clock multiplier circuit is set in the dicing lane, and output end is connect with the chip.

In a kind of exemplary embodiment of the disclosure, the frequency of the clock signal of the clock multiplier circuit is greater than or waits The frequency of clock signal when the chip operation.

In a kind of exemplary embodiment of the disclosure, the clock multiplier circuit includes OR-NOT circuit or phaselocked loop Road.

In a kind of exemplary embodiment of the disclosure, the chip includes dram chip, NAND chip or NOR chip.

As shown from the above technical solution, the utility model has at least one of following advantages and good effect:

The utility model semiconductor devices, dicing lane are mutually perpendicular to distribution and wafer are separated into several chips；In dicing lane Interior to be equipped with multiple clock multiplier circuits, the output end of clock multiplier circuit is connect with chip.On the one hand, clock multiplier circuit can be with It provides and the consistent high frequency clock of chip clock frequency, while the not performance of loss chips again, power consumption and area；On the other hand, Clock multiplier circuit is arranged in dicing lane can the design of facilitating chip testing scheme.

Detailed description of the invention

Its example embodiment is described in detail by referring to accompanying drawing, above and other feature and advantage of the utility model will It becomes readily apparent from.

Fig. 1 is crystal circle structure schematic diagram；

Fig. 2 is the partial enlargement structural representation of the utility model semiconductor devices；

Fig. 3 is the flow diagram of the preparation method of the utility model semiconductor devices；

The reference numerals are as follows for main element in figure:

1, wafer；2, chip；3, integrated circuit automatic testing machine；4, clock multiplier circuit；5, dicing lane；6, scribing roadside Edge.

Specific embodiment

Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes Formula is implemented, and is not understood as limited to embodiment set forth herein；On the contrary, thesing embodiments are provided so that this is practical new Type will be full and complete, and the design of example embodiment is comprehensively communicated to those skilled in the art.It is identical in figure Appended drawing reference indicates same or similar structure, thus the detailed description that will omit them.

The utility model provides a kind of semiconductor devices first, and referring to shown in Fig. 2, which may include wafer 1, dicing lane and multiple clock multiplier circuits 4；Dicing lane 5 is mutually perpendicular to be distributed, and the wafer 1 is separated into several chips；It is more A clock multiplier circuit 4 is set in dicing lane 5, and output end is connect with chip 2.

In this example embodiment, referring to Fig.1 and shown in Fig. 2, wafer 1 may include multiple chips 2；Wafer 1 produces After out, needs to test the operating electrical characteristic of wafer 1, see whether work normally, meet design requirement.It needs after a test Wafer 1 is cut, so multiple dicing lane 5 can be arranged between multiple chips 2, any two adjacent chips 2 it Between be equipped with dicing lane 5.The frequency that clock multiplier circuit 4 changes clock signal is set in multiple dicing lane 5, when generating high frequency Clock signal, reaches test effect.

The type of chip 2 can be DRAM (Dynamic Random Access Memory, dynamic random access memory Device) chip, NAND chip or NOR chip, it is also possible to other kinds of chip, is not specifically limited in the present embodiment.

In this example embodiment, the position of clock multiplier circuit 4 be can be set apart from chip under test 2 closer In dicing lane 5 of anticipating, a clock multiplier circuit 4 can be only arranged in a dicing lane 5, and multiple clock multiplier circuits also can be set 4, it is not specifically limited in the present embodiment.

In this example embodiment, each clock multiplier circuit 4 connects a chip 2 or multiple chips 2, i.e., each A clock multiplier circuit 4 detects a chip 2 or multiple chips 2.

In this example embodiment, the partial enlargement structural representation of the utility model semiconductor devices referring to shown in Fig. 2 Figure, clock multiplier circuit 4 are arranged in dicing lane 5；Automatic test equipment (Automatic Test Equipment, ATE) is set It sets outside wafer 1, is electrically connected with clock multiplier circuit 4, clock multiplier circuit 4 is connect with chip 2.The clock of automatic test equipment Pulse signal transmission changes after the frequency of clock pulse signal to chip 2 via clock multiplier circuit 4 to clock multiplier circuit 4 It is tested.After the completion of testing wafer 1, wafer 1 cut along dicing lane edge 6,4 meeting of clock multiplier circuit It is removed together, such clock multiplier circuit 4 will not occupy 2 area of chip, and not damage chip 2, while can also reach well To test effect.

In this example embodiment, when the frequency of the clock signal of clock multiplier circuit 4 is greater than or equal to the work of chip 2 Clock signal frequency, chip could accurately be tested in chip full-speed operation in this way.

In this example embodiment, clock multiplier circuit 4 can be phase-locked loop, be also possible to OR-NOT circuit, only It wants that frequency multiplication effect can be reached, is not specifically limited in this example embodiment.

Further, the utility model also provides a kind of preparation method corresponding to above-mentioned semiconductor device；Referring to Fig. 3 institute Show, which may include:

Step S110 provides a wafer.

Multiple dicing lane are arranged in step S120 on the wafer, and the dicing lane is mutually perpendicular to be distributed, by the wafer It is separated into several chips；Form clock multiplier circuit in the dicing lane, the output end of the clock multiplier circuit with it is described Chip connection.

Each step of the preparation method of the semiconductor devices is described in detail below.

In step s 110, a wafer is provided.

In this example embodiment, a wafer is provided, multiple dicing lane are set on wafer, dicing lane is mutually perpendicular to point Wafer is separated into several chips by cloth；After wafer 1 is produced, need to test the operating electrical characteristic of wafer 1, seeing is No normal work, complies with standard, and needs to cut wafer 1 after a test, so it is arranged multiple strokes between multiple chips 2 Film channel 5 is equipped with dicing lane 5 between any two adjacent chips 2.

The type of chip can be DRAM (Dynamic Random Access Memory, dynamic random access memory) Chip, NAND chip or NOR chip, are also possible to other kinds of chip, are not specifically limited in the present embodiment.

In the step s 120, multiple dicing lane are set on the wafer, and the dicing lane is mutually perpendicular to be distributed, will be described Wafer is separated into several chips；Form clock multiplier circuit in the dicing lane, the output end of the clock multiplier circuit with The chip connection.

In this example embodiment, referring to shown in Fig. 2, clock multiplier circuit 4 is set in dicing lane 5 and changes test work Make the frequency of clock, generates high frequency clock signal, reach test effect.Clock multiplier circuit 4 is arranged in dicing lane 5；Automatically Test equipment (Automatic Test Equipment, ATE) is arranged outside wafer 1, connect with clock multiplier circuit 4, clock Frequency multiplier circuit 4 is connect with chip 2.The clock signal transmission of automatic test equipment is to clock multiplier circuit 4, via clock multiplier electricity Chip 2 is tested after changing clock signal frequency in road 4.

Shown in referring to Figures 1 and 2, after the completion of testing wafer 1, wafer 1 is cut along dicing lane edge, clock Frequency multiplier circuit 4 can be cut together, and such clock multiplier circuit 4 is not take up 2 area of chip, and does not damage chip 2；It simultaneously can also Reach test effect well.

In a kind of example embodiment, referring to shown in Fig. 2, clock multiplier circuit 4 can be phase-locked loop, phase-locked loop Input clock can be provided by automatic test equipment, the output clock of phase-locked loop can achieve chip needs work when Clock, even if the clock frequency of clock multiplier circuit 4 is adapted with the clock frequency of chip 2.In another example embodiment, when Clock frequency multiplier circuit 4 can also be OR-NOT circuit, as long as can reach frequency multiplication effect, the clock synchronization in this example embodiment The type of clock frequency multiplier circuit is not specifically limited.

In a kind of example embodiment.The formation of dicing lane 5 and the formation of clock multiplier circuit 4 can be together on wafer Shi Jinhang's, in another example embodiment, it is also possible to be initially formed dicing lane 5, then forms clock times in dicing lane 5 Frequency circuit 4.It is not specifically limited in the present embodiment.

Further, the utility model also provides a kind of semiconductor test method, described above partly leads for testing Body device, the semiconductor test method may include that test equipment is connected to the clock multiplier circuit 4 to test.

In this example embodiment, used test equipment is integrated circuit automatic testing machine 3, certainly by integrated circuit Dynamic test machine is connect with clock multiplier circuit 4 described above, and clock multiplier circuit 4 is connect with chip 2 to be tested is needed, and is integrated The clock signal of circuit automatic test machine 3 changes the frequency of its clock pulse signal by clock multiplier circuit 4, so that clock is believed Number frequency meet chip under test 2 needed for frequency.

Above-mentioned described feature, structure or characteristic can be incorporated in one or more embodiment party in any suitable manner In formula, if possible, it is characterized in discussed in each embodiment interchangeable.In the above description, it provides many specific thin Section fully understands the embodiments of the present invention to provide.It will be appreciated, however, by one skilled in the art that can be real The technical solution of the utility model is trampled without one or more in the specific detail, or others side can be used Method, component, material etc..In other cases, known features, material or operation are not shown in detail or describe to avoid fuzzy sheet The various aspects of utility model.

When certain structure is at other structures "upper", it is possible to refer to that certain structural integrity is formed in other structures, or refer to certain Structure is " direct " to be arranged in other structures, or refers to that certain structure is arranged in other structures by the way that another structure is " indirect ".

In this specification, term "one", " one ", "the", " described " and "at least one" indicating there are one or Multiple element/component parts/etc.；Term "comprising", " comprising " and " having " are to indicate the open meaning being included And refer to the element in addition to listing/component part/also may be present other than waiting other element/component part/etc.；Term " the One ", " second " and " third " etc. only use as label, are not the quantity limitations to its object.

It should be appreciated that the utility model be not limited in its application to this specification proposition component detailed construction and Arrangement.The utility model can have other embodiments, and can realize and execute in many ways.Aforementioned change Shape form and modification are fallen in the scope of the utility model.It should be appreciated that this reality of this disclosure and restriction It is mentioned or all alternative groups of two or more apparent independent features with the novel text and/or drawings that extend to It closes.All these different combinations constitute multiple alternative aspects of the utility model.Embodiment described in this specification is said The best mode for becoming known for realizing the utility model is illustrated, and those skilled in the art will be enable practical new using this Type.

Claims (2)

1. a kind of semiconductor devices characterized by comprising

Wafer；

Dicing lane, the dicing lane are mutually perpendicular to be distributed, and the wafer is separated into several chips；

Phaselocked loop is set in the dicing lane, and input terminal connects automatic test equipment, and output end is connect with the chip；

The frequency of clock signal when the frequency of the clock signal of the phaselocked loop output is more than or equal to the chip operation.

2. semiconductor devices according to claim 1, which is characterized in that the chip includes dram chip, NAND chip Or NOR chip.