CN112038336A - 氮化物器件及其esd防护结构和制作方法 - Google Patents

氮化物器件及其esd防护结构和制作方法 Download PDF

Info

Publication number
CN112038336A
CN112038336A CN202010543656.3A CN202010543656A CN112038336A CN 112038336 A CN112038336 A CN 112038336A CN 202010543656 A CN202010543656 A CN 202010543656A CN 112038336 A CN112038336 A CN 112038336A
Authority
CN
China
Prior art keywords
layer
esd protection
protection structure
type nitride
field plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202010543656.3A
Other languages
English (en)
Other versions
CN112038336B (zh
Inventor
徐宁
蔡文必
刘成
林育赐
叶念慈
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hunan Sanan Semiconductor Co Ltd
Original Assignee
Xiamen Sanan Integrated Circuit Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xiamen Sanan Integrated Circuit Co Ltd filed Critical Xiamen Sanan Integrated Circuit Co Ltd
Priority to CN202010543656.3A priority Critical patent/CN112038336B/zh
Publication of CN112038336A publication Critical patent/CN112038336A/zh
Priority to US17/344,159 priority patent/US11862680B2/en
Application granted granted Critical
Publication of CN112038336B publication Critical patent/CN112038336B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

本发明公开了一种氮化物器件的ESD防护结构，具有该ESD防护结构的氮化物器件及制作方法，氮化物器件的外延结构下至上包括衬底、缓冲层、沟道层和势垒层，并通过隔离形成有源区和设置于有源区之外的ESD防护结构区；所述有源区上设有源极、漏极、栅极以及场板；所述ESD防护结构区于势垒层上依次设有第一P型氮化物层和金属层并形成ESD防护结构；其中金属层与场板电性连接。本发明的ESD防护结构可以提高氮化物器件制备阶段的ESD防护能力，且不额外占用芯片面积。

Description

氮化物器件及其ESD防护结构和制作方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种氮化物器件的ESD防护结构、具有该防护结构的氮化物器件及其制作方法。
背景技术
静电是指物体表面的静止电荷，物体在接触、摩擦、分离、感应、电解等过程中，发生电子或离子的转移，正电荷和负电荷在局部范围内失去平衡，就形成了静电。带有静电的物体称为带电体。当带电体表面附近的静电场梯度达到一定的程度，超过周围介质的绝缘击穿场强时，介质将会发生电离，从而导致带电体的点和部分的电荷会部分或全部中和，这种现象称之为静电放电，英文Electro-Static Discharge，简称ESD。在ESD过程中，会产生上升时间极快、持续时间极短的初始大电流脉冲，并产生强烈的电磁辐射，形成ESD电磁脉冲，它的电磁能量往往会造成电子产品和设备的功能紊乱甚至部件损坏。
对于氮化物器件，一般会包含场板结构，场板的存在能有效降低电极附近的电场强度，从而提高器件的击穿电压，同时降低沟道中电子受强电场激发进入表面态的几率，从而起到抑制器件电流崩塌的作用。但是在制备氮化物器件过程中，场板会处于浮空状态(浮空电极)，同时氮化物器件在制备过程中会处于易产生静电的环境中，因此处于浮空状态的场板经常会遭受ESD伤害，甚至导致整个器件的击穿。但是传统的ESD方案如电阻分压、二极管、MOS、寄生BJT等并不能降低该制备过程中的ESD风险，同时会额外占用芯片面积。
发明内容
本发明的目的在于克服现有技术存在的不足，提供一种氮化物器件的ESD防护结构、具有该防护结构的氮化物器件及其制作方法。
为了实现以上目的，本发明的技术方案为：
一种氮化物器件的ESD防护结构，所述ESD防护结构设于所述氮化物器件的有源区之外，包括由下至上依次设置的衬底、缓冲层、沟道层、势垒层、第一P型氮化物层和金属层，所述氮化物器件设有场板，所述金属层与所述场板电性连接。
可选的，所述沟道层可以由GaN、InN或InGaN形成；所述势垒层可以由AlGaN、AlN、InAlN、AlScN或InAlGaN形成。
可选的，所述第一P型氮化物层的材料为P型GaN材料、P型AlGaN材料或P型InAlGaN材料，掺杂浓度在1017-1021cm-3之间。
可选的，所述金属层的材料为Ni、Pd、Au中的至少一种，或包含Ni、Pd、Au中的至少一种的合金或化合物；或，所述金属层的材料为Ti、Al、W中的至少一种，或包含Ti、Al、W中的至少一种的合金或化合物。
可选的，所述氮化物器件包括不相交设置的多个所述场板，其中所述ESD防护结构为面状结构，多个所述场板的末端连接至同一所述ESD防护结构；或多个所述ESD防护结构为岛状分立分布，多个所述场板的末端与多个所述ESD防护结构一一对应连接。
一种氮化物器件，所述氮化物器件的外延结构包括由下至上依次设置的衬底、缓冲层、沟道层和势垒层，并通过隔离形成有源区和设置在有源区外的ESD防护结构区；所述有源区上设有源极、漏极、栅极以及场板；所述ESD防护结构区于势垒层上依次设有第一P型氮化物层和金属层并形成权利要求1～6任一项所述的ESD防护结构；其中所述金属层与所述场板电性连接。
可选的，所述有源区还包括设于所述势垒层上的第二P型氮化物层，所述栅极设于所述第二P型氮化物层上；所述第二P型氮化物层和所述第一P型氮化物层同层设置。
可选的，所述场板和所述外延结构之间设有介质层，所述金属层与所述场板同层设置，所述介质层设有让位于所述金属层和所述场板连接的开口。
一种氮化物器件的制作方法，包括以下步骤：
1)提供一外延结构，所述外延结构包括由下至上依次设置的衬底、缓冲层、沟道层和势垒层；
2)于所述外延结构的预设ESD防护结构区上形成第一P型氮化物层；
3)于预设源极区上制备源极，于预设漏极区上制备漏极；
4)通过隔离工艺形成有源区，所述ESD防护结构区位于有源区之外；
5)沉积介质层；
6)去除ESD防护结构区内的介质层，沉积金属于有源区的介质层上制备场板，同时于ESD防护结构区形成与场板连接的金属层；
7)去除预设栅极区内的介质层，沉积金属于栅极区形成栅极。
可选的，步骤1)中，所述外延结构还包括设于所述势垒层上的P型氮化物层；步骤2)中，通过蚀刻所述P型氮化物层形成所述第一P型氮化物层以及位于预设栅极区的第二P型氮化物层；步骤7)中，沉积金属于所述第二P型氮化物层上形成所述栅极。
可选的，步骤2)中，所述第一P型氮化物层通过选区外延生长、离子注入或离子扩散形成。
本发明的有益效果为：
1)本发明的ESD防护结构通过势垒层/沟道层自发极化和压电极化形成2DEG(二维电子气)，并进一步与P型氮化物形成PN结结构，当器件制备的过程中处于浮空状态的场板上积累的电荷达到一定量，场板会形成一个相对于衬底的高电势，当该电势大于限定值时，PN结结构正向导通，从而导走场板上积累的电荷，有效提高氮化物器件制备阶段的ESD防护能力。
2)有效利用氮化物器件的外延层结构的非有源区区域，不额外占用芯片面积。
3)在氮化物器件的制备过程中同步形成，工艺简单，适于实际生产应用。
附图说明
图1为实施例1和实施例3的氮化物器件的俯视图；
图2为实施例1和实施例3的氮化物器件沿图1中a-a’方向的截面图；
图3为实施例1的氮化物器件沿图1中b-b’方向的截面图；
图4为实施例1的工艺流程图之一，其中各结构表示实施例1的方法中各步骤所形成的结构沿图1中a-a’方向的截面图；
图5为实施例1的工艺流程图之二，其中各结构表示实施例1的方法中各步骤所形成的结构沿图1中b-b’方向的截面图；
图6为实施例2的氮化物器件的俯视图；
图7为实施例3的氮化物器件沿图1中b-b’方向的截面图；
图8为实施例3的工艺流程图之一，其中各结构表示实施例3的方法中各步骤所形成的结构沿图1中a-a’方向的截面图；
图9为实施例3的工艺流程图之二，其中各结构表示实施例3的方法中各步骤所形成的结构沿图1中b-b’方向的截面图；
具体实施方式
以下结合附图和具体实施例对本发明做进一步解释。本发明的各附图仅为示意以更容易了解本发明，其具体比例可依照设计需求进行调整。文中所描述的图形中相对元件的上下关系，在本领域技术人员应能理解是指构件的相对位置而言，因此皆可以翻转而呈现相同的构件，此皆应同属本说明书所揭露的范围。
实施例1
参考图1至图3，一种具有ESD防护结构的氮化物器件，包括场板1、衬底2、缓冲层3、GaN层4、AlGaN层5、第一P型氮化物层61、第二P型氮化物层62、金属层7、介质层8、源极S、漏极D和栅极G。其中衬底2、缓冲层3、GaN层4(作为沟道层)和AlGaN层5(作为势垒层)由下至上依次设置，并通过高阻区C隔离形成有源区A和位于有源区A之外的ESD防护结构区(图中以ESD防护结构B表示)，源极S、漏极D和第二P型氮化物层62设于有源区A上，第一P型氮化物层61设于ESD防护结构区的AlGaN层5上，介质层8覆盖上述结构并对应第一P型氮化物层61和第二P型氮化物层62开口，金属层7和栅极G分别通过介质层8的开口与第一P型氮化物层61和第二P型氮化物层62连接，场板1设于介质层8之上。金属层7和场板1的末端连接。
本实施例中，在HEMT器件的有源区A外侧，利用器件的外延结构，形成了ESD防护结构B。形成的ESD防护结构B包括衬底2、缓冲层3、GaN层4、AlGaN层5、第一P型氮化物层61和金属层7。其中第一P型氮化物层61和第二P型氮化物层62同层设置(即由同一氮化物层形成)，材料为P型GaN材料、P型AlGaN材料或P型InAlGaN材料，掺杂浓度在1017-1021cm-3之间。金属层7和场板1同层设置(即由同一金属材料层形成)，材料为Ni、Pd、Au中的至少一种，或包含Ni、Pd、Au中的至少一种的合金或化合物，与第一P型氮化物层61形成欧姆接触；或者，材料为Ti、Al、W中的至少一种，或包含Ti、Al、W中的至少一种的合金或化合物，与第一P型氮化物层61形成肖特基接触。在器件制备过程中场板1处于浮空状态，会累积大量的电荷，场板1下方为介质，积累的电荷不能通过介质释放，ESD防护结构B的AlGaN/GaN因为自发极化和压电极化会形成2DEG(二维电子气)，并进一步与P型氮化物形成PN结结构，当场板1上积累的电荷达到一定量，场板1会形成一个相对于衬底2的高电势，当该电势大于3.4V，PN结结构正向导通，从而导走场板1上积累的电荷。
参考图1，图1仅以俯视角度显示各电极之间的位置关系，省略了介质层等其他结构，本领域人员应可以理解，各电极垂直方向可能位于不同层，空间上不相交。本实施例的场板1为源极场板，位于漏极D和栅极G之间，有效降低漏极附近的电场强度。本实施例的氮化物器件包括多个场板1，并设置有岛状分立分布的多个ESD防护结构B，各场板1的末端与各ESD防护结构B一一对应连接。
为便于理解，以下采用图4和图5两个方向的截面图的工艺流程图相结合说明本实施例的氮化物器件的制作方法。
步骤1：参考4a和5a，选取合适的P型氮化物HEMT外延结构，包括衬底2、缓冲层3、GaN层4、AlGaN层5和P型氮化物层6，其中AlGaN层5厚度可以在1-50nm之间，Al组分在1％-100％之间，P型氮化物层6厚度可以在50-300nm之间，掺杂浓度在1017-1021cm-3之间。
步骤2：参考4b和5b，通过光刻定义ESD防护结构区，同时定义栅极区(也可以分两步定义)，随后采用ICP、RIE等刻蚀方法去除ESD防护结构区和栅极区之外的P型氮化物层，于ESD防护结构区上形成第一P型氮化物层61，于栅极区形成第二P型氮化物层62。
步骤3：参考4c和5c，通过光刻将器件的源、漏电极图形化，随后采用蒸镀、溅射等方式制备器件的源极S和漏极D，可采用的金属体系包括：Ti、Al、Ni、Au、Ta等及其包含上述金属体系在内的合金及化合物。
步骤4：参考4d和5d，通过光刻定义器件的有源区A，随后采用离子注入或者刻蚀等方法形成有源区A外的高阻区C，高阻区C隔开有源区A和ESD防护结构区。
步骤5：参考4e和5e，整面沉积介质层8。
步骤6：参考4f和5f，通过光刻将器件的场板图形化，去除ESD防护结构区内的介质层8，随后采用蒸镀、溅射等方式同时制备相连的场板1和金属层7，金属层7通过介质层8的开口与第一P型氮化物层61接触。
步骤7：参考4g和5g，通过光刻将器件的栅极图形化，去除栅极区内的介质层8，随后采用蒸镀、溅射等方式制备栅极G，可采用的金属体系包括：Ni、Pd、Au、Ti、Al、W等及其包含上述金属体系在内的合金及化合物，栅极G通过介质层8的开口与第二P型氮化物层62接触。后续还包括常规的对源极、漏极上的介质层开口及金属互联工艺等。
需要说明的是，在本发明实施例中，所述沟道层优选为GaN层，在实际应用过程中，ESD防护结构区应用于氮化物器件，其氮化物器件的沟道层可以由GaN、InN或InGaN等形成。
需要说明的是，在本发明实施例中，所述势垒层优选为AlGaN，在实际应用过程中，ESD防护结构区应用于氮化物器件，其氮化物器件的势垒层可以由AlGaN、AlN、InAlN、AlScN或InAlGaN等形成。
实施例2
参考图6，实施例2与实施例1的差别在于，ESD防护结构B’为面状结构，即形成连续的结构且跨度范围涵盖多个平行的场板1的设置范围，平行设置的多个场板1的末端连接至同一ESD防护结构B’。其余参考实施例1。
实施例3
参考图7，本实施例的具有ESD防护结构的氮化物器件，包括场板1、衬底2、缓冲层3、GaN层4(作为沟道层)、AlGaN层5(作为势垒层)、第一P型氮化物层61、金属层7、介质层8、源极S、漏极D和栅极G。实施例3与实施例1的俯视图(图1)及a-a’方向截面图(图2)相同，由图7的b-b’方向截面图与实施例1的图3对比可见，本实施例有源区A的栅极区不设置第二P型氮化物层62，栅极G形成于AlGaN层5上，其余参考实施例1。
为便于理解，以下采用图8和图9两个方向的截面图结合说明本实施例的氮化物器件的制作方法。
步骤1：参考8a和9a，选取合适的氮化物HEMT外延结构，包括衬底2、缓冲层3、GaN层4和AlGaN层5。
步骤2：参考8b和9b，沉积氮化硅或者氧化硅等介质，通过光刻定义ESD防护结构区，通过选区二次外延在ESD防护结构区生长第一P型氮化物层63，随后采用ICP、RIE等刻蚀方法或者湿法去除氮化硅或者氧化硅等介质。第一P型氮化物层63厚度可以在50-300nm之间，掺杂浓度在1017-1021cm-3之间。
步骤3：参考8c和9c，通过光刻将器件的源、漏电极图形化，随后采用蒸镀、溅射等方式制备器件的源极S和漏极D，可采用的金属体系包括：Ti、Al、Ni、Au、Ta等及其包含上述金属体系在内的合金及化合物。
步骤4：参考8d和9d，通过光刻定义器件的有源区A，随后采用离子注入或者刻蚀等方法形成有源区A外的高阻区C，高阻区C隔开有源区A和ESD防护结构区。
步骤5：参考8e和9e，整面沉积介质层8。
步骤6：参考8f和9f，通过光刻将器件的场板图形化，去除ESD防护结构区内的介质层8，随后采用蒸镀、溅射等方式同时制备相连的场板1和金属层7，金属层7通过介质层8的开口与第一P型氮化物层63接触。
步骤7：参考8g和9g，通过光刻将器件的栅极图形化，去除栅极区内的介质层8，随后采用蒸镀、溅射等方式制备栅极G，可采用的金属体系包括：Ni、Pd、Au、Ti、Al、W等及其包含上述金属体系在内的合金及化合物，栅极G通过介质层8的开口与AlGaN层5接触。后续还包括常规金属互联工艺等。
实施例4
实施例4与实施例3均采用不包含P型氮化物的HEMT外延结构，差别为步骤2)，第一P型氮化物层是通过离子注入或扩散形成的，具体为：沉积氮化硅或者氧化硅等介质，通过光刻定义ESD防护结构区，在ESD防护结构区进行离子注入Mg或者扩散Mg，通过高温激活Mg，在ESD防护结构区形成P型氮化物；随后采用ICP、RIE等刻蚀方法或者湿法去除氮化硅或者氧化硅等介质。
本发明的ESD防护结构，可以应用于各种类型栅极的氮化物器件。
上述实施例仅用来进一步说明本发明的一种氮化物器件及其ESD防护结构和制作方法，但本发明并不局限于实施例，凡是依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均落入本发明技术方案的保护范围内。

Claims (10)

1.一种氮化物器件的ESD防护结构，其特征在于：所述ESD防护结构设于所述氮化物器件的有源区之外，包括由下至上依次设置的衬底、缓冲层、沟道层、势垒层、第一P型氮化物层和金属层，所述氮化物器件设有场板，所述金属层与所述场板电性连接。
2.根据权利要求1所述的ESD防护结构，其特征在于：所述第一P型氮化物层的材料为P型GaN材料、P型AlGaN材料或P型InAlGaN材料，掺杂浓度在1017-1021cm-3之间。
3.根据权利要求1所述的ESD防护结构，其特征在于：所述金属层的材料为Ni、Pd、Au中的至少一种，或包含Ni、Pd、Au中的至少一种的合金或化合物；或，所述金属层的材料为Ti、Al、W中的至少一种，或包含Ti、Al、W中的至少一种的合金或化合物。
4.根据权利要求1所述的ESD防护结构，其特征在于：所述氮化物器件包括不相交设置的多个所述场板，其中
所述ESD防护结构为面状结构，多个所述场板的末端连接至同一所述ESD防护结构；或
多个所述ESD防护结构为岛状分立分布，多个所述场板的末端与多个所述ESD防护结构一一对应连接。
5.一种氮化物器件，其特征在于：所述氮化物器件的外延结构包括由下至上依次设置的衬底、缓冲层、沟道层和势垒层，并通过隔离形成有源区和设置在有源区外的ESD防护结构区；所述有源区上设有源极、漏极、栅极以及场板；所述ESD防护结构区于势垒层上依次设有第一P型氮化物层和金属层并形成权利要求1～4任一项所述的ESD防护结构；其中所述金属层与所述场板电性连接。
6.根据权利要求5所述的氮化物器件，其特征在于：所述有源区还包括设于所述势垒层上的第二P型氮化物层，所述栅极设于所述第二P型氮化物层上；所述第二P型氮化物层和所述第一P型氮化物层同层设置。
7.根据权利要求5所述的氮化物器件，其特征在于：所述场板和所述外延结构之间设有介质层，所述金属层与所述场板同层设置，所述介质层设有让位于所述金属层和所述场板连接的开口。
8.一种氮化物器件的制作方法，其特征在于包括以下步骤：
1)提供一外延结构，所述外延结构包括由下至上依次设置的衬底、缓冲层、沟道层和势垒层；
2)于所述外延结构的预设ESD防护结构区上形成第一P型氮化物层；
3)于预设源极区上制备源极，于预设漏极区上制备漏极；
4)通过隔离工艺形成有源区，所述ESD防护结构区位于有源区之外；
5)沉积介质层；
6)去除ESD防护结构区内的介质层，沉积金属于有源区的介质层上制备场板，同时于ESD防护结构区形成与场板连接的金属层；
7)去除预设栅极区内的介质层，沉积金属于栅极区形成栅极。
9.根据权利要求8所述的制作方法，其特征在于：步骤1)中，所述外延结构还包括设于所述势垒层上的P型氮化物层；步骤2)中，通过蚀刻所述P型氮化物层形成所述第一P型氮化物层以及位于预设栅极区的第二P型氮化物层；步骤7)中，沉积金属于所述第二P型氮化物层上形成所述栅极。
10.根据权利要求8所述的制作方法，其特征在于：步骤2)中，所述第一P型氮化物层通过选区外延生长、离子注入或离子扩散形成。
CN202010543656.3A 2020-06-15 2020-06-15 氮化物器件及其esd防护结构和制作方法 Active CN112038336B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202010543656.3A CN112038336B (zh) 2020-06-15 2020-06-15 氮化物器件及其esd防护结构和制作方法
US17/344,159 US11862680B2 (en) 2020-06-15 2021-06-10 Electrostatic discharge protection structure, nitride-based device having the same and method for manufacturing nitride-based device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010543656.3A CN112038336B (zh) 2020-06-15 2020-06-15 氮化物器件及其esd防护结构和制作方法

Publications (2)

Publication Number Publication Date
CN112038336A true CN112038336A (zh) 2020-12-04
CN112038336B CN112038336B (zh) 2023-03-24

Family

ID=73579620

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010543656.3A Active CN112038336B (zh) 2020-06-15 2020-06-15 氮化物器件及其esd防护结构和制作方法

Country Status (2)

Country Link
US (1) US11862680B2 (zh)
CN (1) CN112038336B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112687740A (zh) * 2020-12-30 2021-04-20 江苏大学 一种AlGaN/GaN高电子迁移率晶体管及制造方法
CN114267734A (zh) * 2021-12-28 2022-04-01 东南大学 一种抗静电释放冲击的异质结半导体器件

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6583476B1 (en) * 2002-06-28 2003-06-24 Micrel, Inc. Electrostatic discharge protection for integrated semiconductor devices using channel stop field plates
CN103855152A (zh) * 2012-12-07 2014-06-11 旺宏电子股份有限公司 用于高电压静电放电防护的双向双极型结晶体管
CN107331697A (zh) * 2017-06-23 2017-11-07 深圳市晶相技术有限公司 氮化镓半导体器件及其制备方法
CN108364935A (zh) * 2018-02-13 2018-08-03 扬州江新电子有限公司 具有阵列式静电防护结构的ldmos器件
US20180323184A1 (en) * 2017-05-05 2018-11-08 Macronix International Co., Ltd. High Voltage Electrostatic Discharge (ESD) Protection
CN110444599A (zh) * 2019-08-05 2019-11-12 中国电子科技集团公司第十三研究所 GaN基异质结场效应晶体管及其制造方法
CN111211176A (zh) * 2020-01-14 2020-05-29 香港商莫斯飞特半导体有限公司 一种氮化镓基异质结集成器件结构及制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8785973B2 (en) * 2010-04-19 2014-07-22 National Semiconductor Corporation Ultra high voltage GaN ESD protection device
US8860120B2 (en) * 2010-09-22 2014-10-14 Nxp, B.V. Field modulating plate and circuit
JP5874173B2 (ja) * 2011-02-25 2016-03-02 富士通株式会社 化合物半導体装置及びその製造方法
JP5678866B2 (ja) * 2011-10-31 2015-03-04 株式会社デンソー 半導体装置およびその製造方法
US20130240894A1 (en) * 2012-03-13 2013-09-19 Hans Joachim Würfl Overvoltage Protection Device for Compound Semiconductor Field Effect Transistors
US8946779B2 (en) * 2013-02-26 2015-02-03 Freescale Semiconductor, Inc. MISHFET and Schottky device integration
JP6107435B2 (ja) * 2013-06-04 2017-04-05 三菱電機株式会社 半導体装置及びその製造方法
TWI555209B (zh) * 2013-07-29 2016-10-21 高效電源轉換公司 具有降低的輸出電容之氮化鎵裝置及其製法
DE102020111863A1 (de) * 2019-05-03 2020-11-05 Analog Devices International Unlimited Company Gegen elektrische Überlastung tolerante Mikrowellenverstärker
US20230117946A1 (en) * 2020-01-13 2023-04-20 Cambridge Gan Devices Limited Iii-v semiconductor device
US20220102344A1 (en) * 2020-09-25 2022-03-31 Intel Corporation Gallium nitride (gan) three-dimensional integrated circuit technology

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6583476B1 (en) * 2002-06-28 2003-06-24 Micrel, Inc. Electrostatic discharge protection for integrated semiconductor devices using channel stop field plates
CN103855152A (zh) * 2012-12-07 2014-06-11 旺宏电子股份有限公司 用于高电压静电放电防护的双向双极型结晶体管
US20180323184A1 (en) * 2017-05-05 2018-11-08 Macronix International Co., Ltd. High Voltage Electrostatic Discharge (ESD) Protection
CN107331697A (zh) * 2017-06-23 2017-11-07 深圳市晶相技术有限公司 氮化镓半导体器件及其制备方法
CN108364935A (zh) * 2018-02-13 2018-08-03 扬州江新电子有限公司 具有阵列式静电防护结构的ldmos器件
CN110444599A (zh) * 2019-08-05 2019-11-12 中国电子科技集团公司第十三研究所 GaN基异质结场效应晶体管及其制造方法
CN111211176A (zh) * 2020-01-14 2020-05-29 香港商莫斯飞特半导体有限公司 一种氮化镓基异质结集成器件结构及制造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112687740A (zh) * 2020-12-30 2021-04-20 江苏大学 一种AlGaN/GaN高电子迁移率晶体管及制造方法
CN114267734A (zh) * 2021-12-28 2022-04-01 东南大学 一种抗静电释放冲击的异质结半导体器件
CN114267734B (zh) * 2021-12-28 2023-03-31 东南大学 一种抗静电释放冲击的异质结半导体器件

Also Published As

Publication number Publication date
US11862680B2 (en) 2024-01-02
US20210391424A1 (en) 2021-12-16
CN112038336B (zh) 2023-03-24

Similar Documents

Publication Publication Date Title
US20200212180A1 (en) Iii-nitride devices including a graded depleting layer
US20240105829A1 (en) Group iii-nitride high-electron mobility transistors with buried p-type layers and process for making the same
US20170018617A1 (en) Field-plate structures for semiconductor devices
JP5011069B2 (ja) 小さな寄生抵抗を有する低電圧ダイオードおよび製造方法
US11195943B2 (en) Epitaxial structure of Ga-face group III nitride, active device, and gate protection device thereof
US9330918B2 (en) Edge termination by ion implantation in gallium nitride
US20210167199A1 (en) Group iii-nitride high-electron mobility transistors with gate connected buried p-type layers and process for making the same
CN112038336B (zh) 氮化物器件及其esd防护结构和制作方法
US20200395447A1 (en) Semiconductor Device and Method for Fabricating a Wafer
KR102626266B1 (ko) 매립된 p형 층을 갖는 3족 질화물 고전자 이동도 트랜지스터 및 이를 제조하기 위한 공정
CN112018176A (zh) 一种半导体器件及其制造方法
CN114270532A (zh) 半导体装置及其制造方法
US10840334B2 (en) Gallium nitride high-electron mobility transistors with deep implanted p-type layers in silicon carbide substrates for power switching and radio frequency applications and process for making the same
CN112701116B (zh) 密封环结构及其制备方法
US11929428B2 (en) Circuits and group III-nitride high-electron mobility transistors with buried p-type layers improving overload recovery and process for implementing the same
KR20240007684A (ko) 후방 장벽 구조와 매립된 p형 층을 갖는 3족 질화물 트랜지스터 및 그 방법
CN113140457A (zh) 半导体器件和用于制造半导体晶片的方法
CN115411106B (zh) 一种具有雪崩耐量的GaN器件及制作方法
CN118016665B (zh) 集成SBD的SiC衬底上增强型GaN HEMT器件
CN113921596B (zh) 氟离子注入场环氮化镓准垂直肖特基二极管及其制备方法
CN111354789B (zh) 半导体器件及制作方法
CN117121211A (zh) Iii族氮化物高电子迁移率晶体管及其制造工艺
CN114429993A (zh) 双向二极管结构及其制备方法
CN118315414A (zh) 提升纵向功率电子器件关态电学特性的结构、方法及应用
CN118738115A (zh) 一种氮化镓基高电子迁移率晶体管及其制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20230307

Address after: 410000 No. 399, Changxing Road, high tech Development Zone, Changsha, Hunan Province

Applicant after: Hunan San'an Semiconductor Co.,Ltd.

Address before: No.753-799 Min'an Avenue, Hongtang Town, Tong'an District, Xiamen City, Fujian Province, 361000

Applicant before: XIAMEN SANAN INTEGRATED CIRCUIT Co.,Ltd.

GR01 Patent grant
GR01 Patent grant