CN112020773B - 一种集成电路 - Google Patents
一种集成电路 Download PDFInfo
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- CN112020773B CN112020773B CN201880092638.9A CN201880092638A CN112020773B CN 112020773 B CN112020773 B CN 112020773B CN 201880092638 A CN201880092638 A CN 201880092638A CN 112020773 B CN112020773 B CN 112020773B
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Abstract
一种集成电路,涉及电子技术领域,用于保证集成电路具有较高的带宽,同时能够满足ESD标准。所述集成电路包括:裸片(101,201),以及与所述裸片(101,201)耦合的传输线;其中,所述传输线上周期性地设置有静电放电ESD模块(102,204)。
Description
技术领域
本申请涉及电子技术领域,尤其涉及一种集成电路。
背景技术
随着集成电路(Integrated Circuit,IC)工艺的演进,有源器件的尺寸越来越小,其寄生电容也越来越小,IC的工作频率越来越高,进而IC的高速输入输出(Input Output,IO)传输速率和高速模数转换器(Analog-to-Digital Converter,ADC)带宽也将越来越高。但是,为了保证IC的静电放电(Electro Static Discharge,ESD)性能,IC需要满足如下ESD标准:人体静电模型(Human Body Model,HBM)大于2kV、机器静电模型(Machine Model,MM)大于或等于100V/200V、器件充电静电模型(Charged Device Model,CDM)大于或等于200V/500V。因此,导致IC中用于保证ESD性能的ESD保护器件的尺寸变化不大,其寄生电容也变化不大,这样就出现了高速IO传输和高速ADC带宽与ESD标准之间的矛盾。如何解决该矛盾也就成为一个问题。
发明内容
本申请实施例提供一种集成电路,能够保证集成电路具有较高的带宽,同时能够满足ESD标准。
第一方面,提供一种集成电路,该集成电路包括:裸片,以及与所述裸片耦合的传输线;其中,所述传输线上周期性地设置有静电放电ESD模块。上述技术方案中,将用于保护所述裸片的ESD模块周期性地设置在传输线上,使得该传输线的总阻抗Z0(Z0表示传输线本身的总电感L与ESD模块对应的集总电容CESD组成的总的阻抗)对于裸片而言相当于一个特征阻抗,而不是现有带宽公式ω=1/(R0*CESD)中的CESD,且传输线的带宽理论上是没有上限的,所以使得该集成电路具有较高的带宽,同时又不影响该集成电路所需的ESD标准。
在第一方面的一种可能的实现方式中,所述传输线具有周期性结构,所述传输线的每一个周期中均设置有所述ESD模块。进一步地,所述传输线的每一个周期的特征阻抗均相等。上述可能的实现方式中,通过在所述传输线的每个周期中设置ESD模块,且每个周期的特征阻抗均相等,可以使得信号在所述传输线的每个周期内的传输特性相同。
在第一方面的一种可能的实现方式中,所述传输线的特征阻抗与所述裸片的系统阻抗相等。上述可能的实现方式中,能够最大限度地减小所述传输线对传输信号造成的衰减。
在第一方面的一种可能的实现方式中,该集成电路还包括:半导体中介层,所述裸片设置在所述半导体中介层上,所述传输线设置在所述半导体中介层中。上述可能的实现方式中,由于所述半导体中介层的制作成本通常低于所述裸片,将所述传输线设置在所述半导体中介层中能够降低该集成电路的生产成本。
在第一方面的一种可能的实现方式中,所述半导体中介层的特征尺寸大于所述裸片的特征尺寸。上述可能的实现方式中,所述半导体中介层的特征尺寸较大,通常采用较简单的半导体工艺即可实现,从而将所述传输线设置在所述半导体中介层中,也可采用较简单的半导体工艺实现,降低该集成电路的生产成本。
在第一方面的一种可能的实现方式中,所述周期性结构的传输线包括:至少两个周期性结构。
在第一方面的一种可能的实现方式中,所述ESD模块包括:上拉设置的ESD器件;和/或,下拉设置的ESD器件。上述可能的实现方式中,提供了几种所述ESD模块包括的ESD器件的设置方式,且在不同的设置方式下均能够实现ESD模块对所述裸片的保护功能,从而提高了该集成电路的设计灵活性。
在第一方面的一种可能的实现方式中,所述ESD器件为以下任一种:二极管、PNP晶体管、NPN晶体管、GGPMOS管、GGNMOS管、或者可控硅SCR。上述可能的实现方式中,提供了多种简单有效的ESD器件,从而能够提高该集成电路中所述ESD模块实现时的多样性。
第二方面,提供一种集成电路,该集成电路包括:裸片,半导体中介层和封装基板,所述裸片设置在所述半导体中介层上,所述半导体中介层设置在所述封装基板上;其中,所述半导体中介层上设置有静电放电ESD模块,所述ESD模块用于保护所述裸片。本申请的第二方面中的集成电路,由于使用了半导体中介层,所以可以将ESD模块形成于半导体中介层中。由于ESD模块的面积通常较大,将该ESD模块设置半导体中介层中,与设置在裸片中相比,可以减小裸片的面积,同时半导体中介层的生产成本低于裸片的生产成本,将该ESD模块设置半导体中介层中能够减小一定的生产成本。在半导体中介层中,所述ESD模块可以被均匀设置在传输线上形成一种周期性结构,也可以根据需要(比如空间、接口位置等)仅布置在适当的地方。
在第二方面的一种可能的实现方式中,所述裸片包括一个或者多个裸片,所述ESD模块周期性地设置在传输线上。
在第二方面的一种可能的实现方式中,所述半导体中介层的特征尺寸大于所述裸片的特征尺寸。
在第二方面的一种可能的实现方式中,所述ESD模块包括:上拉设置的ESD器件;和/或,下拉设置的ESD器件。
在第二方面的一种可能的实现方式中,所述ESD模块包括以下器件中的任一种:二极管、PNP晶体管、NPN晶体管、GGPMOS管、GGNMOS管、或者可控硅SCR。
可以理解地,上述第二方面提供的集成电路的设计思路和基本原理等与第一方面基本类似,因此,其所能达到的有益效果可参考上文所提供的第一方面中描述的有益效果,此处不再赘述。
附图说明
图1为本申请实施例提供的一种集成电路的结构示意图;
图2为本申请实施例提供的一种传输线的结构示意图;
图3为本申请实施例提供的一种设置有ESD模块的传输线的结构示意图一;
图4为本申请实施例提供的一种设置有ESD模块的传输线的结构示意图二;
图5为本申请实施例提供的一种二极管的结构示意图;
图6为本申请实施例提供的一种设置有ESD模块的传输线的结构示意图三;
图7为本申请实施例提供的一种设置有ESD模块的传输线的结构示意图四;
图8为本申请实施例提供的一种设置有ESD模块的传输线的结构示意图五;
图9为本申请实施例提供的一种设置有ESD模块的传输线的结构示意图六;
图10为本申请实施例提供的一种设置有ESD模块的传输线的结构示意图七;
图11为本申请实施例提供的另一种集成电路的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行描述。在本申请中,“至少一个”是指一个或者多个,“多个”是指两个或两个以上。“和/或”,描述关联对象的关联关系,表示可以存在三种关系,例如,A和/或B,可以表示:单独存在A,同时存在A和B,单独存在B的情况,其中A,B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达,是指的这些项中的任意组合,包括单项(个)或复数项(个)的任意组合。例如,a,b或c中的至少一项(个),可以表示:a,b,c,a-b,a-c,b-c或a-b-c,其中a、b和c可以是单个,也可以是多个。
需要说明的是,本申请中,“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言,使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
图1为本申请实施例提供的一种集成电路的结构示意图,参见图1,该集成电路包括:裸片(die)101、以及与裸片101耦合的传输线,该传输线上周期性地设置有静电放电(Electro-Static Discharge,ESD)模块102,从而使得该传输线成为周期性结构的传输线。
在本申请实施例中,周期性结构的传输线可以是指该传输线上包括多个重复性结构,每一个重复性结构即称为一个周期,这里重复性结构可以是指每个结构所包括的阻抗种类是相同的、且不同周期中多种阻抗之间的连接方式相同(比如,每个重复性结构均包括电感和电容,且电容和电感以串联的方式连接),该传输线在每个周期内对应的阻抗(即每个周期内的电感和电容组成的总阻抗)可以是相同的,所述多个可以是两个或者两个以上。图2为一种周期性结构的传输线的示意图,该传输线以两个大小不同的圆柱(这里的大小圆柱可以代表不同的特征阻抗,比如大圆柱表示传输线本身在一个周期内对应的电感,小圆柱表示ESD模块102在一个周期内对应的电容)构成一个周期为例进行说明,图2的n表示该传输线包括的周期数,n为大于或等于2的正整数,比如,n可以等于10或者20等。其中,周期性结构的传输线在技术上有个显著特征,就是电磁波在里面的传播速度比较慢,因而也可称作慢波传输线。
在可选择的实施例中,不考虑传输线上外接的其它电子器件,将传输线本身视作稳定且均匀的结构,那么按照特定长度来截取传输线并设置上ESD模块就构成了周期性结构的传输线,其中,传输线本身相当于提供电感,而ESD模块则会提供电容。因此,在本申请实施例中,所述周期性结构的传输线可以为:将传输线按照特定长度划分成多个周期,每个周期内的传输线的长度相等,每个周期内的传输线上都设置有一个ESD模块。在这里并没有强调每一个周期内使用相同的ESD模块,这是因为ESD模块的结构通常比较简单,比如一个连接电源端或者接地的二极管,其能提供的电容较为稳定,因此ESD模块的个体差异通常是可以忽略的。如果要做到精细,可以选择电容值相等或者相近的ESD模块布置在各个周期中。
当然,实际使用中传输线可以采用不同的工艺设置,或者传输线上有可能连接其它的电子器件,结果就是每个周期内即使配置了同样长度的传输线,也不会具有相同的电感或电容。对此,有两种处理方法。
第一种处理方法是:传输线工艺区别带来的差别并不大,而电子器件提供的电感或电容毕竟可控,因此,只要在可以承受的范围内,仍然以等长的传输线配置ESD模块来划定结构不同周期。也就是说,周期性结构的传输线仍然是:将传输线按照特定长度划分成多个周期,每个周期内的传输线的长度相等,每个周期内的传输线上都设置有一个相似的ESD模块。所述设置ESD模块可以为完全相同的电路结构,或者电路结构不同但具有相似的电容或者电感。
第二种解决方法则是:计算外接的电子器件能够提供的电感和电容,与传输线的长度和ESD模块合并计算,最终使得周期性结构的传输线上的每一个周期内的电感、电容近似相等。这种方法适合于传输线生成工艺差距较大,或者需要外接大电感或大电容的其它电子器件的场景下。
另外,上述ESD模块102周期性地的设置在传输线上,可以是指周期性结构传输线的每个周期上设置有具有同样阻抗的ESD模块。ESD模块102可用于表示静电放电保护的ESD器件,该集成电路可以包括多个ESD模块102。多个ESD模块102对应有一个集总电容CESD,通常CESD与裸片101的系统阻抗R0的乘积决定了集成电路输入输出(Input Output,IO)的带宽上限:ω=1/(R0*CESD),R0通常为50Ω。由于传输线的带宽理论上是没有上限的,为了减小或避免CESD对带宽的影响,可以将ESD模块102周期性地设置在传输线上,使得周期性结构传输线的总阻抗Z0(Z0表示传输线本身的总电感L与多个ESD模块102对应的集总电容CESD组成的总的阻抗)与系统阻抗R0相匹配,例如等于50Ω,这样可以最大限度地减小传输线对传输信号造成的衰减,同时对于该集成电路而言,设置有ESD模块102的传输线相当于一个特征阻抗(特征阻抗是指在整个传输线上的阻抗维持恒定不变),且上述ESD模块的CESD与上述传输线本身的总电感L组成的总阻抗Z0对裸片101而言表现出来的阻抗特性是一个电阻,而不是单独的电容,从而不再是上述现有带宽公式ω=1/(R0*CESD)中的CESD,所以使得该集成电路的带宽不再受CESD的限制,从而具有较高的带宽上限,能够满足该集成电路所需的ESD标准。比如,在图2中,多个ESD模块102周期性地设置在所述传输线上,且所述传输线的每一个周期中均设置有所述ESD模块102,图2中以ESD表示所述ESD模块102。
布置在传输线上的ESD模块102,可以防止外部能量沿着传输线攻击裸片101。同时布置在传输线上的ESD模块102与裸片101内部的电路,均具有地端或者电源端,因此,裸片101内部的电路通过接地或接电压路径与ESD模块102连接。裸片101内部产生的电荷因而能够通过传输线上的ESD模块102释放掉。
可选的,如图1所示,该集成电路还包括:半导体中介层(业界又称为interposer)103,该传输线设置在半导体中介层103中。由于周期性地设置有ESD模块102的传输线的面积很大,将该传输线设置在成本较低的半导体中介层103中,与将该传输线设置在成本较高的裸片101中相比,可以减小裸片101的面积,同时可以减小一定的成本。
其中,半导体中介层103位于裸片与衬底之间的介面,由半导体材料作为主要成份。当前常用的半导体材料有硅,锗,砷化镓等,目前在消费者领域的芯片以硅最为常见。其上通过工艺加工方法可以生成晶体管等半导体器件。相对于其上承载的裸片101,半导体中介层可以采用较为低端的半导体工艺精度。当将ESD模块制备在半导体中介层103上,相对于制备在裸片101中,具有前端工艺简单、成本低的特点。比如,半导体中介层103可以包括由硅片作为主要材料构成的本体,然后运用半导体制程工艺来形成半导体中介层中的有源区和金属层,并通过硅穿孔(TSV)技术来导通不同的层。该金属层的层数范围可以从一层到十几层,具体可以根据实际情况设置。对于多层金属层,可以将靠近集成电路的衬底的金属层可以称为低层金属层,远离衬底的金属层可以称为高层金属层,位于低层金属层与高层金属层之间的可以称为中间层金属层。比如,该多层金属层包括9层金属,9层金属从低到高可以依次为M1至M9,则上述高层金属可以是指M8和M9,中间金属层可以是指M4至M7,低层金属层可以是指M1至M3。
可选地,半导体中介层103的特征尺寸往往大于裸片101的特征尺寸以减少工艺成本,比如半导体中介层103的特征尺寸可以是90nm、65nm、45nm或者28nm等等。这里的特征尺寸也可以称为线宽,是指集成电路前道工序工艺可达到的最小导线宽度。
在本申请实施例中,ESD模块102包括:上拉设置的ESD器件;和/或,下拉设置的ESD器件。上拉设置的ESD器件是指该ESD器件与电源端连接,下拉设置的ESD器件是指该ESD器件与接地端连接。如图3所示,分别以ESD模块102包括下拉设置的ESD器件、以及上拉和下拉设置的ESD器件为例进行说明,图3中的ESD表示ESD器件,图3中的VSS表示地端,VDD表示电源端。
可选地,ESD器件可以为以下任一种:二极管、PNP晶体管、NPN晶体管、栅极接地P型金属氧化物半导体(grounded-gate P-channel Metal Oxide Semiconductor,GGPMOS)管、栅极接地N型金属氧化物半导体(grounded-gate N-channel Metal OxideSemiconductor,GGNMOS)管、或者SCR(Silicon Controlled Rectifier,可控硅)。上述任一种器件可以通过上拉的方式周期性地设置在传输线上,也可以通过下拉的方式周期性地设置在传输线上,或者同时通过上拉和下拉的方式周期性地设置在传输线上。
示例性的,如图4所示,ESD模块102包括二极管,且二极管同时通过上拉和下拉的方式周期性地设置在传输线上的结构示意图。如图4所示设置的ESD模块102进行静电放电的工作原理为:当S端出现一个正的ESD能量脉冲时,上拉设置的二极管正向导通,ESD能量会从S端-->上拉设置的二极管-->VDD端泄放ESD能量;当S端出现一个负的ESD能量脉冲时,下拉设置的二极管正向导通,ESD能量会从VSS端-->下拉设置的二极管-->S端泄放ESD能量。对应地,如图5所示,为二极管在该传输线上的结构示意图,图5中以二极管包括N区的有源区和P区的有源区、且N区的有源区和P区的有源区通过多层金属层连通为例进行说明,多层金属层可以包括顶层厚金属(ultra thick metal,UTM)、中间层金属(intermediate metals,IMs)和低层金属(lower level metals,LLMs)。在图5中,S表示信号,G1表示地端,G2表示电源端(射频下G1、G2都可以称为交流地)。
如图6所示,ESD模块102包括PNP晶体管,PNP晶体管通过下拉的方式周期性地设置在传输线上的结构示意图。如图6所示设置的ESD模块102进行静电放电的工作原理为:当S端出现一个负的ESD能量脉冲,PNP晶体管的集电极(Collector,C)到基极(Base,B)之间的二极管正向导通,ESD能量会从VSS端-->CB之间的二极管-->S端泄放ESD能量;当S端出现一个正的ESD能量脉冲,PNP的基极B与集电极C形成的反向二极管会被反向击穿,形成的反向击穿电流在基极B上的电阻会形成压降,当该压降使PNP晶体管的发射极(Emitter,E)与基极B正向PN结导通时,则PNP晶体管导通,ESD的正脉冲能量会从S端-->PNP晶体管-->VSS端泄放ESD能量。
如图7所示,ESD模块102包括NPN晶体管,NPN晶体管通过下拉的方式周期性地设置在传输线上的结构示意图。如图8所示,ESD模块102包括GGPMOS管,GGPMOS管通过下拉的方式周期性地设置在传输线上的结构示意图。如图9所示,ESD模块102包括GGNMOS管,GGNMOS管通过下拉的方式周期性地设置在传输线上周期性结构传输线上的结构示意图。如图10所示,ESD模块102包括SCR,SCR通过下拉的方式周期性地设置在传输线上的结构示意图。
需要说明的是,上述仅以图4-图10所示的ESD模块102周期性地设置在传输线上为例进行说明,并不对本申请实施例构成限定,图4-图10中的VSS表示地端,VDD表示电源端。
图11为本申请实施例提供的一种集成电路的结构示意图,参见图11,该集成电路包括:多个裸片(die)201,半导体中介层(interposer)202和封装基板203,多个裸片201被设置在所述半导体中介层202上,所述半导体中介层202则被设置在所述封装基板203上。其中,半导体中介层202上设置有静电放电ESD模块204。可选地,ESD模块204周期性地设置在传输线上,ESD模块204用于保护多个裸片201。图11中的BGA(英文:Ball Grid Array,中文:焊球阵列封装)球可以是指球栅阵列结构的焊球。
需要说明的是,图11中的半导体中介层202、ESD模块204和周期性地设置有ESD模块204的传输线分别与上述实施例中的半导体中介层103、ESD模块102和传输线类似,具体描述参见上述实施例中的相关内容,本申请实施例对此不再赘述。
在本申请实施例中,将用于保护多个裸片201的ESD模块204周期性地设置在传输线上,由于传输线的带宽理论上是没有上限的,通过将该传输线的阻抗设置为与多个裸片的系统阻抗匹配,可以保证该集成电路具有较高的带宽,同时能够满足该集成电路所需的ESD标准。此外,将该设置有ESD模块204的传输线部署在半导体中介层202中,与设置在多个裸片201中相比,可以减小多个裸片201的面积,同时可以减小一定的成本。如果以减小裸片的面积和成本的角度来考虑,将ESD模块从裸片中移入半导体中介层中,就能够实现减小裸片面积和成本的目的。因此,也可以提供一种集成电路,其包括裸片(die),半导体中介层(interposer)和封装基板。所述裸片设置在所述半导体中介层上,所述半导体中介层设置在所述封装基板上;其中,所述半导体中介层上设置有静电放电ESD模块,所述ESD模块用于保护所述裸片。
以上所述,仅为本申请的具体实施方式,但本申请的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本申请揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本申请的保护范围之内。因此,本申请的保护范围应以所述权利要求的保护范围为准。
Claims (9)
1.一种集成电路,其特征在于,包括:裸片,以及与所述裸片耦合的传输线;其中,
与所述裸片耦合的单个所述传输线上周期性地设置有静电放电ESD模块。
2.根据权利要求1所述的集成电路,其特征在于,所述传输线具有周期性结构,所述传输线的每一个周期中均设置有所述ESD模块。
3.根据权利要求2所述的集成电路,其特征在于,每一个周期内的传输线等长。
4.根据权利要求2或3所述的集成电路,其特征在于,所述传输线的每一个周期内的特征阻抗均相等。
5.根据权利要求1所述的集成电路,其特征在于,所述传输线的特征阻抗与所述裸片的系统阻抗相等。
6.根据权利要求1-5任一项所述的集成电路,其特征在于,所述集成电路还包括:半导体中介层,所述裸片设置在所述半导体中介层上,所述传输线设置在所述半导体中介层中。
7.根据权利要求6所述的集成电路,其特征在于,所述半导体中介层的特征尺寸大于所述裸片的特征尺寸。
8.根据权利要求1-7任一项所述的集成电路,其特征在于,所述ESD模块包括:上拉设置的ESD器件;和/或,下拉设置的ESD器件。
9.根据权利要求8所述的集成电路,其特征在于,所述ESD器件为以下任一种:二极管、PNP晶体管、NPN晶体管、GGPMOS管、GGNMOS管、或者可控硅SCR。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1427015A2 (en) * | 2002-12-06 | 2004-06-09 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit device and method for fabricating the same |
CN1909230A (zh) * | 2005-08-02 | 2007-02-07 | 国际商业机器公司 | 用于高速和高频器件的芯片间esd保护结构及其形成方法 |
KR20080003045A (ko) * | 2006-06-30 | 2008-01-07 | 주식회사 하이닉스반도체 | 정전기 방전 보호 회로 |
CN101926004A (zh) * | 2008-01-31 | 2010-12-22 | 飞思卡尔半导体公司 | 静电放电保护 |
WO2017091155A1 (en) * | 2015-11-26 | 2017-06-01 | Agency For Science, Technology And Research | Tsv embedded thyristor for short discharge path and reduced loading in stacked dies |
CN107924909A (zh) * | 2015-08-27 | 2018-04-17 | 高通股份有限公司 | 包括静电放电(esd)保护的集成电路(ic)封装 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8093954B1 (en) * | 2005-05-23 | 2012-01-10 | Cypress Semiconductor Corporation | High-frequency input circuit |
US9245852B2 (en) * | 2011-09-08 | 2016-01-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | ESD protection for 2.5D/3D integrated circuit systems |
US10522531B1 (en) * | 2018-10-08 | 2019-12-31 | Xilinx, Inc. | Integrated circuit device and method of transmitting data in an integrated circuit device |
US11302645B2 (en) * | 2020-06-30 | 2022-04-12 | Western Digital Technologies, Inc. | Printed circuit board compensation structure for high bandwidth and high die-count memory stacks |
-
2018
- 2018-11-15 CN CN201880092638.9A patent/CN112020773B/zh active Active
- 2018-11-15 WO PCT/CN2018/115665 patent/WO2020097859A1/zh active Application Filing
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1427015A2 (en) * | 2002-12-06 | 2004-06-09 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit device and method for fabricating the same |
CN1909230A (zh) * | 2005-08-02 | 2007-02-07 | 国际商业机器公司 | 用于高速和高频器件的芯片间esd保护结构及其形成方法 |
KR20080003045A (ko) * | 2006-06-30 | 2008-01-07 | 주식회사 하이닉스반도체 | 정전기 방전 보호 회로 |
CN101926004A (zh) * | 2008-01-31 | 2010-12-22 | 飞思卡尔半导体公司 | 静电放电保护 |
CN107924909A (zh) * | 2015-08-27 | 2018-04-17 | 高通股份有限公司 | 包括静电放电(esd)保护的集成电路(ic)封装 |
WO2017091155A1 (en) * | 2015-11-26 | 2017-06-01 | Agency For Science, Technology And Research | Tsv embedded thyristor for short discharge path and reduced loading in stacked dies |
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US20210272948A1 (en) | 2021-09-02 |
CN112020773A (zh) | 2020-12-01 |
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