CN112018118B - 3D memory device, memory structure thereof and control method of memory structure - Google Patents

3D memory device, memory structure thereof and control method of memory structure Download PDF

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Publication number
CN112018118B
CN112018118B CN202010705237.5A CN202010705237A CN112018118B CN 112018118 B CN112018118 B CN 112018118B CN 202010705237 A CN202010705237 A CN 202010705237A CN 112018118 B CN112018118 B CN 112018118B
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memory
transistors
transistor
bit line
gate
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CN112018118A (en
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刘磊
周文犀
夏志良
王启光
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

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Abstract

The application discloses a 3D memory device, a memory structure and a memory structure control method thereof, wherein the memory structure comprises a plurality of transistors connected in series between a first end and a second end, and the plurality of transistors comprise: the grid electrode of the first selection transistor is connected with the top selection grid line; the grid electrode of the second selection transistor is connected with the bottom selection grid line; and at least one memory transistor connected in series between the first and second select transistors, the gate of each memory transistor being connected to a corresponding word line, wherein the first end of the memory structure is for connection to a first bit line and the second end is for connection to a second bit line, the first and second bit lines being for providing carriers of the same electrical properties to the channels of the respective transistors during programming and/or erasing operations, thereby greatly improving the programming and erasing speeds.

Description

3D memory device, memory structure thereof and control method of memory structure
Technical Field
The present invention relates to a memory technology, and more particularly, to a 3D memory device and a memory structure thereof and a control method of the memory structure.
Background
The development of semiconductor technology is directed to the reduction of feature size and the improvement of integration level. For memory devices, the increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As feature sizes of semiconductor fabrication processes become smaller, memory density of memory devices becomes higher.
In order to further increase the storage density, three-dimensional structured memory devices (i.e., 3D memory devices) have been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can improve integration in multiple per unit area of a wafer, and can reduce cost.
In 3D memory devices, a gate stack structure is generally used, and channel pillars provide select transistors and memory transistors, and an array common source structure (ACS) is used to provide a common source signal to all channel pillars. As the number of layers of the gate stack structure of the 3D memory device increases, the ACS provides a common source signal to all channel columns, which causes a large noise, and as the memory block capacity increases, there are many redundancy operations in programming and/or erasing the memory block, and in addition, the programming and/or erasing speed is affected.
Disclosure of Invention
The invention aims to provide an improved 3D memory device, a memory structure thereof and a control method of the memory structure, which not only improve noise problems, but also accelerate the programming and/or erasing speed of the device by eliminating an array common source structure and adopting double-bit lines to respectively provide carriers with the same electrical property for channels of each transistor under programming and/or erasing operation.
According to a first aspect of an embodiment of the present invention, there is provided a memory structure of a 3D memory device, including a plurality of transistors connected in series between a first terminal and a second terminal, the plurality of transistors including: the grid electrode of the first selection transistor is connected with the top selection grid line; the grid electrode of the second selection transistor is connected with the bottom selection grid line; and at least one memory transistor connected in series between the first and second select transistors, a gate of each memory transistor being connected to a corresponding word line, wherein the first end of the memory structure is for connection to a first bit line and the second end is for connection to a second bit line, the first and second bit lines being for providing carriers of the same electrical properties to a channel of each transistor under program and/or erase operations.
Preferably, the plurality of transistors further includes a plurality of dummy transistors between the first selection transistor and the memory transistor, and between the second selection transistor and the memory transistor.
Preferably, the number of the storage transistors is plural, and the dummy transistors are further located between the adjacent storage transistors.
Preferably, the gates of the transistors and the respective top gate select line, bottom gate select line and word line are formed based on respective gate conductor layers in a gate stack structure, and the channel of each transistor is formed based on a channel pillar extending through the gate stack structure.
Preferably, the channel column comprises a gate dielectric layer, a charge storage layer, a tunneling dielectric layer and the channel layer which are sequentially arranged along the radial inward direction of the channel column.
According to a second aspect of embodiments of the present invention, there is provided a control method for controlling a memory structure as described above, comprising simultaneously providing the same signal to the first bit line and the second bit line.
According to a third aspect of embodiments of the present invention, there is provided a 3D memory device comprising at least one memory block, each of the memory blocks having a plurality of memory structures as described above arranged in an array.
Preferably, the first ends of each column of memory structures in each of the memory blocks are connected to the same first bit line, and the second ends of each row of memory structures in each of the memory blocks are connected to the same second bit line.
Preferably, the first ends of each column of memory structures in each of the memory blocks are connected to the same first bit line, and the second ends are connected to the same second bit line.
Preferably, in each of the memory blocks, gates of the transistors located at the same layer are connected by the same gate conductor layer.
According to the 3D memory device, the memory structure and the control method of the memory structure, the first end and the second end of the channel pillar are respectively connected to the first bit line and the second bit line, so that the first bit line and the second bit line provide carriers with the same electrical property for the channel of each transistor under programming and/or erasing operation.
Further, since the second terminal of the memory structure is already connected to the second bit line, the prior art array common source structure is replaced, thereby improving the noise problem of the device.
Further, since each memory block of the 3D memory device is divided into a plurality of sub memory blocks, each sub memory block is composed of a column or a memory structure, data in each sub memory block can be individually controlled under a program or erase operation, i.e., the program or erase operation between each sub memory block is not affected each other, thereby improving the problem of redundant operation of the device.
Therefore, the 3D memory device and the memory structure thereof according to the embodiments of the present invention improve the performance of the product.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings.
Fig. 1a and 1b show a circuit diagram and a schematic diagram of a memory structure of a 3D memory device according to an embodiment of the present invention, respectively.
Fig. 1c and fig. 1d are schematic diagrams illustrating a memory structure according to an embodiment of the present invention.
Fig. 2 shows a schematic structure of a plurality of memory blocks of a 3D memory device.
Fig. 3 shows a circuit schematic of each memory block according to the first embodiment of the present invention.
Fig. 4 shows a circuit schematic of each memory block according to the second embodiment of the present invention.
Fig. 5 is a schematic diagram illustrating an effect analysis according to an embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The semiconductor structure obtained after several steps may be depicted in one figure for simplicity.
It will be understood that when a layer, an area, or a structure of a device is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or further layers or areas can be included between the other layer, another area, etc. And if the device is flipped, the one layer, one region, will be "under" or "beneath" the other layer, another region.
If, for the purposes of describing a situation directly overlying another layer, another region, the expression "directly overlying … …" or "overlying and adjoining … …" will be used herein.
In the present application, the term "semiconductor structure" refers to a generic term for the entire semiconductor structure formed in the various steps of fabricating a memory device, including all layers or regions that have been formed. Numerous specific details of the application, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a thorough understanding of the application. However, as will be understood by those skilled in the art, the present application may be practiced without these specific details.
The invention may be embodied in various forms, some examples of which are described below.
Fig. 1a and 1b show a circuit diagram and a schematic diagram of a memory structure (also called a memory cell string) of a 3D memory device, respectively. The memory structure shown in this embodiment includes a case of 4 memory cells. It is to be understood that the present invention is not limited thereto, and the number of memory cells in the memory structure may be any number, for example, 1 or 2 or 32 or 64, or the like.
As shown in fig. 1a, the memory structure 100 has a first terminal for connecting to a first Bit Line (Bit-line_a, bl_a) and a second terminal for connecting to a second Bit Line (Bit-line_b, bl_b). The memory structure 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first selection transistor Q1, memory transistors M1 to M4, and a second selection transistor Q2. The gate of the first selection transistor Q1 is connected to the top selection gate line TSG. The gate of the second selection transistor Q2 is connected to the bottom selection gate line BSG. The gates of the memory transistors M1 to M4 are connected to corresponding Word lines (Word-Line) WL1 to WL4, respectively.
As shown in fig. 1b, the select transistors Q1 and Q2 of the memory structure 100 include a top gate conductor layer 122 and a bottom gate-to-body layer 123, respectively, and the memory transistors M1-M4 include a gate conductor layer 121, respectively. The gate conductor layers 121, 122, and 123 are aligned with the stacking order of transistors in the memory structure 100, and adjacent gate conductor layers are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory structure 100 includes a channel pillar 110. The channel pillar 110 is adjacent to or extends through the gate stack. In the middle portion of the channel pillar 110, a tunneling dielectric layer 112, a charge storage layer 113, and a gate dielectric layer 114 are sandwiched between a gate conductor layer 121 and a channel layer 111, thereby forming memory transistors M1 to M4. Gate dielectric layer 114 is sandwiched between gate conductor layers 122 and 123 and channel layer 111 at both ends of channel pillar 110, thereby forming select transistors Q1 and Q2.
In this embodiment, the channel layer 111 is composed of, for example, polysilicon, the tunneling dielectric layer 112 and the gate dielectric layer 114 are each composed of an oxide, for example, silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals, for example, silicon nitride containing fine particles of a metal or semiconductor, and the gate conductor layers 121, 122, and 123 are composed of a metal, for example, tungsten. The channel layer 111 is used to provide channel regions for the control select and control transistors, and the doping type of the channel layer 111 is the same as the types of the select and control transistors. For example, for an N-type select transistor and a control transistor, the channel layer 111 may be N-type doped polysilicon.
In this embodiment, the core of the channel pillar 110 is the channel layer 111, and the tunneling dielectric layer 112, the charge storage layer 113, and the gate dielectric layer 114 form a stacked structure around the core sidewall. In an alternative embodiment, the core of the channel pillar 110 is an additional insulating layer, and the channel layer 111, the tunneling dielectric layer 112, the charge storage layer 113, and the gate dielectric layer 114 form a stacked structure around the semiconductor layer.
In this embodiment, the selection transistors Q1 and Q2, the memory transistors M1 to M4 use a common channel layer 111 and gate dielectric layer 114. In the channel pillar 110, a channel layer 111 provides source and drain regions and channel layers of a plurality of transistors. In alternative embodiments, the semiconductor layers and gate dielectric layers of the select transistors Q1 and Q2 and the semiconductor layers and gate dielectric layers of the memory transistors M1 to M4 may be formed separately from each other. In the channel pillar 110, the semiconductor layers of the selection transistors Q1 and Q2 and the semiconductor layers of the memory transistors M1 to M4 are electrically connected to each other.
In some other embodiments, the selection transistor Q1 may also be fabricated as a structure like the memory transistors M1 to M4, specifically, the tunnel dielectric layer 112, the charge storage layer 113 and the gate dielectric layer 114 are sandwiched between the gate conductor layer 121 and the channel layer 111 at the upper portion of the channel pillar 110, so as to form the selection transistor Q1. Since the selection transistor Q1 has the same structure as the memory transistors M1 to M4, the formation process of the channel pillar can be simplified.
Fig. 1c and fig. 1d are schematic diagrams illustrating a memory structure according to an embodiment of the present invention.
As shown in connection with fig. 1 a-1 d, in a programming operation, the memory structure 100 utilizes FN tunneling to write data to selected ones of the memory transistors M1-M4. Taking the memory transistor M2 as an example, the first bit line bl_a and the second bit line bl_b are grounded, and the top gate select line TSG and the bottom gate select line BSG are biased to the high voltage VDD, so that the select transistors Q1 and Q2 corresponding to the top gate select line TSG and the bottom gate select line BSG are turned on. Word line WL2 is biased at a programming voltage VPG, e.g., around 20V, with the remaining word lines biased at a low voltage VPS1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons 10 move from the first and second ends of the channel pillar 110 toward the channel region of the memory transistor M2 (arrow direction), and then reach the charge storage layer 113 via the tunneling dielectric layer 112, thereby converting data into charges to be stored in the charge storage layer 113 of the memory transistor M2.
In the erase operation, taking the memory transistor M2 as an example, the top gate selection line TSG and the bottom gate selection line BSG are biased to the high voltage VDD, so that the selection transistors Q1, Q2 corresponding to the top gate selection line TSG and the bottom gate selection line BSG are turned on. The first bit line BL_a and the second bit line BL_b are both biased to a high voltage VDD, the word line WL2 is biased to an erase voltage VES, and holes move from the first and second ends of the channel pillar 110 to the channel region of the memory transistor M2 before reaching the charge storage layer 113 via the tunneling dielectric layer 112, while or accompanied by the channel region reached by electrons 10 in the charge storage layer 113 of the memory transistor M2 through the tunneling dielectric layer 112. In another case, there is only one mechanism for electrons 10 in the charge storage layer 113 of the memory transistor M2 to reach through the tunnel dielectric layer 112.
In a read operation, the memory structure 100 determines the amount of charge in the charge storage layer according to the on state of a selected one of the memory transistors M1 to M4, thereby obtaining data indicative of the amount of charge. Taking memory transistor M2 as an example, word line WL2 is biased at read voltage VRD and the remaining word lines are biased at high voltage VPS2. The on state of the memory transistor M2 is related to its threshold voltage, i.e. to the amount of charge in the charge storage layer, so that the data value can be determined from the on state of the memory transistor M2. The memory transistors M1, M3 and M4 are always in an on state, and thus the on state of the memory structure 100 depends on the on state of the memory transistor M2. The control circuit judges the on state of the memory transistor M2 from the electric signals detected on the first bit line bl_a and the second bit line bl_b, thereby obtaining the data stored in the memory transistor M2.
As shown in fig. 1d, the gate stack structure may further include a plurality of gate conductor layers 124 (DMY) disposed between the gate conductor layers 122 and 121 and between the gate conductor layers 123 and 121, and if the number of the gate conductor layers 121 is plural, the gate conductor layers 124 are also disposed between the adjacent gate conductor layers 121. Correspondingly, the plurality of transistors further includes a plurality of dummy transistors disposed between the first selection transistor Q1 and the memory transistor M1, between the second selection transistor Q2 and the memory transistor M4, and between the adjacent memory transistors M1, M2, M3, and M4. The gate conductor layer 124 (DMY) is used for process and electrical buffering.
Fig. 2 shows a schematic structure of a plurality of memory blocks of a 3D memory device.
As shown in fig. 2, the 3D memory device includes a plurality of memory blocks 1000, and each memory block 1000 may include therein a structure extending along a first direction X, a second direction Y, and a third direction Z crossing each other, for example, each memory block 1000 has therein a memory structure 100 extending along the Z direction.
Fig. 3 shows a circuit schematic of each memory block according to the first embodiment of the present invention.
As shown in fig. 3, the memory structures are arranged in an array, and in each memory block, the gates of the transistors located in the same layer are connected through the same gate conductor layer. The gates of the first select transistors of each memory structure are connected to a uniform top select gate line TSG, the gates of the second select transistors are connected to a uniform bottom select gate line BSG, and the gates of the memory transistors are connected to respective word lines W1 to W4. The first end of each column of memory structures is connected to a respective first bit line BL_a1 to BL_a3, and the second end of each column of memory structures is connected to a respective second bit line BL_b1 to BL_b3. By the above circuit connection, each memory block 1000 is divided into a plurality of sub memory blocks 1001, and each sub memory block 1001 is constituted by a column of memory structures.
Fig. 4 shows a circuit schematic of each memory block according to the second embodiment of the present invention.
As shown in fig. 4, the memory structures are arranged in an array, and in each memory block, the gates of the transistors located in the same layer are connected through the same gate conductor layer. The gates of the first select transistors of each memory structure are connected to a uniform top select gate line TSG, the gates of the second select transistors are connected to a uniform bottom select gate line BSG, and the gates of the memory transistors are connected to respective word lines W1 to W4. The first end of each column of memory structures is connected to a respective first bit line BL_a1 to BL_a3, and the second end of each row of memory structures is connected to a respective second bit line BL_b1 to BL_b3. By the above circuit connection, each memory block 1000 is divided into a plurality of sub memory blocks 1001, and each sub memory block 1001 is constituted by one memory structure.
Fig. 5 is a schematic diagram illustrating an effect analysis according to an embodiment of the present invention.
As shown in fig. 5, in some conventional 3D memory devices, a gate stack structure 210 located on a substrate 201 is penetrated by an array common source structure (ACS) 230, the array common source structure 230 forming an electrical connection with each channel pillar 110 through a source region 230 located in the substrate 201.
Since the common source signal is provided to all the channel pillars 210 in each memory block by the array common source structure, as the number of layers of the gate stack structure of the 3D memory device increases, the common source signal is provided to all the channel pillars 210 by the array common source structure 230, which causes a large noise, and as the memory block capacity increases, there are many redundancy operations in performing the program and/or erase operations of the memory block. For example, to erase or program a portion of data in a memory block, all data in the entire memory block needs to be backed up first, and when the memory capacity of a memory block increases, the data that needs to be backed up increases, thereby causing many redundant operations. In addition, program and/or erase speed can be affected.
According to the 3D memory device, the memory structure and the control method of the memory structure, the first end and the second end of the channel pillar are respectively connected to the first bit line and the second bit line, so that the first bit line and the second bit line provide carriers with the same electrical property for the channel of each transistor under programming and/or erasing operation.
Further, since the second terminal of the memory structure is already connected to the second bit line, the prior art array common source structure is replaced, thereby improving the noise problem of the device.
Further, since each memory block of the 3D memory device is divided into a plurality of sub memory blocks, each sub memory block is composed of a column or a memory structure, data in each sub memory block can be individually controlled under a program or erase operation, i.e., the program or erase operation between each sub memory block is not affected each other, thereby improving the problem of redundant operation of the device.
Therefore, the 3D memory device and the memory structure thereof according to the embodiments of the present invention improve the performance of the product.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present invention are described above. These examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the invention, and such alternatives and modifications are intended to fall within the scope of the invention.

Claims (7)

1. A 3D memory device comprising at least one memory block, each of the memory blocks having a plurality of memory structures arranged in an array, the memory structures comprising a plurality of transistors connected in series between a first terminal and a second terminal, the plurality of transistors comprising:
the grid electrode of the first selection transistor is connected with the top selection grid line;
the grid electrode of the second selection transistor is connected with the bottom selection grid line; and
At least one memory transistor connected in series between the first select transistor and the second select transistor, a gate of each memory transistor being connected to a corresponding word line,
Wherein the first end of each column of the memory structures is for connection to a respective first bit line, the second end of each row of the memory structures is for connection to a respective second bit line, the first bit line and the second bit line are for providing carriers of the same electrical properties to the channel of the respective transistor during programming and/or erasing operations,
Wherein the second bit of a memory structure located in the same row or column in the plurality of memory structures
The lines are connected to each other to form sub memory blocks.
2. The 3D memory device of claim 1, wherein the plurality of transistors further comprises a plurality of dummy transistors between the first select transistor and the memory transistor, between the second select transistor and the memory transistor.
3. The 3D memory device of claim 2, wherein the number of memory transistors is a plurality, the dummy transistors being further located between adjacent ones of the memory transistors.
4. A 3D memory device according to any one of claims 1 to 3, wherein the gates of the transistors and the respective top, bottom and word lines are formed based on respective gate conductor layers in a gate stack structure, the channel of each transistor being formed based on a channel pillar extending through the gate stack structure.
5. The 3D memory device of claim 4, wherein the channel pillar comprises a gate dielectric layer, a charge storage layer, a tunneling dielectric layer, and a channel layer arranged in sequence along a radially inward direction of the channel pillar.
6. The 3D memory device of claim 5, wherein in each of the memory blocks, gates of the transistors located at the same layer are connected by the same gate conductor layer.
7. A control method for controlling a 3D memory device according to any one of claims 1 to 6, comprising supplying the same signal to the first bit line and the second bit line simultaneously.
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