CN112018118A - 3D memory device, memory structure thereof and control method of memory structure - Google Patents

3D memory device, memory structure thereof and control method of memory structure Download PDF

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Publication number
CN112018118A
CN112018118A CN202010705237.5A CN202010705237A CN112018118A CN 112018118 A CN112018118 A CN 112018118A CN 202010705237 A CN202010705237 A CN 202010705237A CN 112018118 A CN112018118 A CN 112018118A
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memory
transistor
gate
transistors
bit line
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CN202010705237.5A
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刘磊
周文犀
夏志良
王启光
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Abstract

The application discloses a 3D memory device, a memory structure thereof and a memory structure control method, wherein the memory structure comprises a plurality of transistors connected in series between a first terminal and a second terminal, the plurality of transistors comprise: a first selection transistor having a gate connected to the top selection gate line; a second selection transistor having a gate connected to the bottom selection gate line; and at least one memory transistor connected in series between the first selection transistor and the second selection transistor, wherein the gate of each memory transistor is connected with a corresponding word line, the first end of the memory structure is used for being connected to a first bit line, the second end of the memory structure is used for being connected to a second bit line, and the first bit line and the second bit line are used for providing carriers of the same electrical property for channels of the transistors under the programming and/or erasing operation, so that the programming and erasing speed is greatly improved.

Description

3D memory device, memory structure thereof and control method of memory structure
Technical Field
The present invention relates to a memory technology, and more particularly, to a 3D memory device, a memory structure thereof, and a control method of the memory structure.
Background
The direction of development in semiconductor technology is the reduction of feature size and the increase of integration. For the memory device, the increase in the memory density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature size of semiconductor manufacturing processes becomes smaller, the storage density of memory devices becomes higher.
In order to further increase the memory density, a memory device of a three-dimensional structure (i.e., a 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can increase integration density by a multiple on a unit area of a wafer, and can reduce cost.
In 3D memory devices, the select transistor and the memory transistor are typically provided in a gate stack structure and channel pillars, and a common source signal is provided to all channel pillars in an array common source structure (ACS). As the number of layers of the gate stack structure of the 3D memory device increases, the use of ACS to supply a common source signal to all channel pillars causes a large noise, and as the capacity of the memory block increases, there are many problems of redundant operations in programming and/or erasing the memory block, and in addition, programming and/or erasing speeds are affected.
Disclosure of Invention
The invention aims to provide an improved 3D memory device, a memory structure thereof and a control method of the memory structure, wherein the noise problem is improved, and the programming and/or erasing speed of the device is increased by eliminating an array common source structure and adopting double bit lines to respectively provide carriers with the same electrical property to channels of various transistors under the programming and/or erasing operation.
According to a first aspect of embodiments of the present invention, there is provided a memory structure of a 3D memory device, including a plurality of transistors connected in series between a first terminal and a second terminal, the plurality of transistors including: a first selection transistor having a gate connected to the top selection gate line; a second selection transistor having a gate connected to the bottom selection gate line; and at least one memory transistor connected in series between the first selection transistor and the second selection transistor, the gate of each memory transistor being connected to a corresponding word line, wherein the first end of the memory structure is for connection to a first bit line, the second end is for connection to a second bit line, and the first bit line and the second bit line are for providing carriers of the same electrical property to the channel of each of the transistors under program and/or erase operations.
Preferably, the plurality of transistors further includes a plurality of dummy transistors between the first selection transistor and the storage transistor and between the second selection transistor and the storage transistor.
Preferably, the number of the memory transistors is plural, and the dummy transistor is also located between the adjacent memory transistors.
Preferably, the gates of the transistors and the respective top gate select line, bottom gate select line and word line are formed on the basis of respective gate conductor layers in a gate stack, the channel of each transistor being formed on the basis of a channel pillar extending through the gate stack.
Preferably, the channel pillar includes a gate dielectric layer, a charge storage layer, a tunneling dielectric layer, and the channel layer, which are sequentially arranged along a radial inward direction of the channel pillar.
According to a second aspect of embodiments of the present invention, there is provided a control method for controlling a memory structure as described above, comprising simultaneously providing the same signal to the first bit line and the second bit line.
According to a third aspect of embodiments of the present invention, there is provided a 3D memory device including at least one memory block, each of the memory blocks having a plurality of memory structures as described above arranged in an array.
Preferably, the first end of each column of memory structures in each memory block is connected to the same first bit line, and the second end of each row of memory structures in each memory block is connected to the same second bit line.
Preferably, the first end of each column of memory structures in each memory block is connected to the same first bit line, and the second end is connected to the same second bit line.
Preferably, in each of the memory blocks, gates of the transistors located in the same layer are connected through the same gate conductor layer.
According to the 3D memory device, the memory structure and the control method of the memory structure of the 3D memory device, the first end and the second end of the channel column are respectively connected to the first bit line and the second bit line, so that the first bit line and the second bit line provide carriers with the same electrical property to the channel of each transistor under the programming and/or erasing operation, and since the carriers are provided into the channel of the transistor from two directions, compared with the scheme of providing the carriers in a single direction in the prior art, the bidirectional carrier supply can improve the programming/erasing speed of the device.
Further, since the second terminal of the memory structure is already connected to the second bit line, the array common source structure in the prior art is replaced, thereby improving the noise problem of the device.
Furthermore, since each memory block of the 3D memory device is divided into a plurality of sub memory blocks, each sub memory block is composed of a column or a memory structure, data in each sub memory block can be individually controlled under a program or erase operation, i.e., the program or erase operations between each sub memory block are not affected by each other, thereby improving the problem of redundant operation of the device.
Therefore, the 3D memory device and the memory structure thereof according to the embodiments of the present invention improve the performance of a product.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1a and 1b show a circuit diagram and a structural schematic diagram, respectively, of a memory structure of a 3D memory device according to an embodiment of the present invention.
Fig. 1c and 1d are schematic diagrams illustrating a memory structure according to an embodiment of the present invention.
Fig. 2 illustrates a structural diagram of a plurality of memory blocks of a 3D memory device.
Fig. 3 shows a circuit schematic of each memory block of the first embodiment of the present invention.
Fig. 4 shows a circuit schematic of each memory block of the second embodiment of the present invention.
Fig. 5 is a schematic diagram of effect analysis according to an embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly on another layer, another area, the expression "directly on … …" or "on … … and adjacent thereto" will be used herein.
In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The present invention may be embodied in various forms, some examples of which are described below.
Fig. 1a and 1b show a circuit diagram and a structural schematic diagram, respectively, of a memory structure (also called a memory cell string) of a 3D memory device. The memory structure shown in this embodiment includes a case of 4 memory cells. It is understood that the present invention is not limited thereto, and the number of memory cells in the memory structure may be any number, for example, 1 or 2 or 32 or 64, etc.
As shown in FIG. 1a, the memory structure 100 has a first terminal for coupling to a first Bit Line (Bit-Line _ a, BL _ a) and a second terminal for coupling to a second Bit Line (Bit-Line _ b, BL _ b). Memory structure 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first select transistor Q1, memory transistors M1-M4, and a second select transistor Q2. The gate of the first select transistor Q1 is connected to the top select gate line TSG. The gate of the second select transistor Q2 is connected to the bottom select gate line BSG. The gates of the memory transistors M1 to M4 are connected to corresponding ones of Word lines (Word-Line) WL1 to WL4, respectively.
As shown in fig. 1b, the select transistors Q1 and Q2 of the memory structure 100 include a top gate conductor layer 122 and a bottom gate-to-body layer 123, respectively, and the memory transistors M1-M4 include a gate conductor layer 121, respectively. The gate conductor layers 121, 122 and 123 are in accordance with the stacking order of the transistors in the memory structure 100, and adjacent gate conductor layers are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory structure 100 includes a channel pillar 110. The channel pillar 110 is adjacent to or through the gate stack structure. In the middle portion of the channel pillar 110, a tunnel dielectric layer 112, a charge storage layer 113, and a gate dielectric layer 114 are interposed between the gate conductor layer 121 and the channel layer 111, thereby forming memory transistors M1 through M4. Gate dielectric layers 114 are sandwiched between the gate conductor layers 122 and 123 and the channel layer 111 at both ends of the channel pillar 110, thereby forming selection transistors Q1 and Q2.
In this embodiment, the channel layer 111 is composed of, for example, polysilicon, the tunnel dielectric layer 112 and the gate dielectric layer 114 are respectively composed of an oxide such as silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals such as silicon nitride containing particles of a metal or a semiconductor, and the gate conductor layers 121, 122, and 123 are composed of a metal such as tungsten. The channel layer 111 serves to provide channel regions of the control selection transistor and the control transistor, and the doping type of the channel layer 111 is the same as that of the selection transistor and the control transistor. For example, for an N-type select transistor and control transistor, the channel layer 111 may be N-type doped polysilicon.
In this embodiment, the core of channel pillar 110 is channel layer 111, and tunnel dielectric layer 112, charge storage layer 113, and gate dielectric layer 114 form a stacked structure around the core sidewall. In an alternative embodiment, the core of channel pillar 110 is an additional insulating layer, and channel layer 111, tunnel dielectric layer 112, charge storage layer 113, and gate dielectric layer 114 form a stacked structure surrounding the semiconductor layers.
In this embodiment, the selection transistors Q1 and Q2, and the memory transistors M1 to M4 use the common channel layer 111 and gate dielectric layer 114. In the channel pillar 110, the channel layer 111 provides source-drain regions and a channel layer of a plurality of transistors. In an alternative embodiment, the semiconductor layer and the gate dielectric layer of the selection transistors Q1 and Q2 and the semiconductor layer and the gate dielectric layer of the memory transistors M1 to M4, respectively, may be formed in separate steps from each other. In the channel column 110, semiconductor layers of the selection transistors Q1 and Q2 and semiconductor layers of the memory transistors M1 to M4 are electrically connected to each other.
In some other embodiments, the selection transistor Q1 may also be fabricated as a memory transistor M1-M4, specifically, on the upper portion of the channel pillar 110, with the tunnel dielectric layer 112, the charge storage layer 113, and the gate dielectric layer 114 sandwiched between the gate conductor layer 121 and the channel layer 111, thereby forming the selection transistor Q1. Since the selection transistor Q1 has the same structure as the memory transistors M1 to M4, the formation process of the channel column can be simplified.
Fig. 1c and 1d are schematic diagrams illustrating a memory structure according to an embodiment of the present invention.
In a programming operation, as shown in conjunction with fig. 1 a-1 d, memory structure 100 utilizes FN tunneling to write data to selected ones of memory transistors M1-M4. Taking the memory transistor M2 as an example, the first bit line BL _ a and the second bit line BL _ b are grounded, and the top gate selection line TSG and the bottom gate selection line BSG are both biased to the high voltage VDD, so that the selection transistors Q1, Q2 corresponding to the top gate selection line TSG and the bottom gate selection line BSG are turned on. Word line WL2 is biased at a programming voltage VPG, e.g., around 20V, and the remaining word lines are biased at a low voltage VPS 1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons 10 move (arrow direction) from the first and second ends of the channel pillar 110 toward the channel region of the memory transistor M2 and then reach the charge storage layer 113 through the tunnel dielectric layer 112, thereby converting data into charges to be stored in the charge storage layer 113 of the memory transistor M2.
In the erase operation, taking the memory transistor M2 as an example, the top gate selection line TSG and the bottom gate selection line BSG are both biased to the high voltage VDD, so that the selection transistors Q1, Q2 corresponding to the top gate selection line TSG and the bottom gate selection line BSG are turned on. The first bit line BL _ a and the second bit line BL _ b are both biased to the high voltage VDD, the word line WL2 is biased to the erase voltage VES, holes move from the first end and the second end of the channel pillar 110 to the channel region of the memory transistor M2, and then reach the charge storage layer 113 through the tunnel dielectric layer 112, and at the same time or along with the channel region reached by the electrons 10 in the charge storage layer 113 of the memory transistor M2 through the tunnel dielectric layer 112. In another case, only the channel region is accompanied by electrons 10 in the charge storage layer 113 of the memory transistor M2 reaching through tunnel dielectric layer 112.
In a read operation, the memory structure 100 determines the amount of charge in the charge storage layer based on the on-state of a selected one of the memory transistors M1-M4, thereby obtaining data indicative of the amount of charge. Taking the memory transistor M2 as an example, the word line WL2 is biased at the read voltage VRD, and the remaining word lines are biased at the high voltage VPS 2. The on state of the memory transistor M2 is related to its threshold voltage, i.e., the amount of charge in the charge storage layer, so that a data value can be determined according to the on state of the memory transistor M2. The memory transistors M1, M3, and M4 are always in a conductive state, and thus, the conductive state of the memory structure 100 depends on the conductive state of the memory transistor M2. The control circuit determines the conductive state of the memory transistor M2 according to the electric signals detected on the first bit line BL _ a and the second bit line BL _ b, thereby obtaining the data stored in the memory transistor M2.
As shown in fig. 1d, a plurality of gate conductor layers 124(DMY) may be further included in the gate stack structure, and are located between the gate conductor layers 122 and 121 and between the gate conductor layers 123 and 121, and if the number of the gate conductor layers 121 is multiple, the gate conductor layer 124 is also located between the adjacent gate conductor layers 121. Accordingly, the plurality of transistors further includes a plurality of dummy transistors between the first select transistor Q1 and the memory transistor M1, between the second select transistor Q2 and the M4 memory transistor, and between the adjacent memory transistors M1, M2, M3, and M4. The gate conductor layer 124(DMY) is used for process and electrical buffering.
Fig. 2 illustrates a structural diagram of a plurality of memory blocks of a 3D memory device.
As shown in fig. 2, the 3D memory device includes a plurality of memory blocks 1000, and each of the memory blocks 1000 may include therein structures extending in a first direction X, a second direction Y, and a third direction Z crossing each other, for example, each of the memory blocks 1000 has therein a memory structure 100 extending in the Z direction.
Fig. 3 shows a circuit schematic of each memory block of the first embodiment of the present invention.
As shown in fig. 3, the memory structures are arranged in an array, and in each memory block, the gates of the transistors in the same layer are connected through the same gate conductor layer. The gate of the first select transistor of each memory structure is connected to a uniform top select gate line TSG, the gate of the second select transistor is connected to a uniform bottom select gate line BSG, and the gates of the memory transistors are connected to respective word lines W1-W4. The first end of each column of memory structures is connected to a respective first bit line BL _ a 1-BL _ a3, and the second end of each column of memory structures is connected to a respective second bit line BL _ b 1-BL _ b 3. Each memory block 1000 is divided into a plurality of sub-memory blocks 1001 by the above circuit connection method, and each sub-memory block 1001 is configured by a column memory structure.
Fig. 4 shows a circuit schematic of each memory block of the second embodiment of the present invention.
As shown in fig. 4, the memory structures are arranged in an array, and in each memory block, the gates of the transistors located in the same layer are connected through the same gate conductor layer. The gate of the first select transistor of each memory structure is connected to a uniform top select gate line TSG, the gate of the second select transistor is connected to a uniform bottom select gate line BSG, and the gates of the memory transistors are connected to respective word lines W1-W4. The first ends of each column of memory structures are connected to a respective first bit line BL _ a 1-BL _ a3, and the second ends of each row of memory structures are connected to a respective second bit line BL _ b 1-BL _ b 3. By the above circuit connection manner, each memory block 1000 is divided into a plurality of sub memory blocks 1001, and each sub memory block 1001 is configured by one memory structure.
Fig. 5 is a schematic diagram of effect analysis according to an embodiment of the present invention.
As shown in fig. 5, in some conventional 3D memory devices, a gate stack structure 210 located on a substrate 201 is intersected by an array common-source structure (ACS)230, and the array common-source structure 230 forms an electrical connection with each channel pillar 110 through a source region 230 located in the substrate 201.
Since the array common-source structure is used to provide a common source signal to all the channel pillars 210 in each memory block, as the number of layers of the gate stack structure of the 3D memory device increases, the array common-source structure 230 is used to provide a common source signal to all the channel pillars 210, which causes a large noise, and as the memory block capacity increases, there are many problems of redundant operations in programming and/or erasing the memory block. For example, to erase or program a part of data in a memory block, all data in the entire memory block needs to be backed up first, and when the storage capacity of a memory block increases, the amount of data to be backed up increases, thereby causing many redundant operations. In addition, programming and/or erase speed can be affected.
According to the 3D memory device, the memory structure and the control method of the memory structure of the 3D memory device, the first end and the second end of the channel column are respectively connected to the first bit line and the second bit line, so that the first bit line and the second bit line provide carriers with the same electrical property to the channel of each transistor under the programming and/or erasing operation, and since the carriers are provided into the channel of the transistor from two directions, compared with the scheme of providing the carriers from one direction in the prior art, the two directions can improve the programming/erasing speed of the device.
Further, since the second terminal of the memory structure is already connected to the second bit line, the array common source structure in the prior art is replaced, thereby improving the noise problem of the device.
Furthermore, since each memory block of the 3D memory device is divided into a plurality of sub memory blocks, each sub memory block is composed of a column or a memory structure, data in each sub memory block can be individually controlled under a program or erase operation, i.e., the program or erase operations between each sub memory block are not affected by each other, thereby improving the problem of redundant operation of the device.
Therefore, the 3D memory device and the memory structure thereof according to the embodiments of the present invention improve the performance of a product.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.

Claims (10)

1. A memory structure of a 3D memory device, comprising a plurality of transistors connected in series between a first terminal and a second terminal, the plurality of transistors comprising:
a first selection transistor having a gate connected to the top selection gate line;
a second selection transistor having a gate connected to the bottom selection gate line; and
at least one memory transistor connected in series between the first select transistor and the second select transistor, each memory transistor having a gate connected to a respective word line,
the first end of the memory structure is used for being connected to a first bit line, the second end of the memory structure is used for being connected to a second bit line, and the first bit line and the second bit line are used for providing carriers with the same electrical property for channels of the transistors under the programming and/or erasing operation.
2. The memory structure of claim 1, wherein the plurality of transistors further comprises a plurality of dummy transistors between the first select transistor and the memory transistor and between the second select transistor and the memory transistor.
3. The memory structure according to claim 2, wherein the number of the memory transistors is plural, and the dummy transistor is further located between the adjacent memory transistors.
4. A memory structure according to any one of claims 1 to 3, wherein the gates of the transistors and the respective top gate select line, bottom gate select line and word line are formed on the basis of respective gate conductor layers in a gate stack, the channel of each transistor being formed on the basis of a channel pillar extending through the gate stack.
5. The memory structure of claim 4, wherein the channel pillar comprises a gate dielectric layer, a charge storage layer, a tunneling dielectric layer, and the channel layer sequentially arranged along a radially inward direction of the channel pillar.
6. A control method for controlling a memory structure as claimed in any one of claims 1 to 5, comprising simultaneously providing the same signal to the first bit line and the second bit line.
7. A 3D memory device comprising at least one memory block, each of the memory blocks having a plurality of memory structures according to any one of claims 1 to 5 arranged in an array.
8. The 3D memory device of claim 7, wherein the first end of each column of memory structures in each of the memory blocks is connected to a same first bit line,
the second end of each row of memory structures in each of the memory blocks is connected to the same second bit line.
9. The 3D memory device of claim 7, wherein each column of memory structures in each of the memory blocks has a first terminal connected to a same first bit line and a second terminal connected to a same second bit line.
10. The 3D memory device according to claim 8 or 9, wherein in each of the memory blocks, gates of the transistors located in the same layer are connected through the same gate conductor layer.
CN202010705237.5A 2020-07-21 2020-07-21 3D memory device, memory structure thereof and control method of memory structure Pending CN112018118A (en)

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