CN112003612A - Delay module and ring oscillator - Google Patents

Delay module and ring oscillator Download PDF

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Publication number
CN112003612A
CN112003612A CN202010792148.9A CN202010792148A CN112003612A CN 112003612 A CN112003612 A CN 112003612A CN 202010792148 A CN202010792148 A CN 202010792148A CN 112003612 A CN112003612 A CN 112003612A
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mos tube
mos
mos transistor
output
electrode
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Chinese (zh)
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苏杰
徐祎喆
朱勇
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Chongqing Bairui Internet Electronic Technology Co ltd
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Chongqing Bairui Internet Electronic Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

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Abstract

The application discloses delay module and ring oscillator belongs to integrated circuit technical field. The delay module of the present application includes: the MOS transistor comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor and a seventh MOS transistor; and oscillation is formed through the negative feedback of the series current of the common source node of the second MOS tube and the fifth MOS tube and the positive feedback of the parallel voltage of the source-drain electrodes of the fourth MOS tube and the seventh MOS tube. The ring oscillator comprises N delay modules, wherein N is an odd number larger than 1, the N delay modules are sequentially connected, and two output ends of an Nth delay module in the N delay modules are correspondingly connected with two input ends of a first delay module in the N delay modules. The delay module adopts a high-gain open-loop comparator structure which uses internal positive feedback to realize hysteresis, weakens the influence of power supply voltage fluctuation and stably outputs oscillation frequency.

Description

Delay module and ring oscillator
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to a delay module and a ring oscillator.
Background
Oscillators are an integral part of many electronic systems, applications ranging from clock generation in microprocessors to carrier synthesis in cellular telephones, requiring widely varying structural and performance parameters. The design of stable, high performance oscillators using CMOS processes continues to present a significant challenge.
In the prior art, a loop formed by cascading CMOS inverters generates oscillation, so that the power supply voltage fluctuation inhibition capability is weak. When the power supply voltage changes, the oscillation frequency changes with the change of the power supply voltage, so that the frequency stability of the ring oscillator is not high, and a stable clock cannot be provided.
Drawings
FIG. 1 is a schematic diagram of one embodiment of a delay module of the present application;
FIG. 2 is a schematic diagram of one embodiment of a ring oscillator of the present application;
FIG. 3 is a schematic diagram of one embodiment of an output shaping and buffering circuit in a ring oscillator according to the present application.
Detailed Description
In order to make the aforementioned features and advantages of the present application more comprehensible, the present application is described in further detail below with reference to the accompanying drawings and the detailed description. This detailed description is merely intended to facilitate an understanding of the present application and the scope of the present application is not limited to the specific description in the specific embodiments.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Fig. 1 shows a specific embodiment of a delay module of the present application, in which a delay module of the present application mainly comprises: a first MOS transistor 1, a second MOS transistor 2, a third MOS transistor 3 and a fourth MOS transistorA fourth MOS transistor 4, a fifth MOS transistor 5, a sixth MOS transistor 6 and a seventh MOS transistor 7; wherein, the source electrode and the substrate of the first MOS tube 1 are connected with an external power supply VDDThe grid of the first MOS tube 1 is connected with a bias voltage VPThe drain electrode of the first MOS tube 1 is connected with the source electrode of the second MOS tube 2 and the source electrode of the fifth MOS tube 5; the grid of the second MOS tube 2 is connected with the first input end, the drain of the second MOS tube 2 is connected with the drain of the third MOS tube 3 and the first output end, the substrate of the second MOS tube 2 is connected with an external power supply VDDWherein the first output terminal is in anti-phase with the first input terminal; the drain electrode of the third MOS tube 3 is connected with the grid electrode, and the source electrode of the third MOS tube 3 is grounded with the substrate; the grid electrode of the fourth MOS tube 4 is connected with the grid electrode of the third MOS tube, the source electrode of the fourth MOS tube 4 is grounded with the substrate, and the drain electrode of the fourth MOS tube 4 is connected with the second output end; the grid electrode of the fifth MOS tube 5 is connected with the second input end, the drain electrode of the fifth MOS tube 5 is connected with the drain electrode and the second output end of the sixth MOS tube 6, and the substrate of the fifth MOS tube 5 is connected with an external power supply VDDThe first input end and the second input end are two differential input ends; the grid electrode of the sixth MOS tube 6 is connected with the drain electrode, and the source electrode of the sixth MOS tube 6 is grounded with the substrate; the grid electrode of the seventh MOS tube 7 is connected with the grid electrode of the sixth MOS tube 6, the source electrode of the seventh MOS tube 7 is grounded with the substrate, and the drain electrode of the seventh MOS tube 7 is connected with the first output end.
In a specific embodiment of the present application, the first input is a differential positive input.
In a specific embodiment of the present application, the first MOS transistor, the second MOS transistor, and the fifth MOS transistor are PMOS transistors, and the third MOS transistor, the fourth MOS transistor, the sixth MOS transistor, and the seventh MOS transistor are NMOS transistors.
It is noted that the bias voltage required in the delay block can be obtained by a common bias circuit.
In particular, the delay module is a hysteresis comparator with positive feedback. The delay module comprises two feedback paths, wherein one feedback path is series current negative feedback through a common source node of a second MOS tube 2 and a fifth MOS tube 5, and the other feedback path is parallel voltage positive feedback connecting a source electrode and a drain electrode of a fourth MOS tube 4 and a seventh MOS tube 7. When the positive feedback coefficient is smaller than the negative feedback coefficient, the whole delay module will be negative feedback, and the delay is lostThe effect is achieved; when the positive feedback coefficient is larger than the negative feedback coefficient, the whole delay module will behave as positive feedback, while hysteresis will occur in the voltage transfer curve. As long as the width-to-length ratio beta of the fourth MOS transistor 4 is larger4Is lower than the width-to-length ratio beta of the third MOS transistor 33The transfer function has no hysteresis; when the width-to-length ratio beta of the fourth MOS transistor 44Is higher than the width-to-length ratio beta of the third MOS tube 33The transfer function will experience hysteresis. The basic principle is that only V is input when the input signal is positive inputINPThe second MOS transistor 2 is turned on, and the fifth MOS transistor 5 is turned off. When the input signal is negative input, only V is inputINNThe second MOS transistor 2 is turned off, and the fifth MOS transistor 5 is turned on. Suppose the gate input INP of the second MOS transistor 2 and VINP＝VDDWhen the input of the fifth MOS transistor 5 is far lower than VDDWhen the first MOS tube 1 is used, the second MOS tube 2 is switched on, the fifth MOS tube 5 is switched off, so that the third MOS tube 3 and the fourth MOS tube 4 are switched on, the sixth MOS tube 6 and the seventh MOS tube 7 are switched off, and the tail current i output through the first MOS tube 1 is output1All the current flows through the second MOS transistor 2 and the third MOS transistor 3, so that the second output node OUTP is low. With VINNContinuously increasing towards the threshold point, i1Starts to flow through the fifth MOS transistor 5, and this continues until i5＝i1. When V isINNWhen the threshold point is increased, the comparator changes state, most of i1Will flow through the fifth MOS transistor 5 and the sixth MOS transistor 6. Then, the seventh MOS transistor 7 is turned on, and the third MOS transistor 3, the fourth MOS transistor 4 and the second MOS transistor 2 are turned off. Similarly, with VINNThe input is reduced, the circuit of the delay module reaches a certain point, so that the current in the second MOS tube 2 is increased to be equal to that in the seventh MOS tube 7, and the oscillation is formed through the loop repetition.
In the specific embodiment shown in fig. 1, the delay module of the present application adopts a high-gain open-loop comparator structure that uses internal positive feedback to implement hysteresis, so as to weaken the influence of power supply voltage fluctuation and stabilize the output oscillation frequency.
Figure 2 shows a specific embodiment of the ring oscillator of the present application. In this embodiment, the ring oscillator of the present application includes N delay modules, where N is an odd number greater than 1, the N delay modules are sequentially connected, and two output terminals of an nth one of the N delay modules are correspondingly connected to two input terminals of a first one of the N delay modules.
It should be noted that the unit structures and parameters of the N delay modules are the same to ensure that the frequency characteristics and amplitudes of the output clock signals are consistent.
In the embodiment shown in fig. 2, the ring oscillator further comprises a load capacitor module, wherein the load capacitor module has 2N, and each of the 2N load capacitor modules is connected to one output terminal of each of the N delay modules.
Specifically, the load capacitor module is a simple capacitor model, and the load capacitor module may be composed of a load capacitor, or may be composed of an MOS transistor and a load capacitor. The load capacitance module is used for changing the oscillation frequency through the change of capacitance. Therefore, the delay time of the delay module can be obtained by calculating the delay time of the delay module through the output swing, the load capacitance and the tail current; the oscillation frequency can be calculated by the delay time and the number of stages.
In the technical solution of the present application, the ring oscillator further includes an output shaping and buffering circuit. Two input ends of the output shaping and buffering circuit are correspondingly connected with two output ends of the N delay modules, wherein the output shaping and buffering circuit is used for adjusting oscillation signals output by the N delay modules and used for outputting square wave oscillation signals.
It is to be noted that the present embodiment is illustrated by three delay modules, which are not limited thereto, and other odd-numbered stage structures, such as 5/7/9, can achieve the same effect, and it should be understood by those skilled in the art that the detailed description is omitted herein. When N equals 3, 3 delay modules are connected in series in sequence, and two output ends of the third delay module are connected with the input end of the first delay module. The 6 load capacitance modules are connected to two output ends of the 3 delay modules in sequence, and the output shaping and buffering circuit is connected to the output end of the second delay module.
Fig. 3 shows a specific embodiment of an output shaping and buffering circuit in a ring oscillator of the present application, where the output shaping and buffering circuit includes: a mirroring unit, a startup unit and a shaping buffer unit, wherein,
a mirror unit which supplies a mirror current to the starting unit;
the starting unit is connected with the mirror image unit, the input end of the starting unit is used as the input end of the output shaping and buffering circuit, and the starting unit is used for eliminating the degeneracy bias point of the mirror image unit;
and the output end of the shaping buffer unit is used as the output end of the output shaping and buffering circuit, and the shaping buffer unit shapes the oscillation signal output by the starting unit and outputs a square wave oscillation signal.
In the particular embodiment shown in fig. 3, the activation unit comprises: an eighth MOS transistor 8, a ninth MOS transistor 9, a tenth MOS transistor 10, an eleventh MOS transistor 11, a first capacitor 12, and a second capacitor 13. Wherein
The grid electrode of the eighth MOS tube 8 is connected with the second output end of the delay module, the source electrode of the eighth MOS tube 8 is connected with the output end of the mirror image unit, the drain electrode of the eighth MOS tube 8 is connected with the drain electrode and the third output end of the tenth MOS tube 10, and the substrate of the eighth MOS tube 8 is connected with an external power supply VDDWherein the second output terminal is in anti-phase with the third output terminal; the grid electrode of the ninth MOS tube 9 is connected with the first output end of the delay module, the source electrode of the ninth MOS tube 9 is connected with the output end of the mirror image unit, the drain electrode of the ninth MOS tube 9 is connected with the drain electrode and the fourth output end of the eleventh MOS tube 11, and the substrate of the ninth MOS tube 9 is connected with an external power supply VDD(ii) a The grid electrode of the tenth MOS tube 10 is connected with one end of the first capacitor and is connected with the third output end, and the source electrode of the tenth MOS tube 10 is grounded with the substrate; the grid electrode of the eleventh MOS tube 11 is connected with one end of the second capacitor 13 and is connected with the fourth output end, and the source electrode of the eleventh MOS tube 11 and the substrate are grounded; the other terminal of the first capacitor 12 and the other terminal of the second capacitor 13 are grounded.
In this embodiment, the eighth MOS transistor 8 and the ninth MOS transistor 9 are PMOS transistors, and the tenth MOS transistor 10 and the eleventh MOS transistor 11 are NMOS transistors.
In the particular embodiment shown in fig. 3, the mirroring unit comprises: a twelfth MOS transistor 14, a thirteenth MOS transistor 15 and a fourteenth MOS transistor 16. Wherein the content of the first and second substances,
the grid of the twelfth MOS tube 14 is connected with a bias voltage VPAnd the source of the fourteenth MOS tube 16 is connected, and the source of the twelfth MOS tube 14 and the substrate are connected with an external power supply VDD(ii) a The source electrode and the substrate of the thirteenth MOS tube 15 are connected with an external power supply VDDThe grid electrode of the thirteenth MOS tube 15 is connected with the drain electrode of the fourteenth MOS tube 16, and the drain electrode of the thirteenth MOS tube 15 is connected with the drain electrode of the twelfth MOS tube 14 and serves as the output end of the mirror image unit; the gate of the fourteenth MOS transistor 16 is connected to an externally input control signal badjb, and the substrate of the fourteenth MOS transistor 16 is connected to an external power supply VDD。
In this embodiment, the twelfth MOS transistor 14, the thirteenth MOS transistor 15 and the fourteenth MOS transistor 16 are PMOS transistors.
Specifically, the control signal badjb is used to adjust the operating currents of the eighth MOS transistor 8, the ninth MOS transistor 9, the tenth MOS transistor 10, and the eleventh MOS transistor 11, and when badjb is 1.2V, the fourteenth MOS transistor 16 is turned off, the operating current is half of the normal operating current, and the power consumption is further reduced. When badjb is equal to 0V, the operating current is the normal operating current.
In the specific embodiment shown in fig. 3, the shaping buffer unit includes: a fifteenth MOS transistor 17, a sixteenth MOS transistor 18, a seventeenth MOS transistor 19, a third capacitor 20, an eighteenth MOS transistor 21, a nineteenth MOS transistor 22, a twentieth MOS transistor 23, a twenty-first MOS transistor 24, a twenty-twelfth MOS transistor 25, a fourth capacitor 26, a twenty-third MOS transistor 27, a twenty-fourteenth MOS transistor 28, a fifth capacitor 29, and a sixth capacitor 30. Wherein the content of the first and second substances,
the source and the substrate of the seventeenth MOS transistor 19, one end of the third capacitor 20, the source and the substrate of the eighteenth MOS transistor 21, the drain and the substrate of the nineteenth MOS transistor 22, the source and the substrate of the twenty-first MOS transistor 24 and the source and the substrate of the twenty-third MOS transistor 27 are respectively connected with an external power supply VDDThe source and the substrate of the fifteenth MOS transistor 17, the source and the substrate of the sixteenth MOS transistor 18, the drain and the substrate of the twentieth MOS transistor 23, the source and the substrate of the twenty-second MOS transistor 25 and the source and the substrate of the twenty-fourth MOS transistor 28 are grounded,
the grid electrode of the seventeenth MOS tube 19 is connected with the other end of the third capacitor 20 and is connected with the grid electrode of the eighteenth MOS tube 21, the drain electrode of the seventeenth MOS tube 19 is connected with the grid electrode, the drain electrode of the seventeenth MOS tube 19 is connected with the drain electrode of the fifteenth MOS tube 17, the grid electrode of the fifteenth MOS tube 17 is connected with the third output end,
the drain of the eighteenth MOS transistor 21 is connected to the drain of the sixteenth MOS transistor 18, the source of the nineteenth MOS transistor 22, the source of the twentieth MOS transistor 23, the gate of the twenty-first MOS transistor 24, the gate of the twenty-second MOS transistor 25, and one end of the fourth capacitor 26, the gate of the sixteenth MOS transistor 18 is connected to the fourth output terminal,
the drain of the twenty-first MOS transistor 24 is connected to the gate of the nineteenth MOS transistor 22, the gate of the twentieth MOS transistor 23, the drain of the twenty-second MOS transistor 25, the gate of the twenty-third MOS transistor 27, the gate of the twenty-fourth MOS transistor 28 and one end of the fifth capacitor 29,
the drain of the twenty-third MOS transistor 27, which serves as the output of the output shaping and buffering circuit, is connected to the drain of the twenty-fourth MOS transistor 28 and to one terminal of a sixth capacitor 30,
the substrate of the nineteenth MOS tube 22 is grounded, and the substrate of the twentieth MOS tube 23 is connected with an external power supply VDDThe other terminal of the fourth capacitor 26, the other terminal of the fifth capacitor 29 and the other terminal of the sixth capacitor 30 are grounded.
In this specific embodiment, the fifteenth MOS transistor 17, the sixteenth MOS transistor 18, the nineteenth MOS transistor 22, the twelfth MOS transistor 25, and the twenty-fourth MOS transistor 28 are NMOS transistors; the seventeenth MOS transistor 19, the eighteenth MOS transistor 21, the twentieth MOS transistor 23, the twenty-first MOS transistor 24, and the twenty-third MOS transistor 27 are PMOS transistors.
Specifically, the tenth MOS transistor 10, the eleventh MOS transistor 11, the first capacitor 12, and the second capacitor 13 in the start-up unit are used to eliminate a degenerated bias point, and the tenth MOS transistor 10 and the eleventh MOS transistor 11 are used to prevent a negative voltage from appearing across the first capacitor 12 and the second capacitor 13 when the output shaping and buffering circuit is just powered on. The twelfth MOS tube 14 and the thirteenth MOS tube 15 in the mirror image unit are two current mirrors, the fourteenth MOS tube 16 controls whether the twelfth MOS tube 14 and the thirteenth MOS tube 15 are connected in parallel, and the introduction of the mirror image current can enable the oscillator to start oscillation more easily. When the output shaping and buffer circuit is powered on, the eighth MOS transistor 8 and the ninth MOS transistor 9 are conducted, and the eighth MOS transistor is connected with the ninth MOS transistorThe voltage difference between the two ends of the first capacitor 12 and the second capacitor 13 is 0, and the current mirror unit charges the first capacitor 12 and the second capacitor 13, so that the voltage between the two ends of the first capacitor 12 and the second capacitor 13 is close to the external voltage VDDTherefore, the fifteenth MOS transistor 17 is connected to the sixteenth MOS transistor 18, the seventeenth MOS transistor 19 is duplicated to the eighteenth MOS transistor 21 by a current mirror, and the sine wave is converted into a square wave by three groups of inverters, namely, a nineteenth MOS transistor 22, a twentieth MOS transistor 23, a twenty-first MOS transistor 24, a twenty-second MOS transistor 25, a twenty-third MOS transistor 27 and a twenty-fourth MOS transistor 28, and is output.
In the specific embodiment shown in fig. 3, the output end of the output shaping and buffering circuit introduces the inverter formed by the nineteenth MOS transistor 22 and the twentieth MOS transistor 23 for negative feedback, and can reversely superimpose a certain proportion of output signals onto input signals, so that the input variation range of the output shaping and buffering circuit is reduced, the inverter is forced to operate in a linear region, the stability is improved, and the output amplitude is stabilized.
The above embodiments are merely examples, which are not intended to limit the scope of the present disclosure, and all equivalent structural changes made by using the contents of the specification and the drawings, or any other related technical fields, are also included in the scope of the present disclosure.

Claims (10)

1. A delay module, comprising: the MOS transistor comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor and a seventh MOS transistor; wherein the content of the first and second substances,
the source electrode and the substrate of the first MOS tube are connected with an external power supply, the grid electrode of the first MOS tube is connected with bias voltage, and the drain electrode of the first MOS tube is connected with the source electrode of the second MOS tube and the source electrode of the fifth MOS tube;
the grid electrode of the second MOS tube is connected with a first input end, the drain electrode of the second MOS tube is connected with the drain electrode of the third MOS tube and a first output end, the substrate of the second MOS tube is connected with an external power supply, and the first output end and the first input end are in opposite phase;
the drain electrode of the third MOS tube is connected with the grid electrode, the grid electrode of the third MOS tube is connected with the grid electrode of the fourth MOS tube, the source electrode and the substrate of the third MOS tube, the source electrode and the substrate of the fourth MOS tube are grounded, and the drain electrode of the fourth MOS tube is connected with the second output end;
the grid electrode of the fifth MOS tube is connected with a second input end, the drain electrode of the fifth MOS tube is connected with the drain electrode of the sixth MOS tube and the second output end, the substrate of the fifth MOS tube is connected with an external power supply, and the first input end and the second input end are two differential input ends;
the grid electrode of the sixth MOS tube is connected with the drain electrode of the seventh MOS tube, the grid electrode of the sixth MOS tube is connected with the grid electrode of the seventh MOS tube, the source electrode and the substrate of the sixth MOS tube, the source electrode and the substrate of the seventh MOS tube are grounded, and the drain electrode of the seventh MOS tube is connected with the first output end.
2. The delay module of claim 1, wherein the first input is a differential positive input.
3. The delay module of claim 1,
the first MOS tube, the second MOS tube and the fifth MOS tube are PMOS tubes, and the third MOS tube, the fourth MOS tube, the sixth MOS tube and the seventh MOS tube are NMOS tubes.
4. A ring oscillator comprising N delay blocks according to any of claims 1-3, wherein N is an odd number greater than 1, the N delay blocks are connected in sequence and two output terminals of an nth one of the N delay blocks are correspondingly connected to two input terminals of a first one of the N delay blocks.
5. The ring oscillator of claim 4 further comprising load capacitance modules, wherein the load capacitance modules are 2N, and each of the 2N load capacitance modules is connected to an output of each of the N delay modules.
6. The ring oscillator of claim 4, further comprising an output shaping and buffering circuit, wherein two input terminals of the output shaping and buffering circuit are connected to two output terminals of the even-numbered ones of the N delay blocks, respectively, and wherein the output shaping and buffering circuit is configured to adjust the oscillating signals output by the even-numbered ones of the N delay blocks, so as to output square wave oscillating signals.
7. The ring oscillator of claim 4, wherein the output shaping and buffering circuit comprises: a mirroring unit, a startup unit and a shaping buffer unit, wherein,
the mirror image unit is used for providing mirror image current for the starting unit;
the starting unit is connected with the mirror image unit, the input end of the starting unit is used as the input end of the output shaping and buffering circuit, and the starting unit is used for eliminating the degeneracy bias point of the mirror image unit;
and the output end of the shaping buffer unit is used as the output end of the output shaping and buffering circuit, and the shaping buffer unit shapes the oscillation signal output by the starting unit and outputs a square wave oscillation signal.
8. The ring oscillator of claim 7, wherein the start-up unit comprises: the power supply comprises an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a first capacitor and a second capacitor; wherein
The grid electrode of the eighth MOS tube is connected with the second output end of the delay module, the source electrode of the eighth MOS tube is connected with the output end of the mirror image unit, the drain electrode of the eighth MOS tube is connected with the drain electrode of the tenth MOS tube and the third output end, the substrate of the eighth MOS tube is connected with an external power supply, and the second output end and the third output end are in reverse phase;
the grid electrode of the ninth MOS tube is connected with the first output end of the delay module, the source electrode of the ninth MOS tube is connected with the output end of the mirror image unit, the drain electrode of the ninth MOS tube is connected with the drain electrode of the eleventh MOS tube and the fourth output end, and the substrate of the ninth MOS tube is connected with an external power supply;
the grid electrode of the tenth MOS tube is connected with one end of the first capacitor and is connected with the third output end, the grid electrode of the eleventh MOS tube is connected with one end of the second capacitor and is connected with the fourth output end, and the source electrode and the substrate of the tenth MOS tube, the source electrode and the substrate of the eleventh MOS tube, and the other end of the first capacitor and the other end of the second capacitor are grounded.
9. The ring oscillator of claim 8, wherein the eighth and ninth MOS transistors are PMOS transistors and the tenth and eleventh MOS transistors are NMOS transistors.
10. The ring oscillator of claim 7, wherein the mirroring unit comprises: a twelfth MOS transistor, a thirteenth MOS transistor, and a fourteenth MOS transistor, wherein
The grid electrode of the twelfth MOS tube is connected with a bias voltage and the source electrode of the fourteenth MOS tube, and the source electrode and the substrate of the twelfth MOS tube are connected with an external power supply;
the source electrode and the substrate of the thirteenth MOS tube are connected with an external power supply, the grid electrode of the thirteenth MOS tube is connected with the drain electrode of the fourteenth MOS tube, and the drain electrode of the thirteenth MOS tube is connected with the drain electrode of the twelfth MOS tube and serves as the output end of the mirror image unit;
the grid electrode of the fourteenth MOS tube is connected with an externally input control signal, and the substrate of the fourteenth MOS tube is connected with an external power supply.
CN202010792148.9A 2020-08-08 2020-08-08 Delay module and ring oscillator Pending CN112003612A (en)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1968016A (en) * 2006-11-24 2007-05-23 华中科技大学 A slow-moving comparator
CN201011715Y (en) * 2006-11-24 2008-01-23 华中科技大学 Delay Comparator
TW201023523A (en) * 2008-12-03 2010-06-16 Mstar Semiconductor Inc Delay cell of ring oscillator and associated method
CN102326332A (en) * 2009-02-23 2012-01-18 高通股份有限公司 Symmetric load delay cell oscillator
CN108306637A (en) * 2018-01-24 2018-07-20 北京时代民芯科技有限公司 A kind of charge pump phase lock loop controlling voltage controlled oscillator using two-way voltage
CN109995363A (en) * 2019-02-28 2019-07-09 南京邮电大学 A kind of annular voltage controlled oscillator of automatic biasing structure
CN110460308A (en) * 2019-08-15 2019-11-15 电子科技大学 A kind of ring voltage-controlled oscillator circuit of wide scope

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1968016A (en) * 2006-11-24 2007-05-23 华中科技大学 A slow-moving comparator
CN201011715Y (en) * 2006-11-24 2008-01-23 华中科技大学 Delay Comparator
TW201023523A (en) * 2008-12-03 2010-06-16 Mstar Semiconductor Inc Delay cell of ring oscillator and associated method
CN102326332A (en) * 2009-02-23 2012-01-18 高通股份有限公司 Symmetric load delay cell oscillator
CN108306637A (en) * 2018-01-24 2018-07-20 北京时代民芯科技有限公司 A kind of charge pump phase lock loop controlling voltage controlled oscillator using two-way voltage
CN109995363A (en) * 2019-02-28 2019-07-09 南京邮电大学 A kind of annular voltage controlled oscillator of automatic biasing structure
CN110460308A (en) * 2019-08-15 2019-11-15 电子科技大学 A kind of ring voltage-controlled oscillator circuit of wide scope

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