JP3491910B2 - Operational amplifier - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving system for operational amplifiers.

[0002]

2. Description of the Related Art Conventionally, an operational amplifier is used to output a predetermined voltage as an output circuit, a predetermined reference voltage is input to the non-inverting input of the operational amplifier, and the output of the operational amplifier is output from the operational amplifier. The method of forming a voltage follower by returning to the inverting input of is often used. An example of the circuit of this voltage follower is shown in the logic diagram of FIG. Figure 2
In (a), 201 is an operational amplifier, and signal 202 is a predetermined reference voltage input to the non-inverting input of the operational amplifier 201. The signal 203 is the output of the operational amplifier 201 and is fed back to the inverting input of the operational amplifier 201. It is well known that by forming a voltage follower in this way, a signal whose impedance is converted into an extremely small value at the same voltage as the predetermined reference voltage signal 202 is obtained at the output 203 of the operational amplifier. There is.

A specific example for realizing the voltage follower is shown in the circuit diagram of FIG. 2 (b). 2 (b) is
This is an example of realizing a voltage follower using a MOS transistor. In FIG. 2B, the signal 213 is a positive power supply, the signal 214 is a negative power supply, the signal 202 is a predetermined reference voltage, the signal 203 is the output of the operational amplifier, 204 is a bias generation circuit, and the P-type MOS transistor 205 is a bias. A constant current circuit whose gate bias is controlled by a signal from the generation circuit 204, P-type MOS transistors 206 and 207 are formed of a differential pair transistor, and N-type MOS transistors 208 and 209 are formed of a mirror circuit, each of which has an equal impedance P. Type MOS transistors 206 and 207
The gate bias of the P-type transistor 210 and the P-type transistor 210 is controlled by the signal from the bias circuit 204, and the constant current circuit becomes the active load of the output signal 203. The capacitor 211 is the phase correction capacitor and the N-type MOS transistor. Reference numeral 212 is an output stage transistor that outputs a predetermined voltage to the output signal 203. P-type MOS transistors 205, 206, 207 and N-type MO
A differential amplifier circuit is formed by the S transistors 208 and 209. The output signal 215 from the differential amplifier circuit is connected to the phase correction capacitor 211 and the gate input of the N-type MOS transistor 212 in the output stage.

The gate of one P-type transistor 206 of the differential pair transistor is the non-inverting input of the operational amplifier,
A signal 202 that is a predetermined reference voltage is input. The other one of the differential pair transistors, P-type transistor 207
The gate of is the inverting input of the operational amplifier, and the signal 203 which is the output of the operational amplifier is fed back. In this way, the voltage follower was formed.

[0005]

However, the above-mentioned conventional technique has the following problems. Generally, in an operational amplifier, when the input voltage changes at a certain speed, the output voltage cannot change at a speed higher than a certain limit value due to the restriction of the tracking performance of the internal circuit of the operational amplifier. It is well known that the value is called a slew rate and shows how many volts the output voltage changes per unit time. It is also well known that the slew rate of an ideal operational amplifier is infinite. Next, the slew rate of the operational amplifier in the circuit diagram of the conventional example of FIG.
The current for operating the differential amplifier circuit, that is, the current limited by the P-type MOS transistor 205 is I1, the capacitive load of the output signal 215 from the differential amplifier circuit, that is, the capacitance of the phase correction capacitor 211 + the N-type MOS transistor 21.
If the parasitic capacitance parasitic on the gate capacitance of 2 + wiring is C1, then the slew rate of the operational amplifier is expressed by the following equation (1).

Slew rate = I1 / C1 (1) From the equation (1), in order to improve the value of the slew rate, in other words, to improve the followability of the output that follows changes in the input voltage of the operational amplifier. The current I1 flowing through the differential amplifier circuit in the operational amplifier may be increased or the capacitive load C1 of the output signal 215 from the differential amplifier circuit may be decreased.
However, the phase correction capacitor 211 is necessary to prevent abnormal oscillation of the operational amplifier, and the N-type MOS transistor 212 of the output stage transistor is a transistor that constitutes the operational amplifier and cannot be deleted. Therefore, it is difficult to significantly reduce the value of the capacitive load C1 described above. On the other hand, similarly, according to the above equation, the value of the slew rate is improved by increasing the current I1 flowing through the differential amplifier circuit, but this is accompanied by an increase in the operating current consumption of the operational amplifier. This is a fatal drawback in a field such as a portable device using a battery as a power source, in which it is necessary to reduce the operating current consumption because it is necessary to prolong the life of the battery. The present invention is to solve the above-mentioned problems, and the object is to maintain the value of the slew rate,
An operational amplifier that operates with low current consumption is provided.

[0007]

The operational amplifier of the present invention comprises:
A first power supply line, a second power supply line supplying a potential different from that of the first power supply line, a first MOS transistor whose source is connected to the first power supply line, and a source connected to the drain of the first MOS transistor. Second and third MOS
A transistor and a source connected to the second power line,
A fourth MOS transistor having a drain connected to the drain of the second MOS transistor; and a source having the second MOS transistor.
The gate and the drain are both connected to the power supply line and the third
A fifth MOS transistor connected to the drain of the MOS transistor and the gate of the fourth MOS transistor, a sixth MOS transistor whose source is connected to the first power supply line, a source connected to the second power supply line, and a gate A seventh MOS transistor connected to the drains of the second and fourth MOS transistors, the drain of which is connected to the gate of the third MOS transistor, the drain of the sixth MOS transistor and the output terminal, and the source of which is connected to the first power supply line. The gate and the drain are both the gate of the first MOS transistor and the sixth MO transistor.
An eighth MOS transistor connected to the gate of the S transistor, a source connected to the second power supply line, a drain connected to the drain of the eighth MOS transistor, and a source connected to the second power supply line. The gate and the drain are both connected and the ninth MO is connected.
A tenth MOS transistor connected to the gate of the S transistor, an eleventh MOS transistor whose source is connected to the first power supply line and a drain thereof is connected to the drain of the tenth MOS transistor, and a gate of the second MOS transistor. A reference voltage signal whose value is periodically switched,
A gate bias signal input to the gate of the 1-MOS transistor, which has a first value for a predetermined time in synchronization with the switching timing of the reference voltage signal, and then a second value until the next switching timing of the reference voltage signal. An operational amplifier having a gate bias signal that holds a value.

[0008]

The operational amplifier of the present invention is the eleventh M
The OS transistor is a depletion type transistor.

[0010]

[0011]

[0012]

According to the present invention, the current consumption of the current source transistor can be controlled by switching the bias of the current source transistor, and by forming a current mirror circuit with the current source transistor, the differential amplification in the operational amplifier is achieved. Since the current consumption of the circuit and the output stage circuit can be controlled in the same way,
The operating current consumption of the operational amplifier can be reduced.

[0013]

EXAMPLES Examples of the present invention will be described below. FIG. 1 shows an embodiment of the present invention. FIG. 1 is a circuit diagram showing an example in which an operational amplifier is composed of MOS transistors. In FIG. 1, 101 is a positive power source and 102 is a negative power source. P type M
The OS transistor 105 is a current source transistor.
The differential amplifier circuit constituting the operational amplifier is P-type MOS transistors 109, 110 and 111 and N-type MOS transistors 112 and 113. P-type MOS transistor 10
Reference numeral 9 is a constant current transistor that supplies a constant current to the differential amplifier circuit, P-type MOS transistors 110 and 111 are differential pair transistors, and N-type MOS transistors 112 and 113 are drains of the differential pair P-type MOS transistors 110 and 111, respectively. Is a load. The output stage circuit forming the operational amplifier is a P-type MOS transistor 114 and an N-type MOS transistor 115. The N-type MOS transistor 115 is an output driver, and the P-type MOS transistor 114 is an N-type MOS.
It is an active load of the transistor 115. Capacitor 11
6 is a phase correction capacitor, which is the output signal 1 of the differential amplifier circuit.
19 and the signal 117 which is the output of the operational amplifier. The non-inverting input of the operational amplifier is the gate input of the P-type MOS transistor 110, and the signal 103 is input. The inverting input of the operational amplifier is the gate input of the P-type MOS transistor 111 and the signal 11 which is the output of the operational amplifier.
7 is feedback input. With this structure, the voltage follower is formed as described in the conventional example.

On the other hand, the P-type MOS transistor 105 is a current source transistor and the N-type MOS transistor 106 and 1
Reference numeral 08 denotes a current mirror circuit, and similarly P-type MOS transistors 107, 109 and 114 form a current mirror circuit. Then, the current flowing in the P-type MOS transistor 105 is set to I2, and in order to make the explanation easy to understand, it is assumed that the N-type MOS transistors 106 and 108 forming the current mirror circuit have the same conductance constant.
Further P-type MOS forming another current mirror circuit
It is assumed that the transistors 107, 109, and 114 have the same conductance constant. Then, due to the function of the current mirror circuit, a current equal to I2 is obtained in the N-type MOS transistor 108, and similarly, the P-type MOS transistor 1
09 and the P-type MOS transistor 114 can also obtain a current equal to I2. Therefore, the operating current consumption in the circuit example of the operational amplifier of FIG. 1 is 4 × I2. That is, a value obtained by multiplying the current flowing through the current source transistor by a certain constant is the operating current consumption of the operational amplifier.

Next, a P-type MOS transistor 1 as a current source
The current I2 flowing in 05 is the P-type MOS transistor 10
5, the threshold voltage is Vtp, the source-gate bias is Vgp, and the conductance constant is Kp.
When operating in the saturation region, the current I2 is given by the following equation (2).

I2 = Kp / 2 (Vgp−Vtp) ² (2) In the equation (2), if the conductance constant Kp and the threshold voltage Vtp are constant, the current I2 depends on the value of the bias Vgp between the source and the gate. It shows that it changes. In the circuit diagram of FIG. 1, a P-type MOS transistor 1
The bias Vgp between the source and gate of 05 can be controlled by the signal 104. Therefore, the operating current consumption of the operational amplifier of FIG. 1 can be controlled by changing the voltage value of the signal 104.

Next, a specific operation will be described with reference to the timing chart of FIG. In FIG. 3 (a),
For the sake of clarity, the same signals as in FIG. 1 are given the same numbers. The signal 103 is a reference voltage input to the non-inverting input of the operational amplifier, the signal 104 is the gate bias of the current source P-type MOS transistor 105 of the operational amplifier,
Signal 117 is the output signal of the operational amplifier. Signal 103
Indicates that the reference voltage is switched in a certain cycle. The gate bias of the current source P-type MOS transistor 105 is constant at -Va with respect to the voltage of the positive power source. The output signal 117 operates to change with the voltage level of the input signal 103, but the input signal 1 is affected by the constraint of the tracking performance of the internal circuit of the operational amplifier, that is, the slew rate.
A predetermined voltage level is reached with a delay of Ta time with respect to the change of 03.

FIG. 3B is a timing chart of the present invention. The signal 103 is the reference voltage input to the non-inverting input of the operational amplifier, the signal 104 is the gate bias of the current source P-type MOS transistor 105 of the operational amplifier, and the signal 117 is the output signal of the operational amplifier. The same signals as in FIG. 3A are given the same numbers. The signal 103 indicates that the reference voltage is switched in a certain cycle. Figure 1
Signal 104, which is the gate bias of the current source P-type MOS transistor 105, is -Vb with respect to the voltage of the positive power source.
It is a binary voltage of 1 and -Vb2, which shows that it changes in time division. Further, the signal 104 is -Vb1 for a predetermined time in synchronization with the switching timing of the voltage of the signal 103.
And the voltage of −Vb2 is maintained until the timing of switching the voltage next to the signal 103. The magnitude relationship between the absolute values of the voltages −Vb1 and −Vb2 is as shown in the following expression (3).

| -Vb1 |> | -Vb2 | (3) The voltages of -Vb1 and -Vb2 are the same as the current source P-type MOS of FIG.
It is the gate bias of the transistor 105. When the gate bias is large, the current flowing through the MOS transistor is large, and when the gate bias is small, the current flowing through the MOS transistor is small, as described in the above equation (2). That's right. Therefore, the current source P-type MO of FIG.
The current flowing through the S transistor 105 is T of the signal 104.
It is large at the timing of c and small at the timing of Td. Then, the current flowing through the differential amplifier circuit in the operational amplifier is large at the timing of Tc of the signal 104 and small at the timing of Td. Therefore, the slew rate of the operational amplifier is high at the timing of Tc with respect to the timing of Td of the signal 104. Become. Therefore, if the voltage value of -Vb1 is set to an appropriate value, the output signal 117 of the operational amplifier becomes the signal 1
With respect to the switching of the voltage of 03, the delay time Tb becomes extremely small and an output close to ideal can be obtained.

Next, the current consumption will be described. As described above, the operating current consumption of the operational amplifier is large at the timing Tc of the signal 104 in FIG. 3 and small at the timing Td. By the way, since the output signal 117 has already reached the predetermined voltage level at the timing of Td,
The operational amplifier need only hold its voltage level.

Therefore, at the timing of Td, the operating current consumption of the operational amplifier can be extremely small. On the other hand, Tc
Although the operational amplifier requires a large amount of current at the timing of, the current consumption at the timing of Tc can be reduced by making the time of Tc longer than the delay time Tb of the output signal 117 within the range of Td as much as possible. The influence of the increase of can be made extremely small.

Next, another embodiment of the present invention in which the P-type MOS transistor 105 which is the current source transistor of the operational amplifier shown in FIG. 1 is a depletion type will be described. When the current source P-type MOS transistor 105 is a depletion type, the gate bias signal 103 of the P-type MOS transistor 105 is given as shown in the timing chart of FIG. In FIG. 4, the same symbols as those in FIG. 3 are attached to the same timings as those in FIG. The signal 103 is T
The timing of c is the negative power supply level, and the timing of Td is the positive power supply level. Since the P-type MOS transistor 105 as a current source is a depletion type, a predetermined current can be obtained by inputting the positive power supply level of the ground level to the gate. Further, by inputting the negative power supply level to the gate, it is possible to obtain a larger amount of current than when the positive power supply level is input to the gate. In this way, the current source transistor of the operational amplifier may be controlled.

In the above description, the bias of the current source transistor is selected to be binary, but of course, it is not necessary that the bias is only binary, and the settling time of the operational amplifier is desired to be shortened. Three or more values may be selected in order to smoothly switch the bias. Also, the positive power source has been described as the ground,
Of course, even if the negative electrode power source is set to the ground, the same effect can be obtained by using the same configuration as that of the present invention. Therefore, although the current source transistor has been described as a P-type MOS transistor, it is an N-type M transistor.
Of course, it is good to use an OS transistor. Further, although the embodiment of the present invention has been described using the MOS transistor,
The same effect can be obtained not only with MOS transistors but also with other types of transistors.

[0024]

According to the present invention, since the slew rate of the operational amplifier can be increased for a predetermined time in synchronization with the switching of the input voltage of the operational amplifier, the delay time of the output voltage that follows the switching of the input voltage. A very small operational amplifier can be obtained.

Further, since the current of the current source transistor for limiting the operating current consumption of the operational amplifier is controlled in a time-division manner, the time of the timing when a large amount of current flows can be reduced, and the time of a timing at which a small amount of current does not flow can be increased. It is possible to obtain an operational amplifier that operates with low current consumption.

Further, since the current source transistor of the operational amplifier is of the depletion type, the current source transistor can be controlled in two values of the positive power source level and the negative power source level, so that at least the binary value for controlling the current source transistor is provided. A circuit for generating a voltage becomes unnecessary, and for example, when the present operational amplifier is built in a semiconductor integrated device, the chip size can be reduced and the chip cost can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2A is a logic diagram showing an example of an operational amplifier. (B) A circuit diagram showing a conventional technology example.

FIG. 3A is a timing chart showing the operation of the operational amplifier. (B) A timing chart showing the operation of the operational amplifier of the present invention.

FIG. 4 is a timing chart showing the operation of the operational amplifier of the present invention.

[Explanation of symbols]

101, 102 ... Power supply lines 103, 117, 118, 119 ... Signal lines 105, 107, 109, 110 ... P-type MOS transistors 111, 114 ... P-type MOS transistors 106, 108, 112, 113 ... N-type MOS transistors 115. N-type MOS transistor 116 ... Capacitor 201 ... Operational amplifier 202, 203 ... Signal line 204 ... Bias circuit 205, 206, 207, 210 ... P-type MOS transistor 208, 209, 212 ... N-type MOS transistor 211 ... Capacitor 213, 214 ... Power line

Claims (2)

(57) [Claims] 1. A first power supply line, a second power supply line supplying a potential different from that of the first power supply line, a first MOS transistor having a source connected to the first power supply line, and a source having the first MOS transistor. Second and third MOS transistors connected to the drain of the transistor, and a fourth MO whose source is connected to the second power supply line and drain is connected to the drain of the second MOS transistor.
An S transistor and a source are connected to the second power supply line, and a gate and a drain are both connected to the drain of the third MOS transistor and the gate of the fourth MOS transistor.
An OS transistor, a sixth MOS transistor whose source is connected to the first power supply line, a source is connected to the second power supply line, and a gate is the second power supply line.
And a seventh MOS transistor connected to the drain of the fourth MOS transistor, the drain of which is connected to the gate of the third MOS transistor, the drain of the sixth MOS transistor and the output terminal, and the source of which is connected to the first power line An eighth MO whose drain and drain are both connected to the gate of the first MOS transistor and the gate of the sixth MOS transistor.
An S-transistor and a ninth MO whose source is connected to the second power line and whose drain is connected to the drain of the eighth MOS transistor.
An S transistor, a source is connected to the second power supply line, a gate and a drain are both connected to the gate of the ninth MOS transistor, a tenth MOS transistor, a source is connected to the first power supply line, and a drain is the above. Eleventh connected to the drain of the tenth MOS transistor
A reference voltage signal input to the gate of the second MOS transistor, the reference voltage signal being cyclically switched in value, and a gate bias signal input to the gate of the eleventh MOS transistor; It becomes a first value for a predetermined time in synchronization with the switching timing of the reference voltage signal,
And a gate bias signal which holds the second value until the next switching timing of the reference voltage signal. 2. The operational amplifier according to claim 1, wherein the eleventh MOS transistor is a depletion type transistor.