CN112003358A - Multi-input environment energy collecting circuit capable of synchronously extracting - Google Patents
Multi-input environment energy collecting circuit capable of synchronously extracting Download PDFInfo
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- CN112003358A CN112003358A CN202010680136.7A CN202010680136A CN112003358A CN 112003358 A CN112003358 A CN 112003358A CN 202010680136 A CN202010680136 A CN 202010680136A CN 112003358 A CN112003358 A CN 112003358A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/34—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering
- H02J7/345—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering using capacitors as storage or buffering devices
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/66—Regulating electric power
- G05F1/67—Regulating electric power to the maximum power available from a generator, e.g. from solar cell
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/34—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering
- H02J7/35—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering with light sensitive cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/56—Power conversion systems, e.g. maximum power point trackers
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Abstract
The invention discloses a multi-input environment energy collecting circuit capable of synchronously extracting, which comprises a first direct current transducer, a second direct current transducer, a third direct current transducer, a first capacitor, a second capacitor, a third capacitor, an output capacitor, an inductor, a freewheeling diode, a first controllable switch, a second controllable switch, a third controllable switch, a fourth controllable switch, a fifth controllable switch, a sixth controllable switch, a sampling pulse generator, a first maximum power point tracker, a second maximum power point tracker, a third maximum power point tracker and a logic controller, wherein the first direct current transducer, the second direct current transducer, the third direct current transducer, the first capacitor, the second capacitor, the third capacitor, the output capacitor, the inductor, the freewheeling diode, the first controllable switch, the second controllable switch, the third controllable switch, the fourth controllable; the advantage is that can extract different direct current source synchronization, and output power is higher.
Description
Technical Field
The invention belongs to the technical field of power management, and particularly relates to a multi-input environment energy collecting circuit capable of synchronously extracting.
Background
The energy converters such as photovoltaic cells, thermoelectric generators and biofuel cells adopt a technology of converting energy in the environment into electric energy, and can supply the electric energy to low-power consumption sensing nodes.
Because a single energy converter has low power under certain conditions, for example, when the light intensity of a photovoltaic cell is insufficient, more and more people start to adopt a multi-source energy capture technology to provide more energy for a load, a time division multiplexing method is generally used by a multi-source energy capture circuit based on a maximum power tracking technology at present, namely, a plurality of energy converters use the same management circuit through a switch, the energy converters are sequenced according to priority and perform charge extraction on each energy converter according to the sequence, and the time division multiplexing has the advantages of reducing the volume of the circuit, reducing the power consumption of the circuit and avoiding the mutual influence among the energy converters and has the defect that two or more than two energy converters cannot be simultaneously extracted. Although a structure in which two transducers are directly connected to a diode and then connected to the same energy transmission node in parallel is proposed, the structure has the advantages that two kinds of energy can be simultaneously extracted, and the disadvantage is that the diodes consume a part of energy, thereby reducing the energy supplied to the load by the transducers.
Disclosure of Invention
The invention aims to provide a multi-input environment energy collecting circuit which can synchronously extract different direct current sources and has higher output power and can synchronously extract.
The technical scheme adopted by the invention for solving the technical problems is as follows: a multi-input environmental energy collecting circuit capable of synchronously extracting comprises a first direct current transducer, a second direct current transducer, a third direct current transducer, a first capacitor, a second capacitor, a third capacitor, an output capacitor, an inductor, a freewheeling diode, a first controllable switch, a second controllable switch, a third controllable switch, a fourth controllable switch, a fifth controllable switch, a sixth controllable switch, a sampling pulse generator, a first maximum power point tracker, a second maximum power point tracker, a third maximum power point tracker and a logic controller, wherein the positive end of the first direct current transducer, one end of the first controllable switch, one end of the first capacitor and the positive input end of the first maximum power point tracker are connected, the other end of the first controllable switch, one end of the second controllable switch and one end of the inductor are connected, the other end of the inductor, one end of the third controllable switch, one end of the fourth controllable switch, one end of the fifth controllable switch and one end of the sixth controllable switch are connected, the other end of the fourth controllable switch, the negative terminal of the second dc transducer, one end of the second capacitor and the negative input end of the second maximum power point tracker are connected, the other end of the fifth controllable switch, the negative terminal of the third dc transducer, one end of the third capacitor and the negative input end of the third maximum power point tracker are connected, the other end of the sixth controllable switch, the positive terminal of the third dc transducer, the other end of the third capacitor, the positive input end of the third maximum power point tracker and the positive electrode of the freewheeling diode are connected, the negative electrode of the freewheeling diode is connected to one end of the output capacitor, the negative terminal of the first dc transducer, the positive terminal of the second dc transducer, the negative input terminal of the first maximum power point tracker, the positive input terminal of the second maximum power point tracker, the other end of the first capacitor, the other end of the second controllable switch, the other end of the third controllable switch, the other end of the second capacitor, and the other end of the output capacitor are all grounded, the output terminal of the sampling pulse generator, the clock input terminal of the first maximum power point tracker, the clock input terminal of the second maximum power point tracker, and the clock input terminal of the third maximum power point tracker are connected, the output terminal of the first maximum power point tracker is connected to the first input terminal of the logic controller, the output end of the second maximum power point tracker is connected with the second input end of the logic controller, the output end of the third maximum power point tracker is connected with the third input end of the logic controller, a first output terminal of the logic controller is connected with a control terminal of the first controllable switch, a second output terminal of the logic controller is connected with a control terminal of the second controllable switch, a third output terminal of the logic controller is connected with a control terminal of the third controllable switch, a fourth output terminal of the logic controller is connected with a control terminal of the fourth controllable switch, a fifth output terminal of the logic controller is connected with a control terminal of the fifth controllable switch, a sixth output end of the logic controller is connected with a control end of the sixth controllable switch, and a logic expression of the logic controller is as follows:
S1＝SIG1
S4＝SIG2
S5＝SIG3
wherein S1 represents a signal output from the first output terminal of the logic controller, S2 represents a signal output from the second output terminal of the logic controller, S3 represents a signal output from the third output terminal of the logic controller, S4 represents a signal output from the fourth output terminal of the logic controller, S5 represents a signal output from the fifth output terminal of the logic controller, S6 represents a signal output from the sixth output terminal of the logic controller, SIG1 represents a signal input from the first input terminal of the logic controller, SIG2 represents a signal input from the second input terminal of the logic controller, and SIG3 represents a signal input from the third input terminal of the logic controller.
The first maximum power point tracker comprises a first resistor, a second resistor, a third resistor, a fourth capacitor, a first comparator, a first NMOS (N-channel metal oxide semiconductor) tube, a first phase inverter and a first AND gate, wherein the positive end of the first direct current transducer, one end of the first resistor and one end of the third resistor are connected, the other end of the first resistor, one end of the second resistor and the source electrode of the first NMOS tube are connected, the other end of the second resistor, the negative end of the first direct current transducer and one end of the fourth capacitor are connected, the other end of the fourth capacitor, the drain electrode of the first NMOS tube and the negative input end of the first comparator are connected, the other end of the third resistor, one end of the fourth resistor and the positive input end of the first comparator are connected, and the other end of the fourth resistor, The output end of the first comparator is connected with one input end of the first AND gate, the grid electrode of the first NMOS tube, the input end of the first phase inverter and the output end of the sampling pulse generator are connected, the output end of the first phase inverter is connected with the other input end of the first AND gate, and the output end of the first AND gate is connected with the first input end of the logic controller;
the second maximum power point tracker comprises a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a fifth capacitor, a second comparator, a second NMOS transistor, a second inverter and a second AND gate, wherein the positive end of the second direct current transducer, one end of the fifth resistor and one end of the seventh resistor are connected, the other end of the fifth resistor, one end of the sixth resistor and the source electrode of the second NMOS transistor are connected, the other end of the sixth resistor, the negative end of the second direct current transducer and one end of the fifth capacitor are connected, the other end of the fifth capacitor, the drain electrode of the second NMOS transistor and the negative input end of the second comparator are connected, the other end of the seventh resistor, one end of the eighth resistor and the positive input end of the second comparator are connected, and the other end of the eighth resistor, the other end of the sixth resistor, one end of the fifth capacitor and one end of the second NMOS transistor are connected, The output end of the second comparator is connected with one input end of the second AND gate, the grid electrode of the second NMOS tube, the input end of the second phase inverter and the output end of the sampling pulse generator are connected, the output end of the second phase inverter is connected with the other input end of the second AND gate, and the output end of the second AND gate is connected with the second input end of the logic controller;
the third maximum power point tracker comprises a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a sixth capacitor, a third comparator, a third NMOS transistor, a third inverter and a third AND gate, wherein the positive end of the third DC transducer, one end of the ninth resistor and one end of the eleventh resistor are connected, the other end of the ninth resistor, one end of the tenth resistor and the source electrode of the third NMOS transistor are connected, the other end of the tenth resistor, the negative end of the third DC transducer and one end of the sixth capacitor are connected, the other end of the sixth capacitor, the drain electrode of the third NMOS transistor and the negative input end of the third comparator are connected, the other end of the eleventh resistor, one end of the twelfth resistor and the positive input end of the third comparator are connected, the other end of the twelfth resistor, the output end of the third comparator and one input end of the third and gate are connected, the grid of the third NMOS tube, the input end of the third inverter and the output end of the sampling pulse generator are connected, the output end of the third inverter is connected with the other input end of the third and gate, and the output end of the third and gate is connected with the third input end of the logic controller.
The sampling pulse generator comprises a clock chip with the type of LTC6995, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor and a seventh capacitor, wherein a first pin of the clock chip, one end of the thirteenth resistor and one end of the seventh capacitor are connected, the other end of the thirteenth resistor, a sixth pin of the clock chip, a clock input end of the first maximum power point tracker, a clock input end of the second maximum power point tracker and a clock input end of the third maximum power point tracker are connected, a third pin of the clock chip is connected with one end of the fourteenth resistor, a fifth pin of the clock chip, one end of the fifteenth resistor and a power voltage are connected, the other end of the fifteenth resistor, a fourth pin of the clock chip and one end of the sixteenth resistor are connected, and the second pin of the clock chip, the other end of the seventh capacitor, the other end of the fourteenth resistor and the other end of the sixteenth resistor are all grounded.
The logic controller comprises a fourth inverter, a fifth inverter, a sixth inverter and a fourth AND gate, wherein the output end of the first maximum power point tracker, the control end of the first controllable switch, the input end of the fourth inverter and one input end of the fourth AND gate are connected, the output end of the fourth inverter is connected with the control end of the second controllable switch, the output end of the second maximum power point tracker, the input end of the fifth inverter and the control end of the fourth controllable switch are connected, the output end of the fifth inverter is connected with the other input end of the fourth AND gate, the output end of the fourth AND gate is connected with the control end of the third controllable switch, the output end of the third maximum power point tracker, the control end of the fifth controllable switch and the input end of the sixth inverter are connected, and the output end of the sixth inverter is connected with the control end of the sixth controllable switch.
Compared with the prior art, the invention has the advantages that the energy transfer process of the circuit is divided into two stages of inductive charging and inductive afterflow, wherein the inductive charging process is determined by the first direct current transducer and the second direct current transducer, one direct current source is determined to charge the inductor or the two direct current transducers and the inductor form a loop to charge the inductor together according to whether the two direct current transducers reach the respective maximum power point or not, the inductive afterflow process is determined by the third direct current transducer, whether the third direct current transducer participates in the inductive afterflow process or not is determined according to whether the third direct current transducer reaches the maximum power point or not, the three direct current sources are ensured to collect energy at the respective maximum power and provide the collected energy to the output capacitor, the three direct current transducers are mutually independent, the energy of one direct current transducer can be separately extracted or the energy of a plurality of direct current transducers can be synchronously extracted, the three direct current transducers are not affected with each other, and the output power of the circuit is high.
Drawings
FIG. 1 is a first schematic diagram of a circuit configuration according to the present invention;
FIG. 2 is a second schematic circuit diagram according to the present invention;
fig. 3 is a schematic circuit diagram of a first maximum power point tracker in an embodiment;
fig. 4 is a schematic circuit diagram of a second maximum power point tracker in an embodiment;
fig. 5 is a schematic circuit diagram of a third maximum power point tracker in an embodiment;
FIG. 6 is a schematic diagram of a circuit configuration of a sampling pulse generator in an embodiment;
fig. 7 is a schematic circuit diagram of the logic controller according to the embodiment.
In the figure: 1. a sampling pulse generator; 2. a first maximum power point tracker; 3. a second maximum power point tracker; 4. a third maximum power point tracker; 5. a logic controller.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
The first embodiment is as follows: as shown in the figure, the multi-input environment energy collecting circuit capable of synchronously extracting comprises a first direct current transducer U1, a second direct current transducer U2, a third direct current transducer U3, a first capacitor C1, a second capacitor C2, a third capacitor C3 and an output capacitor C1STOAn inductor L, a freewheeling diode D1, a first controllable switch S1, a second controllable switch S2, a third controllable switch S3, a fourth controllable switch S4, a fifth controllable switch S5, a sixth controllable switch S6, a sampling pulse generator 1, a first maximum power point tracker 2, a second maximum power point tracker 3, a third maximum power point tracker 4 and a logic controller 5, wherein the positive end of a first direct current transducer U1, one end of the first controllable switch S1, one end of a first capacitor C1 and the positive input end of the first maximum power point tracker 2 are connected with each otherThen, the other end of the first controllable switch S1, one end of the second controllable switch S2 and one end of the inductor L are connected, the other end of the inductor L, one end of the third controllable switch S3, one end of the fourth controllable switch S4, one end of the fifth controllable switch S5 and one end of the sixth controllable switch S6 are connected, the other end of the fourth controllable switch S4 and the negative end of the second dc converter U2, one end of a second capacitor C2 is connected with the negative input end of the second maximum power point tracker 3, the other end of a fifth controllable switch S5, the negative end of a third direct current transducer U3, one end of a third capacitor C3 and the negative input end of a third maximum power point tracker 4 are connected, the other end of a sixth controllable switch S6, the positive end of a third direct current transducer U3, the other end of a third capacitor C3, the positive input end of the third maximum power point tracker 4 and the positive electrode of a freewheeling diode D1 are connected, and the negative electrode of the freewheeling diode D1 is connected with the output capacitor C.STOIs connected with the negative terminal of the first dc transducer U1, the positive terminal of the second dc transducer U2, the negative input terminal of the first maximum power point tracker 2, the positive input terminal of the second maximum power point tracker 3, the other terminal of the first capacitor C1, the other terminal of the second controllable switch S2, the other terminal of the third controllable switch S3, the other terminal of the second capacitor C2, the output capacitor CSTOThe other end of the first and second output terminals of the sampling pulse generator 1, the clock input terminal of the first maximum power point tracker 2, the clock input terminal of the second maximum power point tracker 3 and the clock input terminal of the third maximum power point tracker 4 are all grounded, the output terminal of the first maximum power point tracker 2 is connected with the first input terminal of the logic controller 5, the output terminal of the second maximum power point tracker 3 is connected with the second input terminal of the logic controller 5, the output terminal of the third maximum power point tracker 4 is connected with the third input terminal of the logic controller 5, the first output terminal of the logic controller 5 is connected with the control terminal of the first controllable switch S1, the second output terminal of the logic controller 5 is connected with the control terminal of the second controllable switch S2, the third output terminal of the logic controller 5 is connected with the control terminal of the third controllable switch S3, the fourth output terminal of the logic controller 5 is connected with the control terminal of the fourth controllable switch S4, a fifth output terminal of the logic controller 5 is connected to a control terminal of the fifth controllable switch S5, and a sixth output terminal of the logic controller 5Connected to the control terminal of the sixth controllable switch S6, the logic expression of the logic controller 5 is:
S1＝SIG1
S4＝SIG2
S5＝SIG3
wherein S1 represents a signal output from the first output terminal of the logic controller 5, S2 represents a signal output from the second output terminal of the logic controller 5, S3 represents a signal output from the third output terminal of the logic controller 5, S4 represents a signal output from the fourth output terminal of the logic controller 5, S5 represents a signal output from the fifth output terminal of the logic controller 5, S6 represents a signal output from the sixth output terminal of the logic controller 5, SIG1 represents a signal input from the first input terminal of the logic controller 5, SIG2 represents a signal input from the second input terminal of the logic controller 5, and SIG3 represents a signal input from the third input terminal of the logic controller 5.
Example two: the remaining parts are the same as those of the first embodiment, except that the first maximum power point tracker 2 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fourth capacitor C4, a first comparator CMP1, a first NMOS tube M1, a first inverter INV1, AND a first AND gate AND1, the positive terminal of the first dc transducer U1, one end of the first resistor R1, AND one end of the third resistor R3 are connected, the other end of the first resistor R1, one end of the second resistor R2, AND the source of the first NMOS tube M42 are connected, the other end of the second resistor R2, the negative terminal of the first dc transducer U5739, AND one end of the fourth capacitor C4 are connected, the other end of the fourth capacitor C4, the other end of the first NMOS tube M1, AND the negative input terminal of the first comparator CMP drain 1 are connected, the other end of the third resistor R3, one end of the fourth resistor R4, AND the other end of the fourth resistor CMP1, AND the first AND the second AND the source of the first AND the second AND gate AND, An output end of the first comparator CMP1 is connected with one input end of the first AND gate AND1, a gate of the first NMOS transistor M1, an input end of the first inverter INV1 AND an output end of the sampling pulse generator 1 are connected, an output end of the first inverter INV1 is connected with the other input end of the first AND gate AND1, AND an output end of the first AND gate AND1 is connected with a first input end of the logic controller 5; the second maximum power point tracker 3 comprises a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a fifth capacitor C5, a second comparator CMP2, a second NMOS transistor M2, a second inverter INV2 AND a second AND gate AND2, the positive terminal of the second dc converter U2, one end of the fifth resistor R5 AND one end of the seventh resistor R7 are connected, the other end of the fifth resistor R5, one end of the sixth resistor R6 AND the source of the second NMOS transistor M2 are connected, the other end of the sixth resistor R6, the negative terminal of the second dc converter U2 AND one end of the fifth capacitor C5 are connected, the other end of the fifth capacitor C5, the drain of the second NMOS transistor M5 AND the negative input terminal of the second comparator 5 are connected, the other end of the seventh resistor R5, one end of the eighth resistor R5 AND one positive input terminal of the second comparator CMP AND gate AND the second comparator R5 are connected, the gate of the second NMOS transistor M2, the input end of the second inverter INV2, AND the output end of the sampling pulse generator 1 are connected, the output end of the second inverter INV2 is connected to the other input end of the second AND gate AND2, AND the output end of the second AND gate AND2 is connected to the second input end of the logic controller 5; the third maximum power point tracker 4 comprises a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a sixth capacitor C6, a third comparator CMP3, a third NMOS transistor M3, a third inverter INV3 AND a third AND gate AND3, the positive terminal of the third dc converter U3, one end of the ninth resistor R9 AND one end of the eleventh resistor R11 are connected, the other end of the ninth resistor R9, one end of the tenth resistor R10 AND the source of the third NMOS transistor M3 are connected, the other end of the tenth resistor R10, the negative terminal of the third dc converter U3 AND one end of the sixth capacitor C6 are connected, the other end of the sixth capacitor C6, the drain of the third NMOS transistor M6 AND the negative input terminal of the third comparator 6 are connected, the other end of the eleventh resistor R6, one end of the twelfth resistor R6 AND one end of the third comparator CMP AND gate R6 are connected, the twelfth input terminal of the third AND gate AND R6 AND the twelfth comparator 6 are connected, the gate of the third NMOS transistor M3, the input end of the third inverter INV3, AND the output end of the sampling pulse generator 1 are connected, the output end of the third inverter INV3 is connected to the other input end of the third AND gate AND3, AND the output end of the third AND gate AND3 is connected to the third input end of the logic controller 5.
In this embodiment, the sampling pulse generator 1 includes a clock chip with a type LTC6995, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, and a seventh capacitor C7, wherein a first pin of the clock chip, one end of the thirteenth resistor R13, and one end of the seventh capacitor C7 are connected, the other end of the thirteenth resistor R13, a sixth pin of the clock chip, a clock input end of the first maximum power point tracker 2, a clock input end of the second maximum power point tracker 3, and a clock input end of the third maximum power point tracker 4 are connected, a third pin of the clock chip is connected to one end of the fourteenth resistor R14, a fifth pin of the clock chip, one end of the fifteenth resistor R15, and a power voltage, the other end of the fifteenth resistor R15, a fourth pin of the clock chip, and one end of the sixteenth resistor R16 are connected, a second pin of the clock chip, and a fourth pin of the clock chip are connected to the clock chip, The other end of the seventh capacitor C7, the other end of the fourteenth resistor R14 and the other end of the sixteenth resistor R16 are all grounded.
In this embodiment, the logic controller 5 comprises a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a fourth AND gate AND4, an output terminal of the first maximum power point tracker 2, a control terminal of the first controllable switch S1, an input end of a fourth inverter INV4 AND one input end of a fourth AND gate AND4 are connected, an output end of the fourth inverter INV4 is connected with a control end of the second controllable switch S2, an output end of the second maximum power point tracker 3, an input end of the fifth inverter INV5 AND a control end of the fourth controllable switch S4 are connected, an output end of the fifth inverter INV5 is connected with the other input end of the fourth AND gate 4, an output end of the fourth AND gate 4 is connected with a control end of the third controllable switch S3, an output end of the third maximum power point tracker 4, a control end of the fifth controllable switch S5 AND an input end of the sixth inverter INV6 are connected, AND an output end of the sixth inverter INV6 is connected with a control end of the sixth controllable switch S6.
The brief working process of the synchronously extractable multi-input environmental energy collecting circuit disclosed by the above embodiment is as follows:
the inductive charging phase is divided into three cases:
A. when the first maximum power point tracker 2 detects that the first direct current transducer U1 reaches the maximum power point, and the second maximum power point tracker 3 detects that the second direct current transducer U2 reaches the maximum power point, the logic controller 5 controls the first controllable switch S1 and the fourth controllable switch S4 to be firstly switched on, the second controllable switch S2 and the third controllable switch S3 are switched off, and the first direct current transducer U1 and the second direct current transducer U2 jointly charge the inductor L;
B. when the first maximum power point tracker 2 detects that the first direct current transducer U1 reaches the maximum power point and the second maximum power point tracker 3 detects that the second direct current transducer U2 does not reach the maximum power point, the logic controller 5 controls the first controllable switch S1 and the third controllable switch S3 to be firstly switched on, the second controllable switch S2 and the fourth controllable switch S4 to be switched off, and the first direct current transducer U1 charges the inductor L;
C. when the first maximum power point tracker 2 detects that the first dc transducer U1 does not reach the maximum power point, and the second maximum power point tracker 3 detects that the second dc transducer U2 reaches the maximum power point, the logic controller 5 controls the second controllable switch S2 and the fourth controllable switch S4 to be turned on first, the first controllable switch S1 and the third controllable switch S3 are turned off, and the second dc transducer U2 charges the inductor L.
The inductive freewheeling stage is divided into two cases: when the three possible inductive charging processes described above are completed, i.e. the first maximum power point tracker 2 detects that the first dc transducer U1 has left the maximum power point, and the second maximum power point tracker 3 detects that the second dc transducer U2 has left the maximum power point, the logic controller 5 controls the second controllable switchS2 is conducted, the first controllable switch S1, the third controllable switch S3 and the fourth controllable switch S4 are all disconnected, if the third maximum power point tracker 4 detects that the third direct current transducer U3 reaches the maximum power point at the moment, the logic controller 5 controls the fifth controllable switch S5 to be conducted, the sixth controllable switch S6 is disconnected, and the inductor L and the third direct current transducer U3 jointly transfer energy to the output capacitor CSTO(ii) a If the third maximum power point tracker 4 detects that the third dc converter U3 does not reach the maximum power point, the logic controller 5 controls the sixth controllable switch S6 to be turned on, the fifth controllable switch S5 to be turned off, and the inductor L transfers energy to the output capacitor CSTO。
Claims (4)
1. A multi-input environmental energy collection circuit capable of synchronously extracting is characterized by comprising a first direct current transducer, a second direct current transducer, a third direct current transducer, a first capacitor, a second capacitor, a third capacitor, an output capacitor, an inductor, a freewheeling diode, a first controllable switch, a second controllable switch, a third controllable switch, a fourth controllable switch, a fifth controllable switch, a sixth controllable switch, a sampling pulse generator, a first maximum power point tracker, a second maximum power point tracker, a third maximum power point tracker and a logic controller, wherein the positive end of the first direct current transducer, one end of the first controllable switch, one end of the first capacitor and the positive input end of the first maximum power point tracker are connected, the other end of the first controllable switch, one end of the second controllable switch and one end of the inductor are connected, the other end of the inductor, one end of the third controllable switch, one end of the fourth controllable switch, one end of the fifth controllable switch and one end of the sixth controllable switch are connected, the other end of the fourth controllable switch, the negative terminal of the second dc transducer, one end of the second capacitor and the negative input end of the second maximum power point tracker are connected, the other end of the fifth controllable switch, the negative terminal of the third dc transducer, one end of the third capacitor and the negative input end of the third maximum power point tracker are connected, the other end of the sixth controllable switch, the positive terminal of the third dc transducer, the other end of the third capacitor, the positive input end of the third maximum power point tracker and the positive electrode of the freewheeling diode are connected, the negative electrode of the freewheeling diode is connected to one end of the output capacitor, the negative terminal of the first dc transducer, the positive terminal of the second dc transducer, the negative input terminal of the first maximum power point tracker, the positive input terminal of the second maximum power point tracker, the other end of the first capacitor, the other end of the second controllable switch, the other end of the third controllable switch, the other end of the second capacitor, and the other end of the output capacitor are all grounded, the output terminal of the sampling pulse generator, the clock input terminal of the first maximum power point tracker, the clock input terminal of the second maximum power point tracker, and the clock input terminal of the third maximum power point tracker are connected, the output terminal of the first maximum power point tracker is connected to the first input terminal of the logic controller, the output end of the second maximum power point tracker is connected with the second input end of the logic controller, the output end of the third maximum power point tracker is connected with the third input end of the logic controller, a first output terminal of the logic controller is connected with a control terminal of the first controllable switch, a second output terminal of the logic controller is connected with a control terminal of the second controllable switch, a third output terminal of the logic controller is connected with a control terminal of the third controllable switch, a fourth output terminal of the logic controller is connected with a control terminal of the fourth controllable switch, a fifth output terminal of the logic controller is connected with a control terminal of the fifth controllable switch, a sixth output end of the logic controller is connected with a control end of the sixth controllable switch, and a logic expression of the logic controller is as follows:
S1＝SIG1
S4＝SIG2
S5＝SIG3
wherein S1 represents a signal output from the first output terminal of the logic controller, S2 represents a signal output from the second output terminal of the logic controller, S3 represents a signal output from the third output terminal of the logic controller, S4 represents a signal output from the fourth output terminal of the logic controller, S5 represents a signal output from the fifth output terminal of the logic controller, S6 represents a signal output from the sixth output terminal of the logic controller, SIG1 represents a signal input from the first input terminal of the logic controller, SIG2 represents a signal input from the second input terminal of the logic controller, and SIG3 represents a signal input from the third input terminal of the logic controller.
2. The circuit of claim 1, wherein the first maximum power point tracker comprises a first resistor, a second resistor, a third resistor, a fourth capacitor, a first comparator, a first NMOS transistor, a first inverter, and a first AND gate, wherein the positive terminal of the first DC converter, one terminal of the first resistor, and one terminal of the third resistor are connected, the other terminal of the first resistor, one terminal of the second resistor, and the source of the first NMOS transistor are connected, the other terminal of the second resistor, the negative terminal of the first DC converter, and one terminal of the fourth capacitor are connected, the other terminal of the fourth capacitor, the drain of the first NMOS transistor, and the negative input terminal of the first comparator are connected, and the other terminal of the third resistor, the drain of the third NMOS transistor, and the negative input terminal of the first NMOS transistor are connected, One end of the fourth resistor is connected with the positive input end of the first comparator, the other end of the fourth resistor, the output end of the first comparator and one input end of the first AND gate are connected, the grid electrode of the first NMOS tube, the input end of the first phase inverter and the output end of the sampling pulse generator are connected, the output end of the first phase inverter is connected with the other input end of the first AND gate, and the output end of the first AND gate is connected with the first input end of the logic controller;
the second maximum power point tracker comprises a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a fifth capacitor, a second comparator, a second NMOS transistor, a second inverter and a second AND gate, wherein the positive end of the second direct current transducer, one end of the fifth resistor and one end of the seventh resistor are connected, the other end of the fifth resistor, one end of the sixth resistor and the source electrode of the second NMOS transistor are connected, the other end of the sixth resistor, the negative end of the second direct current transducer and one end of the fifth capacitor are connected, the other end of the fifth capacitor, the drain electrode of the second NMOS transistor and the negative input end of the second comparator are connected, the other end of the seventh resistor, one end of the eighth resistor and the positive input end of the second comparator are connected, and the other end of the eighth resistor, the other end of the sixth resistor, one end of the fifth capacitor and one end of the second NMOS transistor are connected, The output end of the second comparator is connected with one input end of the second AND gate, the grid electrode of the second NMOS tube, the input end of the second phase inverter and the output end of the sampling pulse generator are connected, the output end of the second phase inverter is connected with the other input end of the second AND gate, and the output end of the second AND gate is connected with the second input end of the logic controller;
the third maximum power point tracker comprises a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a sixth capacitor, a third comparator, a third NMOS transistor, a third inverter and a third AND gate, wherein the positive end of the third DC transducer, one end of the ninth resistor and one end of the eleventh resistor are connected, the other end of the ninth resistor, one end of the tenth resistor and the source electrode of the third NMOS transistor are connected, the other end of the tenth resistor, the negative end of the third DC transducer and one end of the sixth capacitor are connected, the other end of the sixth capacitor, the drain electrode of the third NMOS transistor and the negative input end of the third comparator are connected, the other end of the eleventh resistor, one end of the twelfth resistor and the positive input end of the third comparator are connected, the other end of the twelfth resistor, the output end of the third comparator and one input end of the third and gate are connected, the grid of the third NMOS tube, the input end of the third inverter and the output end of the sampling pulse generator are connected, the output end of the third inverter is connected with the other input end of the third and gate, and the output end of the third and gate is connected with the third input end of the logic controller.
3. The circuit of claim 1, wherein the sampling pulse generator comprises a clock chip of type LTC6995, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor and a seventh capacitor, wherein a first pin of the clock chip, a terminal of the thirteenth resistor and a terminal of the seventh capacitor are connected, another terminal of the thirteenth resistor, a sixth pin of the clock chip, a clock input terminal of the first maximum power point tracker, a clock input terminal of the second maximum power point tracker and a clock input terminal of the third maximum power point tracker are connected, a third pin of the clock chip is connected with a terminal of the fourteenth resistor, a fifth pin of the clock chip, a terminal of the fifteenth resistor and a power supply voltage are connected, the other end of the fifteenth resistor, the fourth pin of the clock chip and one end of the sixteenth resistor are connected, and the second pin of the clock chip, the other end of the seventh capacitor, the other end of the fourteenth resistor and the other end of the sixteenth resistor are all grounded.
4. The circuit of claim 1, wherein the logic controller comprises a fourth inverter, a fifth inverter, a sixth inverter, and a fourth AND gate, wherein the output terminal of the first MPPT, the control terminal of the first controllable switch, the input terminal of the fourth inverter, and an input terminal of the fourth AND gate are connected, the output terminal of the fourth inverter is connected to the control terminal of the second controllable switch, the output terminal of the second MPPT, the input terminal of the fifth inverter, and the control terminal of the fourth controllable switch are connected, the output terminal of the fifth inverter is connected to another input terminal of the fourth AND gate, and the output terminal of the fourth AND gate is connected to the control terminal of the third controllable switch, the output end of the third maximum power point tracker, the control end of the fifth controllable switch and the input end of the sixth inverter are connected, and the output end of the sixth inverter is connected with the control end of the sixth controllable switch.
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