CN112366938B

CN112366938B - Multi-source energy collection system and control method thereof

Info

Publication number: CN112366938B
Application number: CN202011208052.XA
Authority: CN
Inventors: 张长春; 张桄华; 赵文斌
Original assignee: Nanjing University of Posts and Telecommunications
Current assignee: Nanjing University of Posts and Telecommunications
Priority date: 2020-11-03
Filing date: 2020-11-03
Publication date: 2021-08-13
Anticipated expiration: 2040-11-03
Also published as: CN112366938A

Abstract

The invention discloses a multi-source energy collection system and a control method thereof, wherein the energy collection system comprises piezoelectric, photoelectric, thermoelectric, radio frequency and other energy collectors, a processing buffer circuit, a reconfigurable charge pump, a charge pump voltage conversion rate control circuit, a digital control oscillator, a charge pump maximum power tracking circuit, an MPPT mode control circuit, an arbitration circuit, a sampling and holding comparator, a fixed conduction time comparator and a self-starting circuit. The reconfigurable charge pump improves the conversion efficiency and enlarges the input voltage range by adjusting the voltage conversion rate and the switch working frequency. The self-adaptive control circuit controls the output voltage of the system by adopting a fixed conduction time method, and the generated peak voltage is multiplexed to control the working state of the charge pump, so that the complexity of the circuit is reduced, and the power consumption of the system is reduced.

Description

Multi-source energy collection system and control method thereof

Technical Field

The invention belongs to the technical field of micro-energy collection, and particularly relates to a multi-source energy collection system and a control method thereof.

Background

The continuous development of low-power integrated circuit technology enables wireless sensors, wearable devices and the like to be widely applied. At present, wireless sensors and wearable equipment are mainly powered by batteries, and the batteries are short in endurance time, limited in service life, complex in maintenance and replacement, high in cost and the like. The energy collection technology is considered as a battery replacement technology with the most potential in the field by industry public, and becomes a hot spot of domestic and foreign research in recent years.

The single-source energy collection technology has been widely researched, but the single-source energy collection technology generally has the defects of single energy acquisition, limited application scene, low reliability and the like, and the multi-source energy collection technology can well overcome the defects by comprehensively collecting various environmental energies. Compared with a single-source energy collection design technology, the multi-source energy collection design technology is far from mature. The problems that the number of energy which can be collected simultaneously is small, large inductance outside a chip is required to be used, self-starting cannot be achieved, the wide input power range and the wide input voltage range cannot be adapted, and maximum power point tracking of each type of energy lack of response exists at present.

Disclosure of Invention

In order to solve the problem of the defects of the existing energy collection system chip design proposed by the background art, the invention provides a multi-source energy collection system and a control method thereof, so as to adapt to a wider input voltage range and a wider input power range.

In order to achieve the technical purpose, the technical scheme of the invention is as follows:

a multi-source energy collecting system comprises a piezoelectric energy collector, a photoelectric energy collector, a thermoelectric energy collector, a radio frequency antenna energy collector, a piezoelectric processing and buffering circuit, a photoelectric processing and buffering circuit, a thermoelectric processing and buffering circuit, a radio frequency processing and buffering circuit, a reconfigurable charge pump, a charge pump voltage Conversion Rate (CR) control circuit, a digital control oscillator, a reconfigurable charge pump Maximum Power Point Tracking (MPPT) control circuit, an MPPT mode control circuit, an arbitration circuit, a sample-hold comparator, a fixed conduction time comparator and a self-starting circuit;

the photoelectric processing and buffering circuit comprises a photoelectric interface circuit and a first switch S₁And a photoelectric buffer capacitor C_PVOutput V of the opto-electronic interface circuit_PVConnecting photoelectric buffer capacitor C_PVUpper plate of and first switch S₁One terminal of (1), a photoelectric buffer capacitor C_PVThe lower polar plate is connected with the ground wire, the first switch S₁The other end of the reconfigurable charge pump is connected with an IN voltage input end of the reconfigurable charge pump;

the thermoelectric processing and buffering circuit comprises a thermoelectric interface circuit and a second switch S₂Thermoelectric buffer capacitor C_TEGOutput V of the thermoelectric interface circuit_TEGConnecting thermoelectric buffer capacitor C_TEGAnd the second switch S₂One terminal of (1), a thermoelectric buffer capacitor C_TEGThe lower polar plate is connected with the ground wire, and a second switch S₂The other end of the reconfigurable charge pump is connected with an IN voltage input end of the reconfigurable charge pump;

the radio frequency energy processing and buffering circuit comprises a radio frequency interface circuit and a third switch S₃Radio frequency buffer capacitor C_RFOutput V of the RF interface circuit_RFConnecting radio frequency buffer capacitor C_RFUpper plate and third switch S₃One terminal of (1), a radio frequency buffer capacitor C_RFThe lower polar plate is connected with the ground wire, and a third switch S₃The other end of the reconfigurable charge pump is connected with an IN voltage input end of the reconfigurable charge pump;

the piezoelectric processing and buffering circuit comprises a piezoelectric interface circuit and a piezoelectric buffering capacitor C_PZThe output VDD of the piezoelectric interface circuit is connected with a piezoelectric buffer capacitor C_PZUpper electrode plate of, piezoelectric buffer capacitor C_PZThe lower polar plate is connected with a ground wire;

the self-starting circuit comprises an under-voltage locking circuit and a first inverter INV₁And a fourth switch S₄A first comparator COMP₁The VDD input end of the undervoltage locking circuit is connected with the output VDD of the piezoelectric interface circuit, and the UVLO output end of the undervoltage locking circuit is connected with the first inverter INV₁The first inverter INV₁The output end of the first switch is connected with the RESET input end of the photoelectric interface circuit, the RESET input end of the thermoelectric interface circuit, the RESET input end of the arbitration circuit, the RESET input end of the reconfigurable charge pump MPPT control circuit and the fourth switch S₄One end of the fourth switch is connected with the output VDD of the piezoelectric interface circuit₄The other end is connected with an OUT output end of the reconfigurable charge pump, and a first comparator COMP₁The positive phase input end of the first comparator COMP is connected with the output VDD of the piezoelectric interface circuit₁Negative phase input terminal of the first reference voltage V_REF1First comparator COMP₁Is connected with a fourth switch S₄The control terminal of (1); output signal REQ of an opto-electrical interface circuit_PVOutput signal REQ of thermoelectric interface circuit_TEGOutput signal REQ of radio frequency interface circuit_RFRespectively connected to the input end of the arbitration circuit and the output signal EON of the arbitration circuit_PVEON accessing MPPT mode control circuit_PVEON of signal input end and reconfigurable charge pump MPPT control circuit_PVSignal input terminal and first switch S₁Control terminal of (2), output signal EON of arbitration circuit_TEGEON accessing MPPT mode control circuit_TEGEON of signal input end and reconfigurable charge pump MPPT control circuit_TEGSignal input terminal and second switch S₂Control terminal of (2), output signal EON of arbitration circuit_RFEON accessing MPPT mode control circuit_RFEON of signal input end and reconfigurable charge pump MPPT control circuit_RFSignal input terminal and third switch S₃Control terminal ofFirst AND gate AND₁And EN of a sample-and-hold comparator_AROutput signal EN with input end connected to arbitration circuit_AR(ii) a An output signal CRT of the MPPT mode control circuit is accessed to a CRT input end of the reconfigurable charge pump MPPT control circuit and a CRT input end of a sample-hold comparator, and an output signal FCT of the MPPT mode control circuit is accessed to an FCT input end of the reconfigurable charge pump MPPT control circuit and an FCT input end of the sample-hold comparator; first reference clock CLK_COTA second reference voltage V_REF2And an OUT terminal output signal V of the reconfigurable charge pump_OUTRespectively connected to the input end of the fixed time conduction comparator, and the output signal EN of the fixed time conduction comparator_COTConnected to a first AND gate AND₁Another input terminal of the comparator, the output signal PULSE of the fixed-time conduction comparator_SHPULSE with access to sample-and-hold comparator_SHAn input end; OUT terminal output signal V of reconfigurable charge pump_OUTThe output signal PULSE of the sample-and-hold comparator is connected to the input end of the sample-and-hold comparator_MPPTPULSE connected to reconfigurable charge pump MPPT control circuit_MPPTThe output signal UD of the sample-hold comparator is connected to the UD input end of the reconfigurable charge pump MPPT control circuit; output signal MODE of reconfigurable charge pump MPPT control circuit_CHANGEMODE accessed to MPPT MODE control circuit_CHANGEInput terminal, output signal CR of reconfigurable charge pump MPPT control circuit_D3、CR_D2、CR_D1、CR_D0Respectively connected to the input end of the CR control circuit of the charge pump to reconstruct the output signal FC of the MPPT control circuit of the charge pump_D3、FC_D2、FC_D1、FC_D0Respectively accessing to the input ends of the numerically controlled oscillators; seven output signals SM 1-SM 7 of the charge pump CR control circuit are connected to the CR input end of the reconfigurable charge pump; output signal CLK of a digitally controlled oscillator_CPSwitching in a CLK input end of the reconfigurable charge pump; first AND gate AND₁Output signal EN of_CPThe EN input end of the reconfigurable charge pump is accessed; the output end OUT of the reconfigurable charge pump passes through a capacitor C_OUTAnd a ground line.

Further, the reconfigurable charge pump comprises a first stage charge pump, a second stage charge pump, a third stage charge pump and a fourth stage charge pump;

the first stage charge pump comprises fifth to tenth switches S₅～S₁₀A first capacitor C₁And a second capacitor C₂AND gates AND₂～AND₅A first non-overlapping signal generating circuit NO1 and a second non-overlapping signal generating circuit NO 2;

the first stage charge pump input voltage V_INSwitched in to the fifth switch S₅And a sixth switch S₆And a ninth switch S₉And a tenth switch S₁₀One end of (1), a fifth switch S₅The other end of the first capacitor C is connected to₁Upper pole plate of (1), sixth switch S₆The other end of the first capacitor is connected to a second capacitor C₂Upper pole plate of (1), ninth switch S₉The other end of the first capacitor C is connected to₁Lower pole plate and seventh switch S₇One end of (1), a tenth switch S₁₀Is connected with a second capacitor C₂Lower pole plate and eighth switch S₈One end of (1), a seventh switch S₇The other end of the first switch S is connected with the ground wire, and an eighth switch S₈The other end of the first AND gate AND line, a second AND gate AND line₂AND fifth AND gate AND₅Has an input terminal connected with input signals S1N AND SM1, a second AND gate AND₂Is connected with the fifth switch S₅Control terminal of, fifth AND gate AND₅Is connected to the input of the second non-overlapping signal generating circuit NO2, a third AND gate AND₃AND fourth AND gate AND₄Is connected to the input signals S1P AND SM1, a third AND gate AND₃Is connected with a sixth switch S₆Control terminal of, fourth AND gate AND₄Is connected to an input terminal of a first non-overlapping signal generating circuit NO1, an output terminal of an N terminal of the first non-overlapping signal generating circuit NO1 is connected to a seventh switch S₇The P terminal output of the first non-overlapping signal generating circuit NO1 is connected to the ninth switch S₉The output of the N terminal of the second non-overlapping signal generating circuit NO2 is connected to the eighth switch S₈A P terminal of the second non-overlapping signal generating circuit NO2 is connected to a tenth switch S₁₀；

The second stage charge pump comprises eleventh to eighteenth switches S₁₁～S₁₈A third capacitor C₃And a fourth capacitance C₄AND AND gates of the sixth to ninth₆～AND₉A third non-overlapping signal generating circuit NO3 and a fourth non-overlapping signal generating circuit NO4, a first demultiplexer DEMUX1 and a second demultiplexer DEMUX 2;

the eleventh switch S₁₁And an eighteenth switch S₁₈Is connected to the output V1L of the first stage charge pump, a twelfth switch S₁₂And a seventeenth switch S₁₇Is connected to the output V1R of the first stage charge pump, a fifteenth switch S₁₅And a sixteenth switch S₁₆Is connected to the input voltage V of the reconfigurable charge pump_INThe eleventh switch S₁₁Is connected at the other end to a third capacitance C₃Upper pole plate of (1), twelfth switch S₁₂Is connected to a fourth capacitance C at the other end₄Upper pole plate of (1), seventeenth switch S₁₇The other end of (1), a fifteenth switch S₁₅And the other end of the thirteenth switch S₁₃Is connected to a third capacitor C₃Lower pole plate of (1), eighteenth switch S₁₈The other end of (1), a sixteenth switch S₁₆And a fourteenth switch S₁₄Is connected to a fourth capacitor C₄Lower plate of, a thirteenth switch S₁₃And a fourteenth switch S₁₄Is connected to ground, a seventh AND gate AND₇AND eighth AND gate AND₈Is connected with the input signals SM2 AND S2N, a seventh AND gate AND₇Is connected with a twelfth switch S₁₂Control terminal of, eighth AND gate AND₈Is connected to the input of the third non-overlapping signal generating circuit NO3, a sixth AND gate AND₆AND the ninth AND gate AND₉Is connected to the input signals SM2 AND S2P, a sixth AND gate AND₆Is connected with an eleventh switch S₁₁The ninth AND gate AND₉Is connected to an input of a fourth non-overlapping signal generating circuit NO4, a third non-overlapping signal generating circuitThe N-terminal output of NO3 is connected to the thirteenth switch S₁₃A P terminal output of the third non-overlapping signal generating circuit NO3 is connected to an input terminal of the first demultiplexer DEMUX1, and an N terminal output of the fourth non-overlapping signal generating circuit NO4 is connected to the fourteenth switch S₁₄A P terminal output of the fourth non-overlapping signal generating circuit NO4 is connected to an input terminal of the second demultiplexer DEMUX2, an a terminal output of the first demultiplexer DEMUX1 is connected to the fifteenth switch S₁₅A B terminal output of the first demultiplexer DEMUX1 is connected to a seventeenth switch S₁₇A terminal a of the second demultiplexer DEMUX2 is connected to a sixteenth switch S₁₆A B terminal output of the second demultiplexer DEMUX2 is connected to an eighteenth switch S₁₈The input signal SM3 is connected to the select terminal of the first demultiplexer DEMUX1 and the select terminal of the second demultiplexer DEMUX 2;

the third stage charge pump comprises thirty-first to forty-first switches S₃₁～S₄₁Seventh to tenth capacitors C₇～C₁₀The tenth AND gate AND₁₀AND the eleventh AND gate AND₁₁A second inverter INV₂And a third inverter INV₃First OR gate OR₁NOR of first NOR gate₁A first NAND gate NAND₁And a seventh non-overlapping signal generating circuit NO 7;

the thirty-first switch S₃₁One end of the voltage-measuring circuit is connected with the input voltage V of the charge pump_INThe thirty-first switch S₃₁Is connected to a seventh capacitor C at the other end₇Upper pole plate, thirty-two switch S₃₂And a thirty-fifth switch S₃₅One end of (1), a thirty-two switch S₃₂Is connected with an eighth capacitor C₈Upper pole plate and thirty-third switch S₃₃And a thirty-sixth switch S₃₆One end of (1), a thirty-third switch S₃₃Is connected to a ninth capacitor C at the other end₉Upper polar plate, thirty-fourth switch S₃₄And a thirty-seventh switch S₃₇One end of (1), a thirty-fourth switch S₃₄Is connected to a tenth capacitor C at the other end₁₀Upper plate of and a thirty-fifth switch S₃₅The other end of (1), a sixteenth switch S₃₆Is connected to a seventh capacitor C at the other end₇Lower pole plate and thirty-eighth switch S₃₈And a fortieth switch S₄₀One end of (1), a third seventeen switch S₃₇Is connected to an eighth capacitor C at the other end₈And a thirty-ninth switch S₃₉At one end of (1), the fortieth switch S₄₀Is connected to a forty-first switch S at the other end₄₁One end of (1), a third eighteen switch S₃₈Is connected to ground, a thirty-ninth switch S₃₉Is connected to ground, a forty-first switch S₄₁Is connected to ground, a tenth AND gate AND₁₀The input of the first AND second AND-gate AND is connected with the input signal S3N/S3P AND the input signal SM6₁₀Is connected to an input terminal of a seventh non-overlapping signal generating circuit NO7, an N-terminal output of the seventh non-overlapping signal generating circuit NO7 is connected to the second inverter INV₂Input terminal of, eleventh AND gate AND₁₁An input terminal of, a twenty-ninth switch S₂₉And a thirty-fifth switch S₃₅And a P terminal output of the seventh non-overlapping signal generating circuit NO7 is connected to the third inverter INV₃Input terminal of (1), first OR gate OR₁An input terminal of, a twenty-seventh switch S₂₇And a thirty-third switch S₃₃The second inverter INV₂Is connected to the first NOR gate NOR₁An input terminal of the third inverter INV₃Is connected to the first NAND gate NAND₁An eleventh AND gate AND₁₁First NOR gate NOR₁Another input terminal of the first NAND gate NAND₁And a first OR gate OR₁Is connected to the input signal SM7, an eleventh AND gate AND₁₁Is connected to the thirty-first switch S₃₁Control terminal and the thirty-sixth switch S₃₆First NOR gate NOR₁Is connected to the twenty-eight switch S₂₈And a control terminal of the thirty-fourth, first NAND gate NAND₁Is connected to a thirtieth switch S₃₀And a seventeenth switch S₃₇A first OR gate OR₁Is connected to the thirty-second switch S₃₂The control terminal of (1);

the fourth stage charge pump comprises nineteenth to thirtieth switches S₁₉～S₃₀And a forty-second switch S₄₂And a forty-third switch S₄₃A fifth capacitor C₅A sixth capacitor C₆A fifth non-overlapping signal generating circuit NO5 and a sixth non-overlapping signal generating circuit NO6, a third demultiplexer DEMUX3 and a fourth demultiplexer DEMUX 4;

the nineteenth switch S₁₉One end of (1), a twentieth switch S₂₃And a twenty-sixth switch S₂₆Is connected to the output V2L of the second stage charge pump, a twentieth switch S₂₀One end of and the twenty-fourth switch S₂₄And a twenty-fifth switch S₂₅Is connected to the output V2R of the second stage charge pump, a twenty-seventh switch S₂₇And a twenty-eighth switch S₂₈Is connected to the input voltage V of the reconfigurable charge pump_INTwenty ninth switch S₂₉Is connected to the output V3L of the third stage charge pump, a thirtieth switch S₃₀Is connected to the output V3R of the third stage charge pump, a nineteenth switch S₁₉Is connected to a fifth capacitance C at the other end₅Upper plate of and a forty-second switch S₄₂One end of (1), the twentieth switch S₂₀Is connected to a sixth capacitor C at the other end₆Upper plate and a forty-third switch S₄₃One end of (1), the twentieth switch S₂₃Is connected to a fifth capacitance C at the other end₅Lower polar plate and twenty-fifth switch S₂₅The other end of the first switch S and a twenty-seventh switch S₂₇The other end of the first switch S and a twenty-ninth switch S₂₉And the other end of (1) and the twenty-first switch S₂₁One end of (1), a twenty-four switch S₂₄Is connected to a sixth capacitor C at the other end₅Lower polar plate and twenty-sixth switch S₂₆The other end of (1), the twenty-eighth switch S₂₈Another end of (1), thirtieth switch S₃₀And the other end of the second switch S₂₂One end of (1), the twenty-first switch S₂₁The other end of the first switch is connected with a ground wire, and a twenty-second switch S₂₂Is connected to ground, a forty-second switch S₄₂And the other end of the forty-third switch S₄₃Is connected at the other end to V of the charge pump_OUTAn output terminal, an input terminal of the fifth non-overlapping signal generating circuit NO5 is connected to the input signal S4P, and an N terminal output of the fifth non-overlapping signal generating circuit NO5 is connected to the twenty-first switch S₂₁A P terminal output of the fifth non-overlapping signal generating circuit NO5 is connected to an input terminal of the third demultiplexer DEMUX3, an input terminal of the sixth non-overlapping signal generating circuit NO6 is connected to the input signal S4N, and an N terminal output of the sixth non-overlapping signal generating circuit NO6 is connected to the twenty-second switch S₂₂P terminal of the sixth non-overlapping signal generating circuit NO6 is connected to an input terminal of a fourth demultiplexer DEMUX4, selection terminals of the third DEMUX3 and the fourth demultiplexer DEMUX4 are connected to an input signal SM4 and an input signal SM5, and an a terminal of the third demultiplexer DEMUX3 is connected to a twenty-third switch S₂₃A B terminal of the third demultiplexer DEMUX3 is connected to a twenty-fifth switch S₂₅C-terminal output of the third demultiplexer DEMUX3 is connected to the twenty-seventh switch S₂₇A D terminal of the third demultiplexer DEMUX3 is connected to a twenty-ninth switch S₂₉A terminal a of the fourth demultiplexer DEMUX4 is connected to the twenty-fourth switch S₂₄A B terminal of the fourth demultiplexer DEMUX4 is connected to a twenty-sixth switch S₂₆C terminal of the fourth demultiplexer DEMUX4 is connected to the twenty-eighth switch S₂₈A D terminal of the fourth demultiplexer DEMUX4 is connected to a thirtieth switch S₃₀The control terminal of (1).

Further, the fixed-time on comparator comprises a second OR gate OR₂Four bit counter, fourth inverseTool INV₄NAND gates of the second to fifth₂～NAND₅NOR, second NOR gate₃NOR, third NOR gate₃A latch comparator;

the second OR gate OR₂And the CLK input terminal of the latching comparator is connected to the input signal CLK_COTThe positive input end of the latch comparator is connected with an input signal V_OUTThe negative input end of the latch comparator is connected with the input signal V_REFSecond OR gate OR₂Is connected to the output signal of the latching comparator, a second OR gate₂Is connected to the CLK terminal of the quad counter, and the 0 bit output of the quad counter is connected to the fourth inverter INV₄And a third NAND gate NAND₃The 1-bit output of the four-bit counter is connected to the third NAND gate NAND₃And a fifth NAND gate NAND₅The 2-bit output of the four-bit counter is connected to the second NAND gate NAND₂And a fourth NAND gate NAND₄The 3-bit output of the four-bit counter is connected to the second NAND gate NAND₂And a fourth NAND gate NAND₄The other input terminal of (1), a fourth inverter INV₄Is connected to the fifth NAND-gate NAND₅Of a second NAND-gate NAND₂Is connected to the second NOR gate NOR₂Of a third NAND gate NAND₃Is connected to the second NOR gate NOR₂Of a fourth NAND-gate NAND₄Is connected to the output of the third NOR gate NOR₃Of a fifth NAND-gate NAND₅Is connected to the output of the third NOR gate NOR₃A second NOR gate NOR₂Is connected to the enable terminal of the latching comparator, a third NOR gate NOR₃Output signal PULSE_SH。

Further, the sample-and-hold comparator includes a fifth demultiplexer DEMUX₅And a forty-fourth switch S₄₄Forty-fifth switch S₄₅An eleventh capacitor C₁₁And a twelfth capacitor C₁₂A second comparator COMP₂And first to fourth D flip-flops DFF₁～DFF₄First to fifth DELAY units DELAY₁～DELAY₅AND AND gates of twelfth to fourteenth₁₂～AND₁₄XOR of the first XOR gate₁First XNOR gate₁NOR, fourth NOR gate₄The fifth inverter INV₅；

The fifth demultiplexer DEMUX₅Is connected with the input signal PULSE_SHFifth demultiplexer DEMUX₅Is connected to the forty-fifth switch S₄₅And the first exclusive or gate XOR₁An input terminal of the fifth demultiplexer DEMUX₅Is connected to the fourteenth switch S₄₄And the first exclusive or gate XOR₁Of a forty-fourth switch S₄₄Is connected to an input voltage V_OUTThe fourteenth switch S₄₄Is connected to an eleventh capacitor C at the other end₁₁And a second comparator COMP₂Negative phase input terminal of (1), the forty-fifth switch S₄₅Is connected to an input voltage V_OUTForty-fifth switch S₄₅Is connected to a twelfth capacitor C₁₂And a second comparator COMP₂A non-inverting input terminal of (1), a second comparator COMP₂Is connected to a first xor gate XNOR₁A first exclusive nor gate XNOR₁Is connected to the third D flip-flop DFF₃D input terminal of (1), first exclusive or gate XOR₁Is connected to the first DELAY unit DELAY₁The first DELAY unit DELAY₁Is connected to a second comparator COMP₂Enable terminal and second DELAY unit DELAY₂Input terminal of the second DELAY unit DELAY₂Is connected to the third DELAY unit DELAY₃Input terminal of, twelfth AND gate AND₁₂And a fifth inverter INV₅Input terminal of, the third DELAY unit DELAY₃Is connected to the fourth DELAY unit DELAY₄AND a thirteenth AND gate AND₁₃An input terminal of the fourth DELAY unit DELAY₄Is connected to the second D flip-flop DFF₂CLK terminal of, fifth inverter INV₅Is connected to the first D flip-flop DFF₁CLK input terminal of, the first D flip-flop DFF₁Is connected to a first D flip-flop DFF₁D input terminal, fifth demultiplexer DEMUX₅And a first exclusive nor gate XNOR₁Said second D flip-flop DFF₂D input terminal of the second D flip-flop DFF is connected with a power supply VDD₂Is connected to the twelfth AND gate AND₁₂AND a thirteenth AND gate AND₁₃AND a twelfth AND gate AND₁₂Is connected to the third D flip-flop DFF₃CLK input terminal of, thirteenth AND gate AND₁₃Output signal PULSE_MPPTSaid fourth NOR gate NOR₄The input end of the input end is connected with an input signal CRT and an input signal FCT; NOR of fourth NOR gate₄Is connected to the fourth D flip-flop DFF₄CLK input terminal of, a fourth D flip-flop DFF₄D input terminal of the D flip-flop is connected with a power supply VDD and a fourth D flip-flop DFF₄QB output terminal of the first AND gate is connected to the fourteenth AND gate AND₁₄And a fifth DELAY unit DELAY₅Of the fifth DELAY unit DELAY₅Is connected to the fourth D flip-flop DFF₄The fourteenth AND gate AND₁₄And a second D flip-flop DFF₂CLR of (1) terminates the input signal EN_ARFourteenth AND gate AND₁₄Is connected to the third D flip-flop DFF₃The CLR terminal of (1).

Furthermore, the digital control oscillator comprises a zeroth PMOS tube M to a second PMOS tube M₀～M₂And the third to fifth NMOS transistors M₃～M₅First to fifth oscillation units, sixth to eighth inverters INV₆～INV₈；

The oscillation unit comprises sixth to eleventh PMOS tubes M₆～M₁₁Twelfth to seventeenth NMOS transistors M₁₂～M₁₇And ninth to twelfth inverters INV₉～INV₁₂Thirteenth to sixteenth capacitors C₁₃～C₁₆；

The sixth PMOS tube M₆Is connected to a power supply VDD, and a sixth PMOS transistor M₆Is connected to a seventh PMOS transistor M₇Source electrode of (1), sixth PMOS transistor M₆Is connected to the thirteenth NMOS transistor M₁₃And the grid of the transistor is used as the input end of the oscillation unit, and the seventh PMOS tube M₇Is connected to the twelfth NMOS tube M₁₂Drain electrode of the transistor, eighth PMOS transistor M to eleventh PMOS transistor M₈～M₁₁Source electrode and fourteenth to seventeenth NMOS transistors M₁₄～M₁₇And the drain electrode of the transistor is used as the output end of the oscillation unit, and a seventh PMOS tube M₇Is connected to the zeroth PMOS transistor M₀The twelfth NMOS tube M₁₂Is connected to the thirteenth NMOS transistor M₁₃The twelfth NMOS tube M₁₂Is connected to the fourth NMOS transistor M₄Grid of (1), thirteenth NMOS tube M₁₃Is connected to ground, an eighth PMOS transistor M in the oscillation unit₈Gate of (2) and ninth inverter INV₉Is connected to an input signal FC_D3Ninth inverter INV₉Is connected to the fourteenth NMOS transistor M₁₄A ninth PMOS transistor M in the oscillation unit₉Gate of (1) and tenth inverter INV₁₀Is connected to an input signal FC_D2The tenth inverter INV₁₀Is connected to the fifteenth NMOS transistor M₁₅Grid of (1), tenth PMOS tube M in oscillation unit₁₀Gate of (1) and an eleventh inverter INV₁₁Is connected to an input signal FC_D1Eleventh inverter INV₁₁Is connected to the sixteenth NMOS transistor M₁₆Grid of (1), eleventh PMOS tube M in oscillation unit₁₁Gate of (1) and twelfth inverter INV₁₂Is connected to an input signal FC_D0Twelfth inverter INV₁₂Is connected to the seventeenth NMOS transistor M₁₇The eighth PMOS transistor M₈Drain electrode of (1) and fourteenth NMOS tube M₁₄Is connected to a thirteenth capacitor C₁₃Upper plate of, a thirteenth capacitor C₁₃The lower polar plate is connected to the ground wire, and a ninth PMOS tube M₉Drain electrode of (1) and a fifteenth NMOS tube M₁₅Is connected to a fourteenth capacitor C₁₄Upper plate of (2), fourteenth capacitance C₁₄The lower polar plate is connected to the ground wire, and a tenth PMOS tube M₁₀Drain electrode of (1) and sixteenth NMOS transistor M₁₆Is connected to a fifteenth capacitor C₁₅Upper plate of, a fifteenth capacitor C₁₅The lower polar plate is connected to the ground wire, and an eleventh PMOS tube M₁₁Drain electrode of (1) and seventeenth NMOS transistor M₁₇Is connected to a sixteenth capacitor C₁₆Upper plate of, sixteenth capacitor C₁₆The lower polar plate is connected to the ground wire, and a zeroth PMOS tube M₀Is connected to a power supply VDD, and a zeroth PMOS transistor M₀Is connected to the zeroth PMOS transistor M₀Grid and first PMOS transistor M₁Source electrode of (1), first PMOS transistor M₁Is connected to the first PMOS transistor M₁Grid electrode of and a third NMOS tube M₃Third NMOS transistor M₃Drain electrode of (1) and third NMOS transistor M₃Third NMOS transistor M₃The third NMOS transistor M₃Third NMOS transistor M₃Is connected to the fourth NMOS transistor M₄Drain electrode of (1) and fourth NMOS transistor M₄The fourth NMOS transistor M₄Is connected to a ground line, an output terminal of the first oscillating unit is connected to an input terminal of the second oscillating unit, an output terminal of the second oscillating unit is connected to an input terminal of the third oscillating unit, an output terminal of the third oscillating unit is connected to an input terminal of the fourth oscillating unit, an output terminal of the fourth oscillating unit is connected to an input terminal of the fifth oscillating unit, and an output terminal of the fifth oscillating unit is connected to a seventh inverter INV₇Input end of and a second PMOS tube M₂Source electrode of (1) and fifth NMOS transistor M₅Drain electrode of, seventh inverter INV₇Is connected to the eighth inverter INV₈The eighth inverter INV₈Output terminal of the second PMOS transistor M outputs a CLK signal₂Drain electrode of (1) and fifth NMOS transistor M₅Is connected to the input terminal of the first oscillating unitSecond PMOS transistor M₂Gate of (1) and sixth inverter INV₆Is connected with the input signal EN, a sixth inverter INV₆Is connected to the fifth NMOS transistor M₅A gate electrode of (1).

Further, the MPPT mode control circuit includes first to third counters, thirteenth to fifteenth inverters INV₁₃～INV₁₅And fifth to seventh D flip-flops DFF₅～DFF₇And sixth to eighth DELAY cells DELAY₆～DELAY₈Fifteenth AND gate AND₁₅Sixteenth AND gate AND₁₆A first three-input OR gate 3OR₁NOR of fifth NOR gate₅；

The input end of the first counter is connected with an input signal EON_PVThe output end of the first counter is connected to a first three-input OR gate 3OR₁An input terminal of the second counter is connected with the input signal EON_TEGThe output end of the second counter is connected to the first three-input OR gate 3OR₁The input of the third counter is connected with the input signal EON_RFThe output end of the third counter is connected to the first three-input OR gate 3OR₁A first three-input OR gate 3OR₁Is connected to the thirteenth inverter INV₁₃Input terminal of, a thirteenth inverter INV₁₃Is connected to the output of the fifth NOR gate NOR₅An input terminal of the fifth NOR gate NOR₅Is connected to the fifth D flip-flop DFF₅CLK input terminal of, a fifth D flip-flop DFF₅The D input end of the D flip-flop is connected with a power supply VDD and a fifth D flip-flop DFF₅Is connected to the sixth DELAY unit DELAY₆Input terminal of, the sixth DELAY unit DELAY₆Is connected to the fourteenth inverter INV₁₄An input terminal of (1); the fourteenth inverter INV₁₄Is connected to the sixth D flip-flop DFF₆CLK input terminal of (1), sixth D flip-flop DFF₆The D input end of the D flip-flop is connected with a power supply VDD and a sixth D flip-flop DFF₆Is connected to the fifth NOR gate NOR₅To the other input terminal, fifteenth inversePhoto device INV₁₅Is connected with the input signal MODE_CHANGEFifteenth inverter INV₁₅Is connected to a seventh D flip-flop DFF₇CLK input terminal of, a seventh D flip-flop DFF₇The D input end of the D flip-flop is connected with a power supply VDD and a seventh D flip-flop DFF₅QB output terminal of the first AND gate is connected to the fifteenth AND gate₁₅One input terminal of, the sixteenth AND gate AND₁₆And a seventh DELAY unit DELAY₇An input terminal of (1); seventh DELAY cell DELAY₇Is connected to the eighth DELAY unit DELAY₈The eighth DELAY unit DELAY₈Is connected to a seventh D flip-flop DFF₇CLR input terminal, fifteenth AND gate AND₁₅AND a sixteenth AND gate AND₁₆And the other input of which is connected to the input signal RESETN.

Further, the MPPT control circuit of the reconfigurable charge pump comprises seventeenth to twenty-fifth AND gates AND₁₇～AND₂₅Second to seventh 4-bit reversible counters₂～Counter₇First to eighth third input selector MUX₁～MUX₈；

The seventeenth AND gate AND₁₇One input terminal of, eighteenth AND gate AND₁₈AND a nineteenth AND gate AND₁₉One input end of the first AND gate is connected with the input signal CRT, the twentieth AND gate₂₀One input terminal of, the twenty-first AND gate AND₂₁AND a twenty-second AND gate AND₂₂One input terminal of (2) is connected with input signal PULSE_MPPTTwenty third AND gate AND₂₃One input terminal of, the twenty-fourth AND gate AND₂₄AND a twenty-fifth AND gate AND₂₅One input terminal of the first AND second switches is connected with the input signal FCT, AND a seventeenth AND gate₁₇Another input terminal of (1), a twentieth AND gate AND₂₀AND the twenty-third AND gate AND₂₃Is connected to the input signal EON_PVThe first to eighth third input selectors MUX₁～MUX₈S of₃Input terminal, eighteenth AND gate AND₁₈Another input ofEnd, twenty-first AND gate AND₂₁AND the twenty-fourth AND gate AND₂₄Is connected to the input signal EON_TEGThe first to eighth third input selectors MUX₁～MUX₈S of₂Input terminal, nineteenth AND gate AND₁₉AND a twenty-second AND gate AND₂₂Another input terminal of (1), twenty-fifth AND gate AND₂₅Is connected to the input signal EON_RFThe first to eighth third input selectors MUX₁～MUX₈S of₁Input terminal, seventeenth AND gate AND₁₇Is connected to a second 4-bit up-down Counter₂End EN of, eighteenth AND gate AND₁₈Is connected to a third 4-bit up-down Counter₃End EN of, nineteenth AND gate AND₁₉Is connected to a fourth 4-bit up-down Counter₄EN terminal, twentieth AND gate AND₂₀Is connected to a second 4-bit up-down Counter₂CLK terminal and fifth 4-bit up/down Counter₅The CLK terminal of, the twenty-first AND gate AND₂₁Is connected to a third 4-bit up-down Counter₃CLK terminal and a sixth 4-bit up/down Counter₆CLK terminal of, twenty-second AND gate AND₂₂Is connected to a fourth 4-bit up-down Counter₄CLK terminal and seventh 4-bit up/down Counter₇CLK terminal, twenty-third AND gate AND₂₃Is connected to a fifth 4-bit up-down Counter₅End EN of, twenty-fourth AND gate AND₂₄Is connected to a sixth 4-bit up-down Counter₆EN terminal of, twenty-fifth AND gate AND₂₅Is connected to a seventh 4-bit up-down Counter₇The second to seventh 4-bit reversible counters₂～Counter₇The UD input terminal receives the input signal UD, and a second 4-bit reversible Counter₂D of (A)₃The output terminal is connected to the first three-input selector MUX₁IN of₃Input terminal, second 4-bit reversible Counter₂D of (A)₂The output terminal is connected to the secondThree-input selector MUX₂IN of₃Input terminal, second 4-bit reversible Counter₂D of (A)₁The output terminal is connected to a third three-input selector MUX₃IN of₃Input terminal, second 4-bit reversible Counter₂D of (A)₀The output terminal is connected to a fourth three-input selector MUX₄IN of₃Input terminal, third 4-bit reversible Counter₃D of (A)₃The output terminal is connected to the first three-input selector MUX₁IN of₂Input terminal, third 4-bit reversible Counter₃D of (A)₂The output terminal is connected to a second three-input selector MUX₂IN of₂Input terminal, third 4-bit reversible Counter₃D of (A)₁The output terminal is connected to a third three-input selector MUX₃IN of₂Input terminal, third 4-bit reversible Counter₃D of (A)₀The output terminal is connected to a fourth three-input selector MUX₄IN of₂Input terminal, fourth 4-bit reversible Counter₄D of (A)₃The output terminal is connected to the first three-input selector MUX₁IN of₁Input terminal, fourth 4-bit reversible Counter₄D of (A)₂The output terminal is connected to a second three-input selector MUX₂IN of₁Input terminal, fourth 4-bit reversible Counter₄D of (A)₁The output terminal is connected to a third three-input selector MUX₃IN of₁Input terminal, fourth 4-bit reversible Counter₄D of (A)₀The output terminal is connected to a fourth three-input selector MUX₄IN of₁Input terminal, fifth 4-bit reversible Counter₅D of (A)₃The output terminal is connected to a fifth third input selector MUX₅IN of₃Input terminal, fifth 4-bit reversible Counter₅D of (A)₂The output terminal is connected to a sixth third input selector MUX₆IN of₃Input terminal, fifth 4-bit reversible Counter₅D of (A)₁The output terminal is connected to a seventh third input selector MUX₇IN of₃Input terminal, fifth 4-bit reversible Counter₅D of (A)₀The output terminal is connected toEighth three-input selector MUX₈IN of₃Input terminal, sixth 4-bit reversible Counter₆D of (A)₃The output terminal is connected to a fifth third input selector MUX₅IN of₂Input terminal, sixth 4-bit reversible Counter₆D of (A)₂The output terminal is connected to a sixth third input selector MUX₆IN of₂Input terminal, sixth 4-bit reversible Counter₆D of (A)₁The output terminal is connected to a seventh third input selector MUX₇IN of₂Input terminal, sixth 4-bit reversible Counter₆D of (A)₀The output terminal is connected to an eighth third input selector MUX₈IN of₂Input terminal, seventh 4-bit reversible Counter₇D of (A)₃The output terminal is connected to a fifth third input selector MUX₅IN of₁Input terminal, seventh 4-bit reversible Counter₇D of (A)₂The output terminal is connected to a sixth third input selector MUX₆IN of₁Input terminal, seventh 4-bit reversible Counter₇D of (A)₁The output terminal is connected to a seventh third input selector MUX₇The seventh 4-bit up/down Counter at the input of IN1₇D of (A)₀The output terminal is connected to an eighth third input selector MUX₈IN1 input terminal, first three-input selector MUX₁Output signal CR of OUT output terminal_D3Second three-input selector MUX₂Output signal CR of OUT output terminal_D2Third three-input selector MUX₃Output signal CR of OUT output terminal_D1Fourth three input selector MUX₄Output signal CR of OUT output terminal_D0Fifth three input selector MUX₅Output signal FC of OUT output terminal_D3Sixth three-input selector MUX₆Output signal FC of OUT output terminal_D2Seventh three-input selector MUX₇Output signal FC of OUT output terminal_D1Eighth third input selector MUX₈Output signal FC of OUT output terminal_D0。

Further, the charge pump CR control circuit includes first to seventy-sixth input selectors 4BIT _ MUX₁～4BIT_MUX₇；

The first to seventy-sixth input selectors 4BIT _ MUX₁～4BIT_MUX₇S of₃The input end is connected with an input signal CR_D3First to seventy-sixth input selectors 4BIT _ MUX₁～4BIT_MUX₇S of₂The input end is connected with an input signal CR_D2First to seventy-sixth input selectors 4BIT _ MUX₁～4BIT_MUX₇S of₁The input end is connected with an input signal CR_D1First to seventy-sixth input selectors 4BIT _ MUX₁～4BIT_MUX₇S of₀The input end is connected with an input signal CR_D0(ii) a The first sixteen-input selector 4BIT _ MUX₁IN of₀～IN₁₅The input terminal is sequentially connected with "0", "1", "0" and "0", and the first sixteen input selector 4BIT _ MUX₁Output terminal of the second multiplexer 4BIT _ MUX, and an OUT output terminal of the second multiplexer SM1₂IN of₀～IN₁₅The input end is sequentially connected with ' 0 ', ' 1 ', ' 0 ', and ' twenty-sixth input selector 4BIT _ MUX₂Output terminal of the signal SM2, thirty-sixth input selector 4BIT _ MUX₃IN of₀～IN₁₅The input terminal is sequentially connected with '0', '1', '0', and the thirty-sixth input selector 4BIT _ MUX₃Output terminal of the signal SM3, and a forty-sixth input selector 4BIT _ MUX₄IN of₀～IN₁₅The input end is sequentially connected with '1', '0', '1', '0', '1', '0' and '0', a forty-sixth input selector 4BIT _ MUX₄OUT output terminal of SM4, fifty-sixth input selector 4BIT _ MUX₅IN of₀～IN₁₅The input end is sequentially connected with '1', '0', '1', '0', and '0', a fifty-sixth input selector 4BIT _ MUX₅OUT output terminal of SM5, sixty-sixth input selector 4BIT _ MUX₆IN of₀～IN₁₅The input terminal is sequentially connected with '1', '0', and the sixty-sixth input selector 4BIT _ MUX₆OUT output terminal of SM6, seventy-sixth input selector 4BIT _ MUX₇IN of₀～IN₁₅The input terminal is sequentially connected with '0', '1', '0', and '0', a seventy-sixth input selector 4BIT _ MUX₇Outputs the signal SM 7.

The invention also provides a control method of the multi-source energy collecting system, which comprises the following steps:

(1) the energy collectors such as photoelectricity, thermoelectricity, radio frequency and piezoelectricity change micro energy in the environment into electric energy, and then the electric energy is processed through a corresponding interface circuit and is converted into direct current energy to be stored in a corresponding buffer capacitor;

1a) the electric energy output by the piezoelectric energy processing and buffering circuit is directly used as a power supply VDD of the whole energy collecting system, and when the power supply VDD is larger than V_REF1When the power supply VDD is smaller than V, the fourth switch can be conducted, redundant electric energy is transmitted to the load end, and when the power supply VDD is smaller than V_REF1When the current is greater than the first threshold value, the fourth switch is closed;

1b) when the voltage of the upper plate of the storage capacitor of the photoelectric, thermoelectric and radio frequency energy is greater than the threshold voltage V_X(X PV, TEG, RF), a corresponding request signal REQ is generated_PV、REQ_TEGOr REQ_RFThe arbitration circuit generates a response signal EON according to the priority and latency of the request signal_PVOr EON_TEGOr EON_RF，EON_XSignal-driven reconfigurable charge pump MPPT control circuitOutput corresponding CR_D[3:0]X and FC_D[3:0]_X(X＝PV，TEG，RF)；

1c)CR_D[3:0]The _Xis input into a charge pump CR control circuit to output corresponding SM 1-SM 7 signals to control the voltage conversion rate of the charge pump; FC_D[3:0]The signal-X adjusts the frequency of the output clock of the digitally controlled oscillator to control the switching frequency of the charge pump, while the EON is set_XThe corresponding switch can be opened to connect the energy buffer capacitor to the input end of the charge;

1d) final arbitration circuit pass signal EN_ARStarting a charge pump to transfer the charges in the buffer capacitor to an energy storage capacitor C at the load end_OUTPerforming the following steps;

(2) in the process of transferring charges from the buffer capacitor to the load by the charge pump, the fixed-time conducting comparator controls the output voltage of the charge pump by taking fixed time as a period, wherein the fixed time T_ONIs 16 CLK_COTA clock period;

2a) charge pump at time T_ONAn internal start-up to transfer charge from the interface circuit to the load; at T_ONFinally, turning on the internal comparator of the comparator for a fixed time to start the output voltage V of the charge pump_OUTAnd a reference voltage V_REF2Comparing;

2b) if V_OUTLess than V_REF2Indicating that the output power at this time is insufficient to maintain the output voltage at V_REF2Therefore, no limitation is placed on the output voltage, next CLK_COTWhen the rising edge of the T comes, the next T is started immediately_ONA period;

2c) if V_OUTGreater than V_REF2When the output power is excessive, EN indicates that_COTLow, turn off the charge pump, stop transferring charge to the load, V_OUTGradually decrease once V_OUTLess than V_REF2Then at CLK_COTWhen the rising edge of (c) comes, the charge pump is restarted and a new T is started_ONA period;

2d) at each T_ONThe 15 th CLK in a cycle_COTDuring clock, the COT output voltage control circuit generates a pulse signalNumber PULSE_SHClock driving for the subsequent sampling comparison circuit;

(3) sample-and-hold comparator for use in input signal PULSE_SHIs driven by (2), each PULSE is judged_SHThe rising edge time of the signal is compared with the last PULSE_SHSignal rising edge time V_OUTThe trend of change of (c);

3a) when V is_OUTDuring the fall, UD is low, and V is_OUTUD is high level when rising;

3b) when the sample-hold comparator makes a judgment on the level value of UD, a PULSE signal PULSE is output_MPPTThe clock driver is used for the MPPT control circuit of the reconfigurable charge pump;

(4) MPPT mode control circuit for arbitrating circuit response signal EON for each energy_X(X ═ PV, TEG, RF) responses were counted;

4a) when the counting times reach a threshold value, the MPPT mode control circuit raises the CRT, enters a charge pump voltage conversion rate adjusting stage and adjusts the charge pump CR;

4b) in PULSE_MPPTWhen the rising edge comes, if the UD signal is high level, CR is performed_D[3:0]The lowest order bit is decremented by one, and then waits for the next PULSE_MPPTA rising edge; if the UD signal is low, CR_D[3:0]The lowest order bit is incremented by one, and then CR is set_D[3:0]Is saved to CR_D[3:0]X (X) ═ PV, TEG, RF), output MODE_CHANGEA signal ends the regulation of the charge pump CR and starts the regulation of the switching frequency of the charge pump;

4c) also in PULSE_MPPTWhen the rising edge comes, if the UD signal is at high level, FC_D[3:0]The lowest order bit is decremented by one, and then waits for the next PULSE_MPPTA rising edge; FC if the UD signal is low_D[3:0]Adding one to the lowest order and then FC_D[3:0]The value of (A) is stored in FC_D[3:0]X (X) ═ PV, TEG, RF), output MODE_CHANGEAnd setting the FCT signal to be low level, and finishing the adjustment of the switching frequency of the charge pump.

Has the advantages that:

the invention adopts the charge pump with adjustable voltage conversion rate and switch working frequency to boost, and can adapt to wider input voltage range and input power range; the whole chip can be realized only by a capacitor, which is beneficial to the miniaturization of an energy collection system; the output voltage of the system is controlled by adopting a fixed conduction time method, and the generated peak voltage is multiplexed to control the voltage conversion rate and the switching working frequency of the charge pump, so that the complexity of a circuit is reduced, and the power consumption of the system is reduced. In addition, the energy collection system chip is self-powered, and the self-starting of the system can be realized under the condition of piezoelectric energy.

Drawings

FIG. 1 is a block diagram of a multi-source energy collection system of the present invention

FIG. 2A reconfigurable charge pump circuit diagram

Operation of charge pump at 8X CR in fig. 2B

Operation of charge pump in fig. 2C-14/3X CR

Operation of charge pump in fig. 2D CR 4/3X

FIG. 3 is a circuit diagram of a fixed on-time comparator

FIG. 4 sample-and-hold comparator circuit diagram

FIG. 5 MPPT mode control circuit diagram

Figure 6 reconfigurable charge pump MPPT control circuit diagram

FIG. 7 is a circuit diagram of a charge pump CR control circuit

FIG. 8 is a circuit diagram of a digitally controlled oscillator

FIG. 9 state transition diagram of arbitration circuit

FIG. 10 is a flow chart of an adaptive control circuit

Detailed Description

The technical scheme of the invention is explained in detail in the following with the accompanying drawings.

As shown in fig. 1, the energy collectors such as photovoltaic, thermoelectric, radio frequency and piezoelectric etc. change micro energy in the environment into electric energy, which is then processed by corresponding interface circuits to become direct current energy stored in corresponding buffer capacitors. In which the electric energy output by the piezoelectric energy processing and buffering circuit is directly used as the whole energy-collecting systemA power supply VDD, when the energy collection system is automatically started, the output electric energy of the piezoelectric interface circuit is in C_PZThe capacitor is accumulated, so that VDD gradually rises, when VDD is larger than 1.2V, the energy collection system is started up, and the self-starting mode is entered into the energy collection mode. When VDD is larger than V_REF1While, the fourth switch S is turned on₄Conducting to transmit the redundant power to the load end when VDD is less than V_REF1Then the fourth switch S is closed₄And the power supply voltage of the energy collection system is ensured to be stable. When the voltage on the storage capacitor of the photoelectric, thermoelectric and radio frequency energy is greater than the threshold voltage V_X(X ═ PV, TEG, RF, and the like), a corresponding request signal REQ is generated_PV、REQ_TEGOr REQ_RFThe arbitration circuit generates a response signal EON according to the priority and latency of the request signal_PVOr EON_TEGOr EON_RF，EON_XThe signal can enable the reconfigurable charge pump MPPT control circuit to output corresponding CR_D[3:0]X and FC_D[3:0]X, wherein CR_D[3:0]The _Xis input into a charge pump CR control circuit, so that the charge pump CR control circuit outputs corresponding SM 1-SM 7 signals to control the voltage conversion rate of the charge pump; FC_D[3:0]X signal regulating digital controlled oscillator output clock CLK_CPTo control the switching operating frequency of the charge pump. Simultaneous EON_XWill open the corresponding switch to connect the energy buffer capacitor to the input terminal of the charge, and the final arbitration circuit will pass the signal EN_ARStarting a charge pump to transfer the charges in the energy buffer capacitor to an energy storage capacitor C at the load end_OUTIn (1).

During the process that the charge pump transmits the charges from the buffer capacitor to the load, the fixed-time conduction comparator detects and controls the output voltage of the charge pump by taking the fixed time as a period, wherein the fixed time T_ONIs 16 CLK_COTA clock cycle. Charge pump at time T_ONAn internal start-up to transfer charge from the interface circuit to the load; at T_ONFinally, turning on the internal comparator of the comparator for a fixed time to start the output voltage V of the charge pump_OUTAnd a reference voltage V_REF2A comparison is made. If V_OUTLess than V_REF2To show that this is the caseThe output power is not sufficient to maintain the output voltage at V_REF2Therefore, no limitation is placed on the output voltage, next CLK_COTWhen the rising edge of the T comes, the next T is started immediately_ONA period; if V_OUTGreater than V_REFWhen the output power is excessive, EN indicates that_COTLow, turn off the charge pump, stop transferring charge to the load, V_OUTGradually decreases. Once V is_OUTLess than V_REF2Then at CLK_COTWill restart the charge pump and start a new T when the rising edge of (c) comes_ONAnd (4) period. At each T_ONThe 15 th CLK in a cycle_COTWhen the clock is running, the comparator circuit will generate a PULSE signal PULSE_SHAnd the clock driving circuit is used for clock driving of the subsequent sampling comparison circuit.

The sample-and-hold comparator will be at PULSE_SHIs driven by (2), each PULSE is judged_SHV at the time of rising edge of signal_OUTVoltage comparison last PULSE_SHV at the time of rising edge of signal_OUTTrend of change in voltage, if V_OUTDown, UD is low, if V_OUTUD goes high. When sampling and holding comparator pair V_OUTAfter the change trend of the voltage is judged once and the UD signal is output, a PULSE signal PULSE is output_MPPTAnd the circuit is used for clock driving of the reconfigurable charge pump MPPT control circuit.

MPPT mode control circuit responds to EON signal for each energy_XWhen the counted times reach a threshold value, the MPPT mode control circuit can set the CRT high, so that the reconfigurable charge pump MPPT control circuit enters a charge pump voltage conversion rate adjusting stage to adjust the charge pump CR, and each PULSE is provided with a plurality of PULSE signals_MPPTWhen the rising edge comes, if the UD signal is high level, CR is performed_D[3:0]The lowest order bit is decremented by one, and then waits for the next PULSE_MPPTA rising edge; if the UD signal is low, CR_D[3:0]The lowest order bit is incremented by one, and then CR is set_D[3:0]Is saved to CRD [3:0 ]]In _X, output MODE_CHANGEA signal. Receiving MODE by MPPT MODE control circuit_CHANGEAfter the signal, the CRT is set to be low, the FCT is set to be high, and the reconfigurable charge pump MPPT control circuit finishes the adjustment of the charge pump CR and starts the adjustment of the switching frequency of the charge pump. Also in PULSE_MPPTWhen the rising edge comes, if the UD signal is at high level, FC_D[3:0]The lowest order bit is decremented by one, and then waits for the next PULSE_MPPTA rising edge; FC if the UD signal is low_D[3:0]Adding one to the lowest order and then FC_D[3:0]The value of (A) is stored in FC_D[3:0]In _X, output MODE_CHANGEAnd the MPPT mode control circuit sets the FCT signal to be low level, and the MPPT control circuit of the reconfigurable charge pump finishes the adjustment of the switching frequency of the charge pump.

As shown in fig. 2A, the reconfigurable charge pump of the present invention can change its structure to adjust CR to accommodate different input voltages and reduce charge redistribution loss. The charge pump of the invention adopts a nested structure, so that the number of switches and capacitors is as small as possible under the condition of obtaining higher CR. The first stage charge pump is a voltage-multiplying charge pump, and comprises fifth to tenth switches S₅～S₁₀A first capacitor C₁And a second capacitor C₂AND gates AND₂～AND₅A first non-overlapping signal generating circuit NO1 and a second non-overlapping signal generating circuit NO2 which convert the input voltage from V_INPump to 2V_IN(ii) a The second stage charge pump is also a voltage-multiplying charge pump, and comprises eleventh to eighteenth switches S₁₁～S₁₈A third capacitor C₃And a fourth capacitance C₄AND AND gates of the sixth to ninth₆～AND₉A third non-overlapping signal generating circuit NO3 and a fourth non-overlapping signal generating circuit NO4, a first demultiplexer DEMUX1 and a second demultiplexer DEMUX2, which pump the output voltage of the first stage charge pump to 3V_INOr 4V_INThe different output voltages are controlled by the SM2 signal, a first demultiplexer DEMUX1 and a second demultiplexer DEMUX 2; the third stage charge pump is a 1/3 or 2/3 fractional charge pump and comprises thirty-first to forty-first switches S₃₁～S₄₁Seventh toA tenth capacitor C₇～C₁₀The tenth AND gate AND₁₀AND the eleventh AND gate AND₁₁A second inverter INV₂And a third inverter INV₃First OR gate OR₁NOR of first NOR gate₁A first NAND gate NAND₁And a seventh non-overlapping signal generating circuit NO7, the different output voltages being controlled by the SM6, SM7 signals; the fourth stage charge pump is a voltage-multiplying charge pump and comprises nineteenth to thirtieth switches S₁₉～S₃₀And a forty-second switch S₄₂And a forty-third switch S₄₃A fifth capacitor C₅A sixth capacitor C₆Fifth and sixth non-overlapping signal generating circuits NO5 and NO6, a third demultiplexer DEMUX3 and a fourth demultiplexer DEMUX4, the inputs of which are the outputs of the first three stages of charge pumps, are controlled by signals SM4 and SM5, a third demultiplexer DEMUX3 and a fourth demultiplexer DEMUX 4. The preferable values of CR of the designed reconfigurable charge pump are as follows from large to small: 8X, 6X, 5X, 14/3X, 13/3X, 4X, 11/3X, 10/3X, 3X, 8/3X, 7/3X, 2X, 5/3X, 4/3X.

Fig. 2B, 2C, and 2D are circuit diagrams of the charge pump operation when CR is 8X, CR, 14/3X, CR, 4/3X, respectively, in which only one half cycle of the charge pump operation is shown, and the other half cycle is in the same principle, and devices are exchanged.

As shown in fig. 2B, when CR is 8X, the first stage charge pump generates a 2V output_INThe output voltage of (1); the two-way selector in the second stage circuit pump selects the output (2V) of the first stage charge pump_IN) As input, a 4V is generated_INThe output voltage of (1); the third stage charge pump is turned off; the four-way selector in the fourth stage charge pump selects the output (4V) of the second stage charge pump_IN) As input, an 8V is generated_INAnd outputting the voltage.

As shown in fig. 2C, the first stage charge pump generates 2V when CR is 14/3X_INThe output voltage of (1); the two-way selector in the second stage circuit pump selects the output (2V) of the first stage charge pump_IN) As input, a 4V is generated_INThe output voltage of (1); the third stage charge pump generates a 2-3V_INThe output voltage of (1); the fourth stage charge pump outputs (4V) to the second stage charge pump in turn_IN) And the output of the third stage charge pump (2/3V)_IN) As inputs to the upper and lower plates, respectively, an 14/3V is generated_INAnd outputting the voltage.

As shown in fig. 2D, when CR is 4/3X, the first stage charge pump and the second stage charge pump are turned off; the third stage charge pump generates 1/3V_INThe output voltage of (1); the fourth stage charge pump sequentially converts V_INAnd the output of the third stage charge pump (1/3V)_IN) Respectively as the input of the upper and lower polar plates to generate 4/3V_INAnd outputting the voltage.

As shown in fig. 3, at each CLK_COTThe rising edge of the clock is clocked by the four bit counter output, which is incremented by one, and the output of the counter is incremented from 0000 to 1110, which is the third NOR gate NOR₃Output PULSE of_SHGoes high when CLK_COTThe rising edge of the clock is again temporary and the output of the four bit counter becomes 1111, when the third NOR gate NOR₃Output PULSE of_SHGoes low, and a second NOR gate NOR₂Output EN of_LCGoing high, the latching comparator starts. If the output voltage V of the charge pump is at this time_OUTSpecific reference voltage V_REF2Large, then output EN of latching comparator_CPGoes high, at which point the output of the four bit counter no longer changes, remains at 1111, and the latching comparator continues comparator V_OUTAnd V_REF2Up to V_OUTLess than V_REF2Latching the output EN of the comparator_CPGoes low and is next CLK_COTWhen the rising edge comes, the output of the four-bit counter changes from 1111 to 0000, the latch comparator is closed, and the counter starts counting again; if the output voltage V of the charge pump is at this time_OUTSpecific reference voltage V_REF2Small, then output EN of the latch comparator_CPAt low level, next CLK_COTWhen the rising edge arrives, the output of the four-bit counter goes directly from 1111 to 0000, the latching comparator turns off, and the four-bit counter restarts counting.

When the PULSE signal is PULSE, as shown in FIG. 4_SHComingIf FL is low, the forty-fifth switch S is closed first₄₅Output voltage V of charge pump_OUTSample to the twelfth capacitor C₁₂The above. Then PULSE signal PULSE_SHVia a first exclusive-or gate XOR₁And a first Delay unit Delay₁Coming to P₁Starting the comparator to convert the eleventh capacitor C₁₁And a twelfth capacitor C₁₂The voltage on the signal is compared, and the comparison result is compared with the FL signal to obtain X₁Is input to a subsequent third D flip-flop DFF₃The D terminal of (1). Followed by PULSE signal PULSE_SHCome to P₂Is mixing X₁Stored in a third D flip-flop DFF₃Finally, the UD signal is obtained. If V_OUTAt the increase, the twelfth capacitor C₁₂The sampled voltage on is larger than that of the eleventh capacitor C₁₁The comparator outputs high level, and the signal X is obtained by performing exclusive or operation with the signal FL₁Low and finally UD high, i.e. V_OUTDuring the rising process; if V_OUTIn descending, the twelfth capacitor C₁₂The sampled voltage on is less than that of the eleventh capacitor C₁₁The comparator outputs low level, and the signal X is obtained by performing exclusive or operation with the signal FL₁At a high level, and finally UD is at a low level, i.e. V_OUTAnd is falling. When PULSE signal PULSE_SHLeave P₂The FL signal is inverted. When PULSE signal PULSE_SHRising edge comes to P₃When it is in use, a PULSE signal is generated_MPPT。

Each time the arbiter responds to the first PULSE signal PULSE after the state switch_SHAnd temporarily, because the voltage held on one sampling capacitor of the sample-hold comparison circuit is the voltage in the response state of the last arbiter, the comparison result of the sample-hold comparison circuit at this time cannot correctly reflect the change condition of the output voltage in the new state. For this case, the following design is made: EN when the response status of the arbiter switches_ARThe signal goes low for a brief period of time, causing the UD signal to go high and the FK signal to go low. First pulse when new stateSignal PULSE_SHGenerating a comparison result X₁Then, shield X by FK signal₁Keeping the UD signal unchanged and not outputting PULSE_MPPTA pulse signal. When PULSE signal PULSE_SHLeave P₂Time-reversal of FL signal and final PULSE signal PULSE_SHTo P₄The FK signal is set high.

As shown in fig. 5, when the MPPT mode control circuit is activated, both the CRT and the FCT are set to low level. When the counted number of the first counter to the third counter to the EON _ X reaches the threshold value, a high level pulse is output, and the rising edge of the pulse enables the output CRT of the fifth trigger to be changed into high level. When MODE_CHANGEWhen the falling edge of the signal comes, the seventh D flip-flop DFF is triggered₇Generates a low level pulse signal that will trigger the fifth D flip-flop DFF₅Is turned to a low level, and the sixth DELAY unit DELAY₆Is longer than the seventh D flip-flop DFF₇So that the falling edge of the CRT will cause the sixth D flip-flop DFF to be activated₆The output FCT of (a) becomes high level. When MODE_CHANGEThe falling edge of the signal comes again temporarily, the sixth D flip-flop DFF₆The output FCT of (a) is set to low level.

As shown in fig. 6, when the MPPT control circuit of the reconfigurable charge pump is started, the second to fourth 4-bit reversible counters Counter₂～Counter₄Is set to 1101, and fifth to seventh 4-bit up-down counters Counter₅～Counter₇The output of (d) is set to 1111. When CRT is 1, EON is determined if the CRT is at the time_PVIs 1, the second 4-bit reversible Counter₂Starting when PULSE_MPPTWhen the rising edge comes, if UD is low level, the second 4-bit reversible Counter₂Is decremented by one, and if UD is high at this time, a second 4-bit up-down Counter₂Plus one (not more than 1101). If EON is present_TEGOr EON_RFWhen 1, start the third 4-bit reversible Counter₃Or a fourth 4-bit up/down Counter₄，PULSE_MPPTThe rising edge timer changes in the same manner as above. When FCT is 1, EON if it is at this time_PVIs 1, the fifth 4-bit reversible Counter₅Starting when PULSE_MPPTWhen the rising edge comes, if UD is low level at this time, the fifth 4-bit reversible Counter₅Is decremented by one, and if UD is high at this time, the fifth 4-bit up-down Counter₅The lowest bit of the output of (a) is incremented by one (no more than 1111). If EON is present_TEGOr EON_RFWhen 1, start the sixth 4-bit reversible Counter₆Or a seventh 4-bit up/down Counter₇， PULSE_MPPTThe rising edge timer changes in the same manner as above. When EON is reached_PVWhen the output value is 1, the CR output by the MPPT control circuit of the reconfigurable charge pump_D[3:0]Is a second 4-bit reversible Counter₂Value of (C), FC_D[3:0]Is a fifth 4-bit reversible Counter₅A value of (d); when EON is reached_TEGWhen the output value is 1, the CR output by the MPPT control circuit of the reconfigurable charge pump_D[3:0]Is a third 4-bit reversible Counter₃Value of (C), FC_D[3:0]Is a sixth 4-bit reversible Counter₆A value of (d); when EON is reached_RFWhen the output value is 1, the CR output by the MPPT control circuit of the reconfigurable charge pump_D[3:0]Is a fourth 4-bit reversible Counter₄Value of (C), FC_D[3:0]Is a seventh 4-bit reversible Counter₇The value of (c).

As shown in FIG. 7, the charge pump CR control circuit is composed of seven multi-input selectors, with different CRs_D[3:0]Will output different SM1 and SM 7. For each multiple input selector, when its output selects terminal S₃～S₀When changing from 0000 to 1111, the output selector will select IN IN turn₀～IN₁₅The input signal of the terminal is used as the output signal of the multi-input selector. When CR is reached_D[3:0]0000, the output signals SM1 SM7 of the CR control circuit of the charge pump are 0001110 in sequence, and when CR is equal to_D[3:0]At 0001, the output signals SM 1-SM 7 of the control circuit of the charge pump CR are 0001111 in sequence, when CR is equal to_D[3:0]0010, the output signal SM 1S of the control circuit of the charge pump CRM7 is in turn 0000100, when CR is_D[3:0]0011, the output signals SM 1-SM 7 of the CR control circuit of the charge pump are 0101110 in sequence, when CR is_D[3:0]0100, the output signals SM 1-SM 7 of the control circuit of the charge pump CR are 0101111 in sequence, when CR is in the state_D[3:0]0101, the output signals SM 1-SM 7 of the control circuit of the charge pump CR are 0100100 in sequence, when CR is equal to_D[3:0]0110, the output signals SM 1-SM 7 of the CR control circuit of the charge pump are 1101110 in sequence, when CR is equal to_D[3:0]0111, the output signals SM 1-SM 7 of the CR control circuit of the charge pump are 1101111 in sequence, when CR is equal to_D[3:0]When the output signal is 1000, the output signals SM 1-SM 7 of the charge pump CR control circuit are 0101000 in sequence, and when CR is in the state_D[3:0]When the output signals SM 1-SM 7 of the CR control circuit of the charge pump are 1111110 in turn, when CR is 1001_D[3:0]At 1010, the output signals SM 1-SM 7 of the CR control circuit of the charge pump are 1111111 in sequence, and when CR is in_D[3:0]At 1011, the output signals SM1 SM7 of the charge pump CR control circuit are 1110100 in sequence, when CR is_D[3:0]When the output signal is 1100, the output signals SM 1-SM 7 of the CR control circuit of the charge pump are 1110000 in sequence, and when CR is in_D[3:0]At 1101, the output signals SM1 to SM7 of the charge pump CR control circuit are 1111000 in order.

As shown in fig. 8, in the dco circuit, M0-M4 are bias generating circuits, which generate two bias voltages VP and VN for biasing the oscillation unit. The digital oscillation circuit main body is formed by connecting five oscillation units in series through a transmission gate controlled by an EN signal. When EN is high level, the transmission gate is conducted, and the five oscillation units are connected end to form a closed loop to generate a clock signal CLK. The five oscillating units are identical, each oscillating unit is a current starved inverter to increase the minimum delay of the oscillating unit, and each oscillating unit has a capacitor array controlled by a digital signal to control the delay size of each delay unit. FC_D[3]Controlling the thirteenth capacitance C₁₃When FC is_D[3]When low, the thirteenth capacitor C₁₃The transmission gate between the output end of the oscillation unit is conducted, otherwise, the transmission gate is turned off; FC_D[2]Control the fourteenth capacitance C₁₄When FC is_D[2]At a low timeFourteenth capacitance C₁₄The transmission gate between the output end of the oscillation unit is conducted, otherwise, the transmission gate is turned off; FC_D[1]Control the fifteenth capacitance C₁₅When FC is_D[1]When low, the fifteenth capacitor C₁₅The transmission gate between the output end of the oscillation unit is conducted, otherwise, the transmission gate is turned off; FC_D[0]Control the sixteenth capacitor C₁₆When FC is_D[0]When low, the sixteenth capacitor C₁₆And a transmission gate between the output end of the oscillating unit is conducted, otherwise, the transmission gate is turned off. The four capacitors in the oscillating unit are a thirteenth capacitor C from large to small₁₃And a fourteenth capacitor C₁₄A fifteenth capacitor C₁₅Sixteenth capacitor C₁₆. When FC is_D[3:0]0000, all the transmission gates of the capacitors are opened, all the capacitors are connected to the output end of the oscillation unit, and the CLK frequency of the output of the digital controlled oscillator is the lowest, when FC is used_D[3:0]And 1111, the transmission gates of all the capacitors are closed, all the capacitors are not connected to the output end of the oscillation unit, and the output CLK frequency of the digital control oscillator is the highest.

As shown in fig. 9, in the invention, the arbiter adopts a Round Robin priority arbiter (Round Robin arbiter), whose working logic is to continuously cycle through each requester, and if the requester sends out a request, respond to the requester for a fixed time; then judging the next requester, if the requester has request, responding, otherwise, continuing to judge the next bit. When all requesters are judged once, the next round of traversal is started. The maximum waiting time of the requesters is thus made explicit, depending on the number of requesters. A specific arbitration logic state transition diagram is shown in fig. 9. Wherein REQ _ X represents three requests for energy collection, REQ _ X ═ 1 represents that the requester sends a request signal, REQ _ X ═ 0 represents that the requester does not send a request signal; EON _ X represents the response state of the arbiter. The arbiter is controlled by the clock signal CLK _ A, and when the rising edge of each clock comes, the arbiter determines the current request state (states A-F in FIG. 9), and determines the next state according to the signal request state and the current state responded by the arbiter. Assuming the current arbiter is in the RON _ PV state, if REQ _ TEG is 1 when CLK _ a rising edge is imminent, the arbiter transitions to the EON _ TEG state; if REQ _ RF 1 and REQ _ TEG 0 are imminent when the CLK _ a rising edge comes, the arbiter transitions to the EON _ RF state; if REQ _ PV is 1 and REQ _ TEG is 0 and REQ _ RF is 0 when CLK _ a rising edge is imminent, the arbiter will remain in EON _ PV state; if REQ _ PV is 0, REQ _ TEG is 0, REQ _ RF is 0 when CLK _ a rising edge is imminent, the arbiter transitions to Wait state.

As shown in fig. 10, CR_D[3:0]X and FC_D[3:0]X (X ═ PV, TEG, RF, and the same below) stores CR and switching frequency FC of the charge pumps corresponding to the three energy interface circuits, respectively; CR_D[3:0]And FC_D[3:0]Is a signal for controlling the charge pump CR and the switching frequency FC output by the control circuit; EON _ X is the response state of the arbiter; counter _ X is used to count the number of times the arbiter responds to a certain energy; CRT and FCT are enable signals for adjustment of the charge pump CR and switching frequency, respectively, which when CRT or FCT is high represents the start of adjustment of the CR or switching frequency of the charge pump; UD is the output signal of the sample-and-hold comparator, and a high level represents that the output power of the output charge pump is greater than the power consumption of the load, and a low level represents that the output power of the charge pump is less than the power consumption of the load.

When the control circuit is started, CR is set_D[3:0]The initial value of _ X is set to 1101, FC is set to correspond to the maximum CR_D[3:0]The initial value of _Xis set to 1111, corresponding to the highest switching frequency, and Counter _ X is set to 0. Whenever the arbitration circuit responds to a change in state, such as switching from PV to TEG, the corresponding Counter _ TEG increments by one and CR_D[3:0]TEG and FC_D[3:0]Loading of stored State in TEG into CR_D[3:0]And FC_D[3:0]And determining whether the value of the Counter _ TEG reaches a threshold value, if so, entering a charge pump regulation stage, and resetting the Counter _ TEG.

Entering the charge pump adjusting stage, the CRT signal is first set to high level, i.e. the charge pump CR is adjusted. In PULSE_MPPTWhen the rising edge comes, if the UD signal is high level, CR is performed_D[3:0]Subtract one, then wait for the next PULSE_MPPTA rising edge; if the UD signal is low, CR_D[3:0]Adding one, then CR_D[3:0]The value of (A) is stored in CR_D[3:0]In _X, the CRT signal is set low, ending the charge pump CR adjustment.

The charge pump CR regulation is completed immediately before the charge pump switching frequency FC regulation is started. Firstly, the FCT signal is set to high level, and at PULSE_MPPTWhen the rising edge comes, if the UD signal is at high level, FC_D[3:0]Subtract one, then wait for the next PULSE_MPPTA rising edge; FC if the UD signal is low_D[3:0]Adding one, then adding FC_D[3:0]The value of (A) is stored in FC_D[3:0]In _x, the FCT signal is set to low, and the adjustment of the switching frequency of the charge pump is ended.

The above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modifications made on the basis of the technical scheme according to the technical idea of the present invention fall within the protection scope of the present invention.

Claims

1. A multi-source energy harvesting system, characterized by: the device comprises a piezoelectric energy collector, a photoelectric energy collector, a thermoelectric energy collector, a radio frequency antenna energy collector, a piezoelectric processing and buffering circuit, a photoelectric processing and buffering circuit, a thermoelectric processing and buffering circuit, a radio frequency processing and buffering circuit, a reconfigurable charge pump, a charge pump CR control circuit, a digital control oscillator, a reconfigurable charge pump MPPT control circuit, an MPPT mode control circuit, an arbitration circuit, a sample-hold comparator, a fixed conduction time comparator and a self-starting circuit;

the photoelectric processing and buffering circuit comprises a photoelectric interface circuit and a first switch S₁And a photoelectric buffer capacitor C_PVOutput V of the opto-electronic interface circuit_PVConnecting photoelectric buffer capacitor C_PVUpper plate of and first switch S₁One terminal of (1), a photoelectric buffer capacitor C_PVThe lower polar plate is connected with the ground wire, the first switch S₁Is connected to the IN voltage input of the reconfigurable charge pumpA terminal;

the radio frequency processing and buffering circuit comprises a radio frequency interface circuit and a third switch S₃Radio frequency buffer capacitor C_RFOutput V of the RF interface circuit_RFConnecting radio frequency buffer capacitor C_RFUpper plate and third switch S₃One terminal of (1), a radio frequency buffer capacitor C_RFThe lower polar plate is connected with the ground wire, and a third switch S₃The other end of the reconfigurable charge pump is connected with an IN voltage input end of the reconfigurable charge pump;

the self-starting circuit comprises an under-voltage locking circuit and a first inverter INV₁And a fourth switch S₄A first comparator COMP₁The VDD input end of the undervoltage locking circuit is connected with the output VDD of the piezoelectric interface circuit, and the UVLO output end of the undervoltage locking circuit is connected with the first inverter INV₁The first inverter INV₁The output end of the first switch is connected with the RESET input end of the photoelectric interface circuit, the RESET input end of the thermoelectric interface circuit, the RESET input end of the arbitration circuit, the RESET input end of the reconfigurable charge pump MPPT control circuit and the fourth switch S₄One end of the fourth switch is connected with the output VDD of the piezoelectric interface circuit₄The other end is connected with an OUT output end of the reconfigurable charge pump, and a first comparator COMP₁The positive phase input end of the first comparator COMP is connected with the output VDD of the piezoelectric interface circuit₁Negative phase input terminal of the first reference voltage V_REF1First comparator COMP₁Output PZS is connected with the fourth switchOff S₄The control terminal of (1); output signal REQ of an opto-electrical interface circuit_PVOutput signal REQ of thermoelectric interface circuit_TEGOutput signal REQ of radio frequency interface circuit_RFRespectively connected to the input end of the arbitration circuit and the output signal EON of the arbitration circuit_PVEON accessing MPPT mode control circuit_PVEON of signal input end and reconfigurable charge pump MPPT control circuit_PVSignal input terminal and first switch S₁Control terminal of (2), output signal EON of arbitration circuit_TEGEON accessing MPPT mode control circuit_TEGEON of signal input end and reconfigurable charge pump MPPT control circuit_TEGSignal input terminal and second switch S₂Control terminal of (2), output signal EON of arbitration circuit_RFEON accessing MPPT mode control circuit_RFEON of signal input end and reconfigurable charge pump MPPT control circuit_RFSignal input terminal and third switch S₃The first AND gate AND₁And EN of a sample-and-hold comparator_AROutput signal EN with input end connected to arbitration circuit_AR(ii) a An output signal CRT of the MPPT mode control circuit is accessed to a CRT input end of the reconfigurable charge pump MPPT control circuit and a CRT input end of a sample-hold comparator, and an output signal FCT of the MPPT mode control circuit is accessed to an FCT input end of the reconfigurable charge pump MPPT control circuit and an FCT input end of the sample-hold comparator; first reference clock CLK_COTA second reference voltage V_REF2And an OUT terminal output signal V of the reconfigurable charge pump_OUTRespectively connected to the input end of the fixed time conduction comparator, and the output signal EN of the fixed time conduction comparator_COTConnected to a first AND gate AND₁Another input terminal of the comparator, the output signal PULSE of the fixed-time conduction comparator_SHPULSE with access to sample-and-hold comparator_SHAn input end; OUT terminal output signal V of reconfigurable charge pump_OUTThe output signal PULSE of the sample-and-hold comparator is connected to the input end of the sample-and-hold comparator_MPPTPULSE connected to reconfigurable charge pump MPPT control circuit_MPPTThe output signal UD of the sample-hold comparator is connected to the UD input end of the reconfigurable charge pump MPPT control circuit(ii) a Output signal MODE of reconfigurable charge pump MPPT control circuit_CHANGEMODE accessed to MPPT MODE control circuit_CHANGEInput terminal, output signal CR of reconfigurable charge pump MPPT control circuit_D3、CR_D2、CR_D1、CR_D0Respectively connected to the input end of the CR control circuit of the charge pump to reconstruct the output signal FC of the MPPT control circuit of the charge pump_D3、FC_D2、FC_D1、FC_D0Respectively accessing to the input ends of the numerically controlled oscillators; seven output signals SM 1-SM 7 of the charge pump CR control circuit are connected to a CR input end of the reconfigurable charge pump; output signal CLK of a digitally controlled oscillator_CPSwitching in a CLK input end of the reconfigurable charge pump; first AND gate AND₁Output signal EN of_CPThe EN input end of the reconfigurable charge pump is accessed; the output end OUT of the reconfigurable charge pump passes through a capacitor C_OUTAnd a ground line.

2. The multi-source energy harvesting system of claim 1, wherein: the reconfigurable charge pump comprises a first-stage charge pump, a second-stage charge pump, a third-stage charge pump and a fourth-stage charge pump;

the first stage charge pump comprises fifth to tenth switches S₅~S₁₀A first capacitor C₁And a second capacitor C₂AND gates AND₂~AND₅A first non-overlapping signal generating circuit NO1 and a second non-overlapping signal generating circuit NO 2;

The second-stage charge pump comprises eleventh to eighteenth switches S₁₁~S₁₈A third capacitor C₃And a fourth capacitance C₄AND AND gates between the sixth AND ninth₆~AND₉A third non-overlapping signal generating circuit NO3 and a fourth non-overlapping signal generating circuit NO4, a first demultiplexer DEMUX1 and a second demultiplexer DEMUX 2;

the eleventh switch S₁₁And an eighteenth switch S₁₈Is connected to the output V1L of the first stage charge pump, a twelfth switch S₁₂And a seventeenth switch S₁₇Is connected to the output V1R of the first stage charge pump, a fifteenth switch S₁₅And a sixteenth switch S₁₆Is connected to the input voltage V of the reconfigurable charge pump_INThe eleventh switch S₁₁Is connected at the other end to a third capacitance C₃Upper pole plate of (1), twelfth switch S₁₂Is connected to a fourth capacitance C at the other end₄Upper pole plate of (1), seventeenth switch S₁₇The other end of (1), a fifteenth switch S₁₅And the other end of the thirteenth switch S₁₃Is connected to a third capacitor C₃Lower pole plate of (1), eighteenth switch S₁₈The other end of (1), a sixteenth switch S₁₆And a fourteenth switch S₁₄Is connected to a fourth capacitor C₄Lower plate of, a thirteenth switch S₁₃And a fourteenth switch S₁₄Is connected to ground, a seventh AND gate AND₇AND eighth AND gate AND₈Is connected with the input signals SM2 AND S2N, a seventh AND gate AND₇Is connected with a twelfth switch S₁₂Control terminal of, eighth AND gate AND₈Is connected to the input of the third non-overlapping signal generating circuit NO3, a sixth AND gate AND₆AND the ninth AND gate AND₉Is connected to the input signals SM2 AND S2P, a sixth AND gate AND₆Is connected with an eleventh switch S₁₁The ninth AND gate AND₉Is connected to an input terminal of a fourth non-overlapping signal generating circuit NO4, and an N-terminal output of a third non-overlapping signal generating circuit NO3 is connected to a thirteenth switch S₁₃A P terminal output of the third non-overlapping signal generating circuit NO3 is connected to an input terminal of the first demultiplexer DEMUX1, and an N terminal output of the fourth non-overlapping signal generating circuit NO4 is connected to the fourteenth switch S₁₄A P terminal output of the fourth non-overlapping signal generating circuit NO4 is connected to an input terminal of the second demultiplexer DEMUX2, an a terminal output of the first demultiplexer DEMUX1 is connected to the fifteenth switch S₁₅A B terminal output of the first demultiplexer DEMUX1 is connected to a seventeenth switch S₁₇A terminal a of the second demultiplexer DEMUX2 is connected to a sixteenth switch S₁₆A B terminal output of the second demultiplexer DEMUX2 is connected to an eighteenth switch S₁₈The input signal SM3 is connected to the select terminal of the first demultiplexer DEMUX1 and the select terminal of the second demultiplexer DEMUX 2;

the third stage charge pump comprises thirty-first to forty-first switches S₃₁~S₄₁Seventh to tenth capacitors C₇~C₁₀The tenth AND gate AND₁₀AND the eleventh AND gate AND₁₁A second inverter INV₂And a third inverter INV₃First OR gate OR₁NOR of first NOR gate₁A first NAND gate NAND₁And a seventh non-overlapping signal generating circuit NO 7;

the thirty-first switch S₃₁One end of the voltage-measuring circuit is connected with the input voltage V of the charge pump_INThe thirty-first switch S₃₁Is connected to a seventh capacitor C at the other end₇Upper pole plate, thirty-two switch S₃₂And a thirty-fifth switch S₃₅One end of (1), a thirty-two switch S₃₂Is connected with an eighth capacitor C₈Upper pole plate and thirty-third switch S₃₃And a thirty-sixth switch S₃₆One end of (1), a thirty-third switch S₃₃Is connected to a ninth capacitor C at the other end₉Upper polar plate, thirty-fourth switch S₃₄And a thirty-seventh switch S₃₇One end of (1), a thirty-fourth switch S₃₄Is connected to a tenth capacitor C at the other end₁₀Upper plate of and a thirty-fifth switch S₃₅The other end of (1), a sixteenth switch S₃₆Is connected to a seventh capacitor C at the other end₇Lower pole plate and thirty-eighth switch S₃₈And a fortieth switch S₄₀One end of (1), a third seventeen switch S₃₇Is connected to an eighth capacitor C at the other end₈And a thirty-ninth switch S₃₉At one end of (1), the fortieth switch S₄₀Is connected to a forty-first switch S at the other end₄₁One end of (1), a third eighteen switch S₃₈Is connected to ground, a thirty-ninth switch S₃₉Is connected to ground, a forty-first switch S₄₁Is connected to ground, a tenth AND gate AND₁₀The input of the first AND second AND-gate AND is connected with the input signal S3N/S3P AND the input signal SM6₁₀Is connected to an input terminal of a seventh non-overlapping signal generating circuit NO7, an N-terminal output of the seventh non-overlapping signal generating circuit NO7 is connected to the second inverter INV₂Input terminal of, eleventh AND gate AND₁₁An input terminal of, a twenty-ninth switch S₂₉Control terminal of andthirty-fifth switch S₃₅And a P terminal output of the seventh non-overlapping signal generating circuit NO7 is connected to the third inverter INV₃Input terminal of (1), first OR gate OR₁An input terminal of, a twenty-seventh switch S₂₇And a thirty-third switch S₃₃The second inverter INV₂Is connected to the first NOR gate NOR₁An input terminal of the third inverter INV₃Is connected to the first NAND gate NAND₁An eleventh AND gate AND₁₁First NOR gate NOR₁Another input terminal of the first NAND gate NAND₁And a first OR gate OR₁Is connected to the input signal SM7, an eleventh AND gate AND₁₁Is connected to the thirty-first switch S₃₁Control terminal and the thirty-sixth switch S₃₆First NOR gate NOR₁Is connected to the twenty-eight switch S₂₈And a control terminal of the thirty-fourth, first NAND gate NAND₁Is connected to a thirtieth switch S₃₀And a seventeenth switch S₃₇A first OR gate OR₁Is connected to the thirty-second switch S₃₂The control terminal of (1);

the fourth stage charge pump comprises nineteenth to thirtieth switches S₁₉~S₃₀And a forty-second switch S₄₂And a forty-third switch S₄₃A fifth capacitor C₅A sixth capacitor C₆A fifth non-overlapping signal generating circuit NO5 and a sixth non-overlapping signal generating circuit NO6, a third demultiplexer DEMUX3 and a fourth demultiplexer DEMUX 4;

the nineteenth switch S₁₉One end of (1), a twentieth switch S₂₃And a twenty-sixth switch S₂₆Is connected to the output V2L of the second stage charge pump, a twentieth switch S₂₀One end of and the twenty-fourth switch S₂₄And a twenty-fifth switch S₂₅Is connected to the output V2R of the second stage charge pump, a twenty-seventh switch S₂₇One end of (A)And a twenty-eighth switch S₂₈Is connected to the input voltage V of the reconfigurable charge pump_INTwenty ninth switch S₂₉Is connected to the output V3L of the third stage charge pump, a thirtieth switch S₃₀Is connected to the output V3R of the third stage charge pump, a nineteenth switch S₁₉Is connected to a fifth capacitance C at the other end₅Upper plate of and a forty-second switch S₄₂One end of (1), the twentieth switch S₂₀Is connected to a sixth capacitor C at the other end₆Upper plate and a forty-third switch S₄₃One end of (1), the twentieth switch S₂₃Is connected to a fifth capacitance C at the other end₅Lower polar plate and twenty-fifth switch S₂₅The other end of the first switch S and a twenty-seventh switch S₂₇The other end of the first switch S and a twenty-ninth switch S₂₉And the other end of (1) and the twenty-first switch S₂₁One end of (1), a twenty-four switch S₂₄Is connected to a sixth capacitor C at the other end₅Lower polar plate and twenty-sixth switch S₂₆The other end of (1), the twenty-eighth switch S₂₈Another end of (1), thirtieth switch S₃₀And the other end of the second switch S₂₂One end of (1), the twenty-first switch S₂₁The other end of the first switch is connected with a ground wire, and a twenty-second switch S₂₂Is connected to ground, a forty-second switch S₄₂And the other end of the forty-third switch S₄₃Is connected at the other end to V of the charge pump_OUTAn output terminal, an input terminal of the fifth non-overlapping signal generating circuit NO5 is connected to the input signal S4P, and an N terminal output of the fifth non-overlapping signal generating circuit NO5 is connected to the twenty-first switch S₂₁A P terminal output of the fifth non-overlapping signal generating circuit NO5 is connected to an input terminal of the third demultiplexer DEMUX3, an input terminal of the sixth non-overlapping signal generating circuit NO6 is connected to the input signal S4N, and an N terminal output of the sixth non-overlapping signal generating circuit NO6 is connected to the twenty-second switch S₂₂A P terminal output of the sixth non-overlapping signal generating circuit NO6 is connected to an input terminal of a fourth demultiplexer DEMUX4, selection terminals of the third demultiplexer DEMUX3 and the fourth demultiplexer DEMUX4 are connected to the input signal SM4 and the input signal SM5, and a third demultiplexer selectsThe A terminal output of the DEMUX3 is connected to the twentieth switch S₂₃A B terminal of the third demultiplexer DEMUX3 is connected to a twenty-fifth switch S₂₅C-terminal output of the third demultiplexer DEMUX3 is connected to the twenty-seventh switch S₂₇A D terminal of the third demultiplexer DEMUX3 is connected to a twenty-ninth switch S₂₉A terminal a of the fourth demultiplexer DEMUX4 is connected to the twenty-fourth switch S₂₄A B terminal of the fourth demultiplexer DEMUX4 is connected to a twenty-sixth switch S₂₆C terminal of the fourth demultiplexer DEMUX4 is connected to the twenty-eighth switch S₂₈A D terminal of the fourth demultiplexer DEMUX4 is connected to a thirtieth switch S₃₀The control terminal of (1).

3. The multi-source energy harvesting system of claim 1, wherein: the fixed-time on comparator comprises a second OR gate₂Four-bit counter, fourth inverter INV₄NAND gates of the second to fifth₂~ NAND₅NOR, second NOR gate₃NOR, third NOR gate₃A latch comparator;

4. The multi-source energy harvesting system of claim 1, wherein: the sample-and-hold comparator comprises a fifth demultiplexer DEMUX₅And a forty-fourth switch S₄₄Forty-fifth switch S₄₅An eleventh capacitor C₁₁And a twelfth capacitor C₁₂A second comparator COMP₂First to fourth D flip-flops DFF₁~DFF₄First to fifth DELAY units DELAY₁~ DELAY₅AND AND gates of twelfth to fourteenth₁₂~ AND₁₄XOR of the first XOR gate₁First XNOR gate₁NOR, fourth NOR gate₄The fifth inverter INV₅；

The fifth demultiplexer DEMUX₅Is connected with the input signal PULSE_SHFifth demultiplexer DEMUX₅Is connected to the forty-fifth switch S₄₅And the first exclusive or gate XOR₁An input terminal of the fifth demultiplexer DEMUX₅Is connected to the fourteenth switch S₄₄And the first exclusive or gate XOR₁To the other of the input terminals of the first,fourteenth switch S₄₄Is connected to an input voltage V_OUTThe fourteenth switch S₄₄Is connected to an eleventh capacitor C at the other end₁₁And a second comparator COMP₂Negative phase input terminal of (1), the forty-fifth switch S₄₅Is connected to an input voltage V_OUTForty-fifth switch S₄₅Is connected to a twelfth capacitor C₁₂And a second comparator COMP₂A non-inverting input terminal of (1), a second comparator COMP₂Is connected to a first xor gate XNOR₁A first exclusive nor gate XNOR₁Is connected to the third D flip-flop DFF₃D input terminal of (1), first exclusive or gate XOR₁Is connected to the first DELAY unit DELAY₁The first DELAY unit DELAY₁Is connected to a second comparator COMP₂Enable terminal and second DELAY unit DELAY₂Input terminal of the second DELAY unit DELAY₂Is connected to the third DELAY unit DELAY₃Input terminal of, twelfth AND gate AND₁₂And a fifth inverter INV₅Input terminal of, the third DELAY unit DELAY₃Is connected to the fourth DELAY unit DELAY₄AND a thirteenth AND gate AND₁₃An input terminal of the fourth DELAY unit DELAY₄Is connected to the second D flip-flop DFF₂CLK terminal of, fifth inverter INV₅Is connected to the first D flip-flop DFF₁CLK input terminal of, the first D flip-flop DFF₁Is connected to a first D flip-flop DFF₁D input terminal, fifth demultiplexer DEMUX₅And a first exclusive nor gate XNOR₁Said second D flip-flop DFF₂D input terminal of the second D flip-flop DFF is connected with a power supply VDD₂Is connected to the twelfth AND gate AND₁₂AND a thirteenth AND gate AND₁₃AND a twelfth AND gate AND₁₂Is connected to the third D flip-flop DFF₃CLK input terminal of, thirteenth AND gate AND₁₃Output signal PULSE_MPPTSaid fourth NOR gate NOR₄The input end of the input end is connected with an input signal CRT and an input signal FCT; NOR of fourth NOR gate₄Is connected to the fourth D flip-flop DFF₄CLK input terminal of, a fourth D flip-flop DFF₄D input terminal of the D flip-flop is connected with a power supply VDD and a fourth D flip-flop DFF₄QB output terminal of the first AND gate is connected to the fourteenth AND gate AND₁₄And a fifth DELAY unit DELAY₅Of the fifth DELAY unit DELAY₅Is connected to the fourth D flip-flop DFF₄The fourteenth AND gate AND₁₄And a second D flip-flop DFF₂CLR of (1) terminates the input signal EN_ARFourteenth AND gate AND₁₄Is connected to the third D flip-flop DFF₃The CLR terminal of (1).

5. The multi-source energy harvesting system of claim 1, wherein: the digital control oscillator comprises zeroth to second PMOS tubes M₀~M₂And the third to fifth NMOS transistors M₃~M₅First to fifth oscillation units, sixth to eighth inverters INV₆~ INV₈；

The oscillation unit comprises sixth to eleventh PMOS tubes M₆~M₁₁And twelfth to seventeenth NMOS transistors M₁₂~M₁₇And ninth to twelfth inverters INV₉~ INV₁₂Thirteenth to sixteenth capacitors C₁₃~C₁₆；

The sixth PMOS tube M₆Is connected to a power supply VDD, and a sixth PMOS transistor M₆Is connected to a seventh PMOS transistor M₇Source electrode of (1), sixth PMOS transistor M₆Is connected to the thirteenth NMOS transistor M₁₃And the grid of the transistor is used as the input end of the oscillation unit, and the seventh PMOS tube M₇Is connected to the twelfth NMOS tube M₁₂Drain electrode of the PMOS transistor, eighth PMOS transistor M to eleventh PMOS transistor M₈~M₁₁Source electrode and fourteenth to seventeenth NMOS transistor M₁₄~M₁₇And the drain electrode of the transistor is used as the output end of the oscillation unit, and a seventh PMOS tube M₇Is connected to the gate ofZeroth PMOS tube M₀The twelfth NMOS tube M₁₂Is connected to the thirteenth NMOS transistor M₁₃The twelfth NMOS tube M₁₂Is connected to the fourth NMOS transistor M₄Grid of (1), thirteenth NMOS tube M₁₃Is connected to ground, an eighth PMOS transistor M in the oscillation unit₈Gate of (2) and ninth inverter INV₉Is connected to an input signal FC_D3Ninth inverter INV₉Is connected to the fourteenth NMOS transistor M₁₄A ninth PMOS transistor M in the oscillation unit₉Gate of (1) and tenth inverter INV₁₀Is connected to an input signal FC_D2The tenth inverter INV₁₀Is connected to the fifteenth NMOS transistor M₁₅Grid of (1), tenth PMOS tube M in oscillation unit₁₀Gate of (1) and an eleventh inverter INV₁₁Is connected to an input signal FC_D1Eleventh inverter INV₁₁Is connected to the sixteenth NMOS transistor M₁₆Grid of (1), eleventh PMOS tube M in oscillation unit₁₁Gate of (1) and twelfth inverter INV₁₂Is connected to an input signal FC_D0Twelfth inverter INV₁₂Is connected to the seventeenth NMOS transistor M₁₇The eighth PMOS transistor M₈Drain electrode of (1) and fourteenth NMOS tube M₁₄Is connected to a thirteenth capacitor C₁₃Upper plate of, a thirteenth capacitor C₁₃The lower polar plate is connected to the ground wire, and a ninth PMOS tube M₉Drain electrode of (1) and a fifteenth NMOS tube M₁₅Is connected to a fourteenth capacitor C₁₄Upper plate of (2), fourteenth capacitance C₁₄The lower polar plate is connected to the ground wire, and a tenth PMOS tube M₁₀Drain electrode of (1) and sixteenth NMOS transistor M₁₆Is connected to a fifteenth capacitor C₁₅Upper plate of, a fifteenth capacitor C₁₅The lower polar plate is connected to the ground wire, and an eleventh PMOS tube M₁₁Drain electrode of (1) and seventeenth NMOS transistor M₁₇Is connected to a sixteenth capacitor C₁₆Upper plate of, sixteenth capacitor C₁₆The lower polar plate is connected to the ground wire, and a zeroth PMOS tube M₀Is connected to a power supply VDD, and a zeroth PMOS transistor M₀Is connected to the drain electrodeTo zero PMOS tube M₀Grid and first PMOS transistor M₁Source electrode of (1), first PMOS transistor M₁Is connected to the first PMOS transistor M₁Grid electrode of and a third NMOS tube M₃Drain electrode of (1) and third NMOS transistor M₃The third NMOS transistor M₃Is connected to the fourth NMOS transistor M₄Drain electrode of (1) and fourth NMOS transistor M₄The fourth NMOS transistor M₄Is connected to a ground line, an output terminal of the first oscillating unit is connected to an input terminal of the second oscillating unit, an output terminal of the second oscillating unit is connected to an input terminal of the third oscillating unit, an output terminal of the third oscillating unit is connected to an input terminal of the fourth oscillating unit, an output terminal of the fourth oscillating unit is connected to an input terminal of the fifth oscillating unit, and an output terminal of the fifth oscillating unit is connected to a seventh inverter INV₇Input end of and a second PMOS tube M₂Source electrode of (1) and fifth NMOS transistor M₅Drain electrode of, seventh inverter INV₇Is connected to the eighth inverter INV₈The eighth inverter INV₈Output terminal of the second PMOS transistor M outputs a CLK signal₂Drain electrode of (1) and fifth NMOS transistor M₅Is connected to the input terminal of the first oscillation unit, and a second PMOS transistor M₂Gate of (1) and sixth inverter INV₆Is connected with the input signal EN, a sixth inverter INV₆Is connected to the fifth NMOS transistor M₅A gate electrode of (1).

6. The multi-source energy harvesting system of claim 1, wherein: the MPPT mode control circuit comprises first to third counters, thirteenth to fifteenth inverters INV₁₃~ INV₁₅And the fifth to seventh D flip-flops DFF₅~DFF₇And sixth to eighth DELAY units DELAY₆~ DELAY₈Fifteenth AND gate AND₁₅Sixteenth AND gate AND₁₆A first three-input OR gate 3OR₁NOR of fifth NOR gate₅；

The input end of the first counter is connected with an input signal EON_PVThe output end of the first counter is connected to a first three-input OR gate 3OR₁One ofAn input terminal, an input terminal of the second counter is connected with the input signal EON_TEGThe output end of the second counter is connected to the first three-input OR gate 3OR₁The input of the third counter is connected with the input signal EON_RFThe output end of the third counter is connected to the first three-input OR gate 3OR₁A first three-input OR gate 3OR₁Is connected to the thirteenth inverter INV₁₃Input terminal of, a thirteenth inverter INV₁₃Is connected to the output of the fifth NOR gate NOR₅An input terminal of the fifth NOR gate NOR₅Is connected to the fifth D flip-flop DFF₅CLK input terminal of, a fifth D flip-flop DFF₅The D input end of the D flip-flop is connected with a power supply VDD and a fifth D flip-flop DFF₅Is connected to the sixth DELAY unit DELAY₆Input terminal of, the sixth DELAY unit DELAY₆Is connected to the fourteenth inverter INV₁₄An input terminal of (1); the fourteenth inverter INV₁₄Is connected to the sixth D flip-flop DFF₆CLK input terminal of (1), sixth D flip-flop DFF₆The D input end of the D flip-flop is connected with a power supply VDD and a sixth D flip-flop DFF₆Is connected to the fifth NOR gate NOR₅The fifteenth inverter INV₁₅Is connected with the input signal MODE_CHANGEFifteenth inverter INV₁₅Is connected to a seventh D flip-flop DFF₇CLK input terminal of, a seventh D flip-flop DFF₇The D input end of the D flip-flop is connected with a power supply VDD and a seventh D flip-flop DFF₅QB output terminal of the first AND gate is connected to the fifteenth AND gate₁₅One input terminal of, the sixteenth AND gate AND₁₆And a seventh DELAY unit DELAY₇An input terminal of (1); seventh DELAY cell DELAY₇Is connected to the eighth DELAY unit DELAY₈The eighth DELAY unit DELAY₈Is connected to a seventh D flip-flop DFF₇CLR input terminal, fifteenth AND gate AND₁₅AND a sixteenth AND gate AND₁₆And the other input of which is connected to the input signal RESETN.

7. The multi-source energy harvesting system of claim 1, wherein: the MPPT control circuit of the reconfigurable charge pump comprises seventeenth to twenty fifth AND gates AND₁₇~ AND₂₅Second to seventh 4-bit reversible counters₂~ Counter₇First to eighth third input selectors MUX₁~MUX₈；

The seventeenth AND gate AND₁₇One input terminal of, eighteenth AND gate AND₁₈AND a nineteenth AND gate AND₁₉One input end of the first AND gate is connected with the input signal CRT, the twentieth AND gate₂₀One input terminal of, the twenty-first AND gate AND₂₁AND a twenty-second AND gate AND₂₂One input terminal of (2) is connected with input signal PULSE_MPPTTwenty third AND gate AND₂₃One input terminal of, the twenty-fourth AND gate AND₂₄AND a twenty-fifth AND gate AND₂₅One input terminal of the first AND second switches is connected with the input signal FCT, AND a seventeenth AND gate₁₇Another input terminal of (1), a twentieth AND gate AND₂₀AND the twenty-third AND gate AND₂₃Is connected to the input signal EON_PVThe first to eighth third input selectors MUX₁~MUX₈S of₃Input terminal, eighteenth AND gate AND₁₈AND twenty-first AND gate AND₂₁AND the twenty-fourth AND gate AND₂₄Is connected to the input signal EON_TEGThe first to eighth third input selectors MUX₁~MUX₈S of₂Input terminal, nineteenth AND gate AND₁₉AND a twenty-second AND gate AND₂₂Another input terminal of (1), twenty-fifth AND gate AND₂₅Is connected to the input signal EON_RFThe first to eighth third input selectors MUX₁~MUX₈S of₁Input terminal, seventeenth AND gate AND₁₇Is connected to a second 4-bit up-down Counter₂End EN of, eighteenth AND gate AND₁₈Is connected to the third 4-bit reversible countCounter₃End EN of, nineteenth AND gate AND₁₉Is connected to a fourth 4-bit up-down Counter₄EN terminal, twentieth AND gate AND₂₀Is connected to a second 4-bit up-down Counter₂CLK terminal and fifth 4-bit up/down Counter₅The CLK terminal of, the twenty-first AND gate AND₂₁Is connected to a third 4-bit up-down Counter₃CLK terminal and a sixth 4-bit up/down Counter₆CLK terminal of, twenty-second AND gate AND₂₂Is connected to a fourth 4-bit up-down Counter₄CLK terminal and seventh 4-bit up/down Counter₇CLK terminal, twenty-third AND gate AND₂₃Is connected to a fifth 4-bit up-down Counter₅End EN of, twenty-fourth AND gate AND₂₄Is connected to a sixth 4-bit up-down Counter₆EN terminal of, twenty-fifth AND gate AND₂₅Is connected to a seventh 4-bit up-down Counter₇The EN terminal of (1), the second to seventh 4-bit reversible counters₂~ Counter₇The UD input terminal receives the input signal UD, and a second 4-bit reversible Counter₂D of (A)₃The output terminal is connected to the first three-input selector MUX₁IN of₃Input terminal, second 4-bit reversible Counter₂D of (A)₂The output terminal is connected to a second three-input selector MUX₂IN of₃Input terminal, second 4-bit reversible Counter₂D of (A)₁The output terminal is connected to a third three-input selector MUX₃IN of₃Input terminal, second 4-bit reversible Counter₂D of (A)₀The output terminal is connected to a fourth three-input selector MUX₄IN of₃Input terminal, third 4-bit reversible Counter₃D of (A)₃The output terminal is connected to the first three-input selector MUX₁IN of₂Input terminal, third 4-bit reversible Counter₃D of (A)₂The output terminal is connected to a second three-input selector MUX₂IN of₂Input terminal, third 4-bit reversible Counter₃D of (A)₁The output terminal is connected to the third three-input selectionMUX₃IN of₂Input terminal, third 4-bit reversible Counter₃D of (A)₀The output terminal is connected to a fourth three-input selector MUX₄IN of₂Input terminal, fourth 4-bit reversible Counter₄D of (A)₃The output terminal is connected to the first three-input selector MUX₁IN of₁Input terminal, fourth 4-bit reversible Counter₄D of (A)₂The output terminal is connected to a second three-input selector MUX₂IN of₁Input terminal, fourth 4-bit reversible Counter₄D of (A)₁The output terminal is connected to a third three-input selector MUX₃IN of₁Input terminal, fourth 4-bit reversible Counter₄D of (A)₀The output terminal is connected to a fourth three-input selector MUX₄IN of₁Input terminal, fifth 4-bit reversible Counter₅D of (A)₃The output terminal is connected to a fifth third input selector MUX₅IN of₃Input terminal, fifth 4-bit reversible Counter₅D of (A)₂The output terminal is connected to a sixth third input selector MUX₆IN of₃Input terminal, fifth 4-bit reversible Counter₅D of (A)₁The output terminal is connected to a seventh third input selector MUX₇IN of₃Input terminal, fifth 4-bit reversible Counter₅D of (A)₀The output terminal is connected to an eighth third input selector MUX₈IN of₃Input terminal, sixth 4-bit reversible Counter₆D of (A)₃The output terminal is connected to a fifth third input selector MUX₅IN of₂Input terminal, sixth 4-bit reversible Counter₆D of (A)₂The output terminal is connected to a sixth third input selector MUX₆IN of₂Input terminal, sixth 4-bit reversible Counter₆D of (A)₁The output terminal is connected to a seventh third input selector MUX₇IN of₂Input terminal, sixth 4-bit reversible Counter₆D of (A)₀The output terminal is connected to an eighth third input selector MUX₈IN of₂Input terminal, seventh 4-bit reversible Counter₇D of (A)₃The output terminal is connected to a fifth third input selector MUX₅IN of₁Input terminal, seventh 4-bit reversible Counter₇D of (A)₂The output terminal is connected to a sixth third input selector MUX₆IN of₁Input terminal, seventh 4-bit reversible Counter₇D of (A)₁The output terminal is connected to a seventh third input selector MUX₇The seventh 4-bit up/down Counter at the input of IN1₇D of (A)₀The output terminal is connected to an eighth third input selector MUX₈IN1 input terminal, first three-input selector MUX₁Output signal CR of OUT output terminal_D3Second three-input selector MUX₂Output signal CR of OUT output terminal_D2Third three-input selector MUX₃Output signal CR of OUT output terminal_D1Fourth three input selector MUX₄Output signal CR of OUT output terminal_D0Fifth three input selector MUX₅Output signal FC of OUT output terminal_D3Sixth three-input selector MUX₆Output signal FC of OUT output terminal_D2Seventh three-input selector MUX₇Output signal FC of OUT output terminal_D1Eighth third input selector MUX₈Output signal FC of OUT output terminal_D0。

8. The multi-source energy harvesting system of claim 1, wherein: the charge pump CR control circuit includes first to seventy-sixth input selectors 4BIT _ MUX₁~4BIT_MUX₇；

The first to seventy-sixth input selectors 4BIT _ MUX₁~4BIT_MUX₇S of₃The input end is connected with an input signal CR_D3First to seventy-sixth input selectors 4BIT _ MUX₁~4BIT_MUX₇S of₂The input end is connected with an input signal CR_D2First to seventy-sixth input selectors 4BIT _ MUX₁~4BIT_MUX₇S of₁The input end is connected with an input signal CR_D1First to seventy-sixth input selectors 4BIT _ MUX₁~4BIT_MUX₇S of₀The input end is connected with an input signal CR_D0(ii) a The first sixteen-input selector 4BIT _ MUX₁IN of₀~IN₁₅The input terminal is sequentially connected with "0", "1", "0" and "0", and the first sixteen input selector 4BIT _ MUX₁Output terminal of the second multiplexer 4BIT _ MUX, and an OUT output terminal of the second multiplexer SM1₂IN of₀~IN₁₅The input end is sequentially connected with ' 0 ', ' 1 ', ' 0 ', and ' twenty-sixth input selector 4BIT _ MUX₂Output terminal of the signal SM2, thirty-sixth input selector 4BIT _ MUX₃IN of₀~IN₁₅The input terminal is sequentially connected with '0', '1', '0', and the thirty-sixth input selector 4BIT _ MUX₃Output terminal of the signal SM3, and a forty-sixth input selector 4BIT _ MUX₄IN of₀~IN₁₅The input end is sequentially connected with '1', '0', '1', '0', '1', '0' and '0', a forty-sixth input selector 4BIT _ MUX₄OUT output terminal of SM4, fifty-sixth input selector 4BIT _ MUX₅IN of₀~IN₁₅The input end is sequentially connected with '1', '0', '1', '0', and '0', a fifty-sixth input selector 4BIT _ MUX₅OUT output terminal of SM5, sixty-sixth input selector 4BIT _ MUX₆IN of₀~IN₁₅The input terminal is sequentially connected with '1', '0', and the sixty-sixth input selector 4BIT _ MUX₆OUT output terminal of SM6, seventy-sixth input selector 4BIT _ MUX₇IN of₀~IN₁₅The input terminal is sequentially connected with '0', '1', '0', and '0', a seventy-sixth input selector 4BIT _ MUX₇Outputs the signal SM 7.

9. A method of controlling the multi-source energy harvesting system of claim 1, wherein: the method comprises the following steps:

1b) when the voltage of the upper plate of the storage capacitor of the photoelectric, thermoelectric and radio frequency energy is greater than the threshold voltage V_XGenerates a corresponding request signal REQ_PV、REQ_TEGOr REQ_RFThe arbitration circuit generates a response signal EON according to the priority and latency of the request signal_PVOr EON_TEGOr EON_RF，EON_XThe signal makes the reconfigurable charge pump MPPT control circuit output corresponding CR_D[3:0]X and FC_D[3:0]_X；

1c）CR_D[3:0]The _Xis input into a charge pump CR control circuit to output corresponding SM 1-SM 7 signals to control the voltage conversion rate of the charge pump; FC_D[3:0]The signal-X adjusts the frequency of the output clock of the digitally controlled oscillator to control the switching frequency of the charge pump, while the EON is set_XThe corresponding switch can be opened to connect the buffer capacitor to the input end of the charge;

2d) at each T_ONThe 15 th CLK in a cycle_COTDuring clock, the COT output voltage control circuit generates a PULSE signal PULSE_SHClock driving for the subsequent sampling comparison circuit;

3b) when the sample-hold comparator makes a judgment on the level value of UD, a PULSE signal PULSE is output_MPPTTime for reconfigurable charge pump MPPT control circuitDriving a clock;

(4) MPPT mode control circuit for arbitrating circuit response signal EON for each energy_XCounting the response times;

4b) in PULSE_MPPTWhen the rising edge comes, if the UD signal is high level, CR is performed_D[3:0]The lowest order bit is decremented by one, and then waits for the next PULSE_MPPTA rising edge; if the UD signal is low, CR_D[3:0]The lowest order bit is incremented by one, and then CR is set_D[3:0]Is saved to CR_D[3:0]In _X, output MODE_CHANGEA signal ends the regulation of the charge pump CR and starts the regulation of the switching frequency of the charge pump;

4c) in PULSE_MPPTWhen the rising edge comes, if the UD signal is at high level, FC_D[3:0]The lowest order bit is decremented by one, and then waits for the next PULSE_MPPTA rising edge; FC if the UD signal is low_D[3:0]Adding one to the lowest order and then FC_D[3:0]The value of (A) is stored in FC_D[3:0]In _X, output MODE_CHANGEAnd setting the FCT signal to be low level, and finishing the adjustment of the switching frequency of the charge pump.

10. The method of claim 9, wherein the method further comprises: x represents one of PV, TEG or RF.