CN108932438A

CN108932438A - The restructural PUF element circuit of multimodal fusion based on linear feedback

Info

Publication number: CN108932438A
Application number: CN201810674296.3A
Authority: CN
Inventors: 张跃军; 栾志存; 王佳伟; 潘钊
Original assignee: Ningbo University
Current assignee: Ningbo University
Priority date: 2018-06-27
Filing date: 2018-06-27
Publication date: 2018-12-04
Anticipated expiration: 2038-06-27
Also published as: CN108932438B

Abstract

The invention discloses a kind of restructural PUF element circuits of multimodal fusion based on linear feedback, including storage-type stochastic source, linear feedback shift register, string turns and module and moderator PUF, the clock end and string of linear feedback shift register turn and the equal incoming clock signal of clock end of module, the input terminal of moderator PUF accesses input signal, the output end of moderator PUF is for exporting PUF output response, 8 parallel-by-bit output ends of storage-type stochastic source and 8 parallel-by-bit input terminals of linear feedback shift register connect one to one, the serial output terminal of linear feedback shift register turns with string and the serial input terminal of module connects, string turns and 16 parallel-by-bit output ends of module and the 16 parallel-by-bit control terminals of moderator PUF connect one to one, storage-type stochastic source includes that identical eight storages of structure are single Member；Advantage is that randomness is higher, realizes the continuous output of key.

Description

The restructural PUF element circuit of multimodal fusion based on linear feedback

Technical field

The present invention relates to a kind of PUF element circuits, restructural more particularly, to a kind of multimodal fusion based on linear feedback PUF element circuit.

Background technique

With the arriving of digital age, smart home, intelligent interconnection and number rely on general in daily life Store-through exists.Smart machine becomes the carrier of intelligent use, smart machine using more and more common, saved on these smart machines Many personal private informations, the security breaches of smart machine cause personal and social risk.The security breaches master of smart machine If hardware identification key safety is low between smart machine, it is easy to be counted by way of collecting a large amount of keys by attacker Modeling is learned, realizes modeling attack.Therefore, the randomness of key and safety become being critical to for hardware identification between smart machine Element.

Physics unclonable function circuit be generated using random process deviation present in ic manufacturing process with Machine sequence can be used to generate high randomness key.Due to the uncontrollable characteristic of process deviation, structure and working environment are all the same PUF circuit, different responses can be exported in different chips.The key of PUF circuit evolving ideally has height Uniqueness, reliability and randomness, and it is very sensitive to manufacturing process change of error.Physics unclonable function electricity as a result, Road is a kind of important information security field hardware identification technology, and the key that physics unclonable function circuit generates can answer extensively For fields such as smart machine certification, automobile burglar, logistic track and anti-counterfeiting marks, information security threats are prevented.Physics not The realization technical aspect of functional circuit can be cloned, Kumar etc. keeps electric current identical at two using the characteristic of non-linear current mirror It is propagated in non-linear current mirror chain, realizes current type PUF element circuit.But in current type PUF element circuit, due to electricity The input and output non complete symmetry of mirror is flowed, so that electric current output is influenced by channel modulation effect, leads to circuit output data Unevenly, randomness is not high.Kim etc. utilizes resistance-type RAM, devises a kind of nonlinear resistor type PUF element circuit, but should Nonlinear resistor type PUF element circuit is since resistance-type RAM internal current-voltage is not non-linear high and circuit is to process deviation It is insensitive, cause randomness undesirable.

Summary of the invention

Technical problem to be solved by the invention is to provide a kind of higher multimodal fusions based on linear feedback of randomness Restructural PUF element circuit.

The technical scheme of the invention to solve the technical problem is: a kind of multimodal fusion based on linear feedback can PUF element circuit is reconstructed, including storage-type stochastic source, linear feedback shift register, string turn simultaneously module and moderator PUF, institute The storage-type stochastic source stated has control terminal, enable end and 8 parallel-by-bit output ends；The linear feedback shift register has 8 parallel-by-bit input terminals, clear terminal, set several ends and clock end at serial output terminal；The string turns and module has serial input End, clock end and 16 parallel-by-bit output ends；The moderator PUF has input terminal, 16 parallel-by-bit control terminals and output end；Institute The control terminal for the storage-type stochastic source stated is for accessing word line control signal, and the enable end of the storage-type stochastic source is for connecing Enter enable signal, the clear terminal of the linear feedback shift register is moved for accessing reset signal, the linear feedback Bit register set several ends for access set several signals, the clock end of the linear feedback shift register and the string turn And the equal incoming clock signal of clock end of module, the input terminal of the moderator PUF access input signal, the moderator The output end of PUF is for exporting PUF output response, 8 parallel-by-bit output ends of the storage-type stochastic source and described linear 8 parallel-by-bit input terminals of feedback shift register connect one to one, the Serial output of the linear feedback shift register End and the described string turn and the serial input terminal of module connect, the string turn simultaneously 16 parallel-by-bit output ends of module and described The 16 parallel-by-bit control terminals of moderator PUF connect one to one；The storage-type stochastic source includes identical eight, structure and deposits Storage unit, each storage unit are respectively provided with control terminal, enable end and output end, the control of storage unit described in eight End connection processed and its connecting pin are the control terminal of the storage-type stochastic source, the enable end connection of storage unit described in eight And its connecting pin is the enable end of the storage-type stochastic source, the output end of storage unit described in m-th is described deposits M, m=1 of 8 parallel-by-bit output ends of storage type stochastic source, 2 ..., 8；The storage unit includes the first PMOS tube, the Two PMOS tube, third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the first NMOS tube, the second NMOS tube, Three NMOS tubes, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube, One or two input nand gates, the two or two input nand gate and the first phase inverter；One or two input nand gate and described Two or two input nand gates are respectively provided with first input end, the second input terminal and output end, the source electrode of first PMOS tube, institute The source electrode for the second PMOS tube stated, the source electrode of the third PMOS tube, the source electrode of the 4th PMOS tube, the described the 5th The source electrode of PMOS tube and the source electrode of the 6th PMOS tube access power supply, the grid of first PMOS tube, described The drain electrode of second PMOS tube, the drain electrode of second NMOS tube, the grid of the third NMOS tube and the described the 4th The drain electrode of NMOS tube connects, the drain electrode of first PMOS tube, the grid of second PMOS tube, the first NMOS The drain electrode of pipe, the drain electrode of the third NMOS tube are connected with the grid of the 4th NMOS tube, first NMOS tube Grid connected with the grid of second NMOS tube and its connecting pin is the control terminal of the storage unit, described the The source electrode of one NMOS tube is connected with the grid of the 7th NMOS tube, the source electrode of second NMOS tube and the described the 8th The grid of NMOS tube connects, and the source grounding of the source electrode of the third NMOS tube and the 4th NMOS tube is described The grid of third PMOS tube, the 6th PMOS tube grid connected with the grid of the 9th NMOS tube and its connecting pin It is the drain electrode of the third PMOS tube, the drain electrode of the 4th PMOS tube, described for the enable end of the storage unit The grid of 5th PMOS tube, the drain electrode of the 5th NMOS tube, the 6th NMOS tube grid and the described the 1st The first input end of input nand gate connects, the drain electrode, described of the grid of the 4th PMOS tube, the 5th PMOS tube The drain electrode of the 6th PMOS tube, the 5th NMOS tube grid, the 6th NMOS tube drain electrode and described second Second input terminal of two input nand gates connects, and the source electrode of the 5th NMOS tube and the drain electrode of the 7th NMOS tube connect It connecing, the source electrode of the 6th NMOS tube is connected with the drain electrode of the 8th NMOS tube, the source electrode of the 7th NMOS tube, The source electrode of 8th NMOS tube is connected with the drain electrode of the 9th NMOS tube, and the source electrode of the 9th NMOS tube connects Second input terminal on ground, the one or two input nand gate is connected with the output end of the two or two input nand gate, institute The output end for the one or two input nand gate stated, the first input end of the two or two input nand gate and described first are anti- The input terminal of phase device connects, and the output end of first phase inverter is the output end of the storage unit.

The linear feedback shift register includes the first data selector, the second data selector, the choosing of third data Select device, the 4th data selector, the 5th data selector, the 6th data selector, the one or two input XOR gate, the first D triggering Device, the second d type flip flop, third d type flip flop, four d flip-flop, the 5th d type flip flop, the 6th d type flip flop, the 7th d type flip flop, Eight d type flip flops, the 9th d type flip flop, the tenth d type flip flop, the 11st d type flip flop, the tenth 2-D trigger, the tenth 3d flip-flop, Tenth four d flip-flop, the 15th d type flip flop and the 16th d type flip flop, first data selector, second number It is four input data selectors according to selector, the third data selector and the 4th data selector, it is described The first data selector, second data selector, the third data selector and the choosing of described 4th data It selects device and is respectively provided with first input end, the second input terminal, third input terminal, the 4th input terminal, the first control terminal, the second control terminal And output end, the 5th data selector and the 6th data selector are two input data selectors, described The 5th data selector and the 6th data selector be respectively provided with first input end, the second input terminal, control terminal and Output end, the one or the two input XOR gate have first input end, the second input terminal and output end, the first D touching Send out device, second d type flip flop, the third d type flip flop, the four d flip-flop, the 5th d type flip flop, It is 6th d type flip flop, the 7th d type flip flop, the 8th d type flip flop, the 9th d type flip flop, described The tenth d type flip flop, the 11st d type flip flop, the tenth 2-D trigger, the tenth 3d flip-flop, institute The tenth four d flip-flop, the 15th d type flip flop and the 16th d type flip flop stated are respectively provided with input terminal, clock It holds, set several ends, clear terminal, output end and reversed-phase output, the clock end of first d type flip flop, the 2nd D triggering The clock end of device, the clock end of the third d type flip flop, the clock end of the four d flip-flop, the 5th D touching Send out clock end, the clock end of the 6th d type flip flop, the clock end of the 7th d type flip flop, the 8th D of device The clock end of trigger, the clock end of the 9th d type flip flop, the clock end of the tenth d type flip flop, the described the tenth The clock end of one d type flip flop, the clock end of the tenth 2-D trigger, the clock end of the tenth 3d flip-flop, institute The clock end for the tenth four d flip-flop stated, the clock end of the 15th d type flip flop and the 16th d type flip flop Clock end connection and its connecting pin are the clock end of the linear feedback shift register；First d type flip flop is set Number ends, the clear terminal of second d type flip flop, the third d type flip flop set several ends, the four d flip-flop Set several ends, the clear terminal of the 5th d type flip flop, the 6th d type flip flop set several ends, the 7th d type flip flop Clear terminal, the 8th d type flip flop set several ends, the clear terminal of the 9th d type flip flop, described tenth D triggering Device set several ends, the 11st d type flip flop sets several ends, the clear terminal of the tenth 2-D trigger, the described the tenth The clear terminal of 3d flip-flop, the tenth four d flip-flop clear terminal, the 15th d type flip flop set several ends and described The 16th d type flip flop clear terminal connection and its connecting pin be that the linear feedback shift register sets several ends；It is described The clear terminal of the first d type flip flop, second d type flip flop set several ends, the clear terminal of the third d type flip flop, institute The clear terminal for the four d flip-flop stated, the 5th d type flip flop set several ends, the 6th d type flip flop clear terminal, 7th d type flip flop set several ends, the clear terminal of the 8th d type flip flop, the 9th d type flip flop set number End, the clear terminal of the tenth d type flip flop, the clear terminal of the 11st d type flip flop, the tenth 2-D trigger Set several ends, the tenth 3d flip-flop set several ends, the tenth four d flip-flop sets several ends, the described the 15th The clear terminal of d type flip flop and the 16th d type flip flop set that several ends connect and its connecting pin is that the linear feedback is moved The clear terminal of bit register；The first input end of first data selector, first d type flip flop output end and The input terminal of second d type flip flop connects, the second input terminal of first data selector, the 2nd D touching The output end of hair device is connected with the input terminal of the third d type flip flop, the third input terminal of first data selector, The output end of the third d type flip flop is connected with the input terminal of the four d flip-flop, first data selector The 4th input terminal, the four d flip-flop output end connected with the input terminal of the 5th d type flip flop, it is described The input of the first input end of second data selector, the output end of the 5th d type flip flop and the 6th d type flip flop End connection, the output end and the described the 7th of the second input terminal of second data selector, the 6th d type flip flop The input terminal of d type flip flop connects, the output of the third input terminal of second data selector, the 7th d type flip flop End is connected with the input terminal of the 8th d type flip flop, the 4th input terminal of second data selector, the described the 8th The output end of d type flip flop is connected with the input terminal of the 9th d type flip flop, the first input of the third data selector It holds, the output end of the 9th d type flip flop is connected with the input terminal of the tenth d type flip flop, the third data choosing The output end of the second input terminal, the tenth d type flip flop of selecting device is connected with the input terminal of the 11st d type flip flop, The third input terminal of the third data selector, the output end of the 11st d type flip flop and the 12nd D touching Send out the input terminal connection of device, the output end of the 4th input terminal of the third data selector, the tenth 2-D trigger It is connected with the input terminal of the tenth 3d flip-flop, the first input end of the 4th data selector, the described the tenth The output end of 3d flip-flop is connected with the input terminal of the tenth four d flip-flop, and the second of the 4th data selector Input terminal, the tenth four d flip-flop output end connected with the input terminal of the 15th d type flip flop, described The third input terminal of four data selectors, the output end of the 15th d type flip flop and the 16th d type flip flop it is defeated Enter end connection, the 4th input terminal of the 4th data selector connected with the output end of the 16th d type flip flop and Its connecting pin be the linear feedback shift register serial output terminal, the output end of first data selector and The first input end of 5th data selector connects, the output end of second data selector and the described the 5th Second input terminal of data selector connects, the output end of the third data selector and the 6th data selector First input end connection, the second input of the output end of the 4th data selector and the 6th data selector End connection, the output end of the 5th data selector are connected with the first input end of the one or the two input XOR gate, The output end of 6th data selector is connected with the second input terminal of described one or the two input XOR gate, and described the The output end of one or two input XOR gates is connected with the input terminal of first d type flip flop, first data selector First control terminal is the 1st of 8 parallel-by-bit input terminals of the linear feedback shift register, the first data selection Second control terminal of device is the 2nd of 8 parallel-by-bit input terminals of the linear feedback shift register, second data First control terminal of selector is the 3rd of 8 parallel-by-bit input terminals of the linear feedback shift register, described second Second control terminal of data selector is the 4th of 8 parallel-by-bit input terminals of the linear feedback shift register, described First control terminal of third data selector is the 5th of 8 parallel-by-bit input terminals of the linear feedback shift register, institute Second control terminal of the third data selector stated is the 6 of 8 parallel-by-bit input terminals of the linear feedback shift register Position, the connecting pin of the control terminal of the first control terminal and the 5th data selector of the 4th data selector is institute The 7th of 8 parallel-by-bit input terminals of the linear feedback shift register stated, the second control terminal of the 4th data selector Connecting pin with the control terminal of the 6th data selector is that 8 parallel-by-bits of the linear feedback shift register input The 8th of end.In the circuit structure of the linear feedback shift register, feedback path be it is randomly selected, the first d type flip flop~ 16th d type flip flop is the d type flip flop that band sets several ends and clear terminal, can effectively prevent linear feedback shift register and enter entirely Zero and a full state, in each signal period, linear feedback shift register selectes feedback path, the stochastic ordering of output at random Column change according to the difference of feedback path, and thus the output sequence of the linear feedback shift register has uncertain and not Predictability.

First d type flip flop includes the 7th PMOS tube, the 8th PMOS tube, the 9th PMOS tube, the tenth PMOS tube, the tenth One PMOS tube, the 12nd PMOS tube, the 13rd PMOS tube, the 14th PMOS tube, the tenth NMOS tube, the 11st NMOS tube, the tenth Two NMOS tubes, the 13rd NMOS tube, the 14th NMOS tube, the 15th NMOS tube, the 16th NMOS tube, the 17th NMOS tube, Two phase inverters, third phase inverter, the 4th phase inverter, the 5th phase inverter, hex inverter, the 7th phase inverter, the 8th phase inverter and 9th phase inverter, the source electrode of the 7th PMOS tube, the source electrode of the 8th PMOS tube and the 12nd PMOS tube Source electrode be respectively connected to power supply, the grid of the 7th PMOS tube is connected with the grid of the 13rd NMOS tube and it connects Connect the clear terminal that end is first d type flip flop, the drain electrode of the 7th PMOS tube and the source of the 9th PMOS tube Pole connection, the grid of the 8th PMOS tube, the source electrode of the 13rd PMOS tube, the 15th NMOS tube grid Pole, the 16th NMOS tube source electrode connected with the output end of the 4th phase inverter, the 8th PMOS tube Drain electrode connects with the source electrode of the tenth PMOS tube, the grid of the 9th PMOS tube, the 14th NMOS tube Grid, the grid of the 16th NMOS tube, the grid of the 14th PMOS tube and the third phase inverter it is defeated Outlet connection, the drain electrode of the 9th PMOS tube, the drain electrode of the tenth NMOS tube, the leakage of the 11st PMOS tube Pole, the drain electrode of the tenth PMOS tube, the drain electrode of the 14th NMOS tube and the input terminal of the 4th phase inverter Connection, the grid of the tenth PMOS tube, the grid of the tenth NMOS tube, the 13rd PMOS tube grid, The input terminal of the grid of 17th NMOS tube, the output end of second phase inverter and the third phase inverter connects It connects, the source electrode of the 11st PMOS tube is connected with the drain electrode of the 12nd PMOS tube, the 11st PMOS tube Grid connected with the grid of the 11st NMOS tube and its connecting pin be first d type flip flop input terminal, institute The output end of the grid for the 12nd PMOS tube stated, the grid of the 12nd NMOS tube and the 9th phase inverter connects Connect, the drain electrode of the 13rd PMOS tube, the drain electrode of the 16th NMOS tube, the 14th PMOS tube source Pole, the 17th NMOS tube source electrode connected with the input terminal of the 5th phase inverter, the 14th PMOS tube Drain electrode, the drain electrode of the 17th NMOS tube, the output end of the hex inverter and the 7th phase inverter Input terminal connection, the source electrode of the tenth NMOS tube, the drain electrode of the 11st NMOS tube and the 12nd NMOS The drain electrode of pipe connects, the source electrode and the described the 13rd of the source electrode of the 11st NMOS tube, the 12nd NMOS tube The drain electrode of NMOS tube connects, the source electrode of the 13rd NMOS tube and the source grounding of the 15th NMOS tube, institute The source electrode for the 14th NMOS tube stated is connected with the drain electrode of the 15th NMOS tube, the input terminal of second phase inverter For the clock end of first d type flip flop, the input terminal of the output end of the 5th phase inverter, the hex inverter It is connected with the input terminal of the 8th phase inverter, the output end of the 7th phase inverter is first d type flip flop Reversed-phase output, the output end of the 8th phase inverter are the output end of first d type flip flop, the 9th reverse phase The input terminal of device sets several ends, second d type flip flop, the third d type flip flop, institute for first d type flip flop It is the four d flip-flop stated, the 5th d type flip flop, the 6th d type flip flop, the 7th d type flip flop, described 8th d type flip flop, the 9th d type flip flop, the tenth d type flip flop, the 11st d type flip flop, described Ten 2-D triggers, the tenth 3d flip-flop, the tenth four d flip-flop, the 15th d type flip flop and described The 16th d type flip flop circuit structure it is identical as first d type flip flop.First d type flip flop is by positive and negative register Constitute with clear terminal and the d type flip flop for setting several ends, it is insensitive to clock overlapping, reduce the power consumption of d type flip flop, can reduce The overall power of digital circuit, and first d type flip flop can use its clear terminal and set several ends and initial value is placed in it, prevent The linear feedback shift register being only made of it enters complete zero or complete one state, can not generate random sequence.

The string turns and module includes the 17th d type flip flop, the 18th d type flip flop, the 19th d type flip flop, the 20th D Trigger, the 21st d type flip flop, the 20th 2-D trigger, the 20th 3d flip-flop, the 20th four d flip-flop, the 20th Five d type flip flops, the 26th d type flip flop, the 27th d type flip flop, the 28th d type flip flop, the 29th d type flip flop, 30 d type flip flops, the 31st d type flip flop and the 30th 2-D trigger, the 17th d type flip flop, the described the 18th It is d type flip flop, the 19th d type flip flop, the 20th d type flip flop, the 21st d type flip flop, described 20th 2-D trigger, the 20th 3d flip-flop, the 20th four d flip-flop, the 25th D touching Send out device, the 26th d type flip flop, the 27th d type flip flop, the 28th d type flip flop, described 29th d type flip flop, the 30th d type flip flop, the 31st d type flip flop and the 32nd D touching Hair device is respectively provided with input terminal, clock end, output end and reversed-phase output, and the input terminal of the 17th d type flip flop is institute The string stated turns and the serial input terminal of module, the clock end of the 17th d type flip flop, the 18th d type flip flop Clock end, the clock end of the 19th d type flip flop, the clock end of the 20th d type flip flop, the described the 21st The clock end of d type flip flop, the clock end of the 20th 2-D trigger, the clock end of the 20th 3d flip-flop, The clock end of 20th four d flip-flop, the clock end of the 25th d type flip flop, the 26th D touching Send out the clock end of the device, clock end of the 27th d type flip flop, the clock end of the 28th d type flip flop, described The clock end of the 29th d type flip flop, the clock end of the 30th d type flip flop, the 31st d type flip flop Clock end is connected with the clock end of the 30th 2-D trigger and its connecting pin is the clock that the string turns simultaneously module End, the connecting pin of the input terminal of the output end and the 18th d type flip flop of the 17th d type flip flop are the string Turn the 1st of simultaneously 16 parallel-by-bit output ends of module, the output end of the 18th d type flip flop and the 19th D touching The connecting pin for sending out the input terminal of device is the 2nd of the string turn and 16 parallel-by-bit output ends of module, the 19th D touching The connecting pin for sending out the output end of device and the input terminal of the 20th d type flip flop is 16 parallel-by-bits for turning simultaneously module of going here and there The 3rd of output end, the company of the input terminal of the output end and the 21st d type flip flop of the 20th d type flip flop Connecing end is that the described string turns and the 4th of 16 parallel-by-bit output ends of module, the output end of the 21st d type flip flop and The connecting pin of the input terminal of 20th 2-D trigger is that the string turns the 5th of simultaneously 16 parallel-by-bit output ends of module Position, the connecting pin of the input terminal of the output end and the 20th 3d flip-flop of the 20th 2-D trigger is described String turn and the 6th of 16 parallel-by-bit output ends of module, the output end and described second of the 20th 3d flip-flop The connecting pin of the input terminal of ten four d flip-flops is that the described string turns and the 7th of 16 parallel-by-bit output ends of module, described the The connecting pin of the input terminal of the output end of 20 four d flip-flops and the 25th d type flip flop is that the string turns simultaneously mould The 8th of 16 parallel-by-bit output ends of block, the output end of the 25th d type flip flop and the 26th D triggering The connecting pin of the input terminal of device is the 9th that the string turns simultaneously 16 parallel-by-bit output ends of module, the 26th D touching Send out the output end of device and the input terminal of the 27th d type flip flop connecting pin be the described string turn and 16 of module simultaneously The 10th of row output end, the output end of the 27th d type flip flop and the input terminal of the 28th d type flip flop Connecting pin be that the described string turns and the 11st of 16 parallel-by-bit output ends of module, the 28th d type flip flop it is defeated The connecting pin of the input terminal of outlet and the 29th d type flip flop is the 16 parallel-by-bit output ends that the string turns simultaneously module The 12nd, the connecting pin of the input terminal of the output end and the 30th d type flip flop of the 29th d type flip flop is The described string turns and the 13rd of 16 parallel-by-bit output ends of module, the output end of the 30th d type flip flop and described The connecting pin of the input terminal of 31st d type flip flop is the 14th that the string turns simultaneously 16 parallel-by-bit output ends of module, institute The connecting pin of the input terminal of the output end and the 30th 2-D trigger for the 31st d type flip flop stated is the string Turn the 15th of simultaneously 16 parallel-by-bit output ends of module, the output end of the 30th 2-D trigger is that the string turns simultaneously The 16th of 16 parallel-by-bit output ends of module.The circuit is made of the d type flip flop for having by low power consumption characteristic, makes circuit entirety function Consumption reduces, and the circuit can work under higher clock frequency, and data transfer speeds are fast.

17th d type flip flop includes the 15th PMOS tube, the 16th PMOS tube, the 17th PMOS tube, the 18th PMOS tube, the 19th PMOS tube, the 20th PMOS tube, the 18th NMOS tube, the 19th NMOS tube, the 20th NMOS tube, second 11 NMOS tubes, the 22nd NMOS tube, the 23rd NMOS tube, the tenth phase inverter, the 11st phase inverter, the 12nd reverse phase Device, the 13rd phase inverter, the 14th phase inverter, the 15th phase inverter and the tenth hex inverter, the 15th PMOS tube Source electrode and the source electrode of the 16th PMOS tube access power supply, the drain electrode of the 15th PMOS tube and the described the tenth The source electrodes of seven PMOS tube connects, the grid of the 15th PMOS tube, the grid of the 19th NMOS tube, described the The grid of 22 NMOS tubes, the 20th PMOS tube grid connected with the output end of the 11st phase inverter, The drain electrode of 16th PMOS tube is connected with the source electrode of the 18th PMOS tube, the grid of the 16th PMOS tube Pole, the output end of the 12nd phase inverter, the grid of the 21st NMOS tube, the 19th PMOS tube Source electrode is connected with the source electrode of the 22nd NMOS tube, the grid and the described the 18th of the 17th PMOS tube The grid of NMOS tube connects and its connecting pin is the input terminal of the 17th d type flip flop, the 17th PMOS tube Drain electrode, the drain electrode of the 18th NMOS tube, the drain electrode of the 18th PMOS tube, the leakage of the 19th NMOS tube Pole is connected with the input terminal of the 12nd phase inverter, grid, the 20th NMOS of the 18th PMOS tube The grid of pipe, the grid of the 19th PMOS tube, the grid of the 23rd NMOS tube, the tenth phase inverter Output end connected with the input terminal of the 11st phase inverter, the drain electrode of the 19th PMOS tube, described second The drain electrode of 12 NMOS tubes, the source electrode of the 20th PMOS tube, the source electrode of the 23rd NMOS tube and described The input terminal of 13rd phase inverter connects, the drain electrode of the 20th PMOS tube, the drain electrode of the 23rd NMOS tube, The output end of 14th phase inverter is connected with the input terminal of the 15th phase inverter, the 18th NMOS tube Source electrode connected with the drain electrode of the 20th NMOS tube, the source electrode and the described the 21st of the 19th NMOS tube The drain electrode of NMOS tube connects, the source electrode of the 20th NMOS tube and the source grounding of the 21st NMOS tube, The input terminal of tenth phase inverter be the 17th d type flip flop clock end, the 13rd phase inverter it is defeated Outlet, the 14th phase inverter input terminal connected with the input terminal of the tenth hex inverter, the described the 15th The output end of phase inverter is the reversed-phase output of the 17th d type flip flop, and the output end of the tenth hex inverter is The output end of 17th d type flip flop；18th d type flip flop, the 19th d type flip flop, described 20 d type flip flops, the 21st d type flip flop, the 20th 2-D trigger, the 23rd D triggering Device, the 20th four d flip-flop, the 25th d type flip flop, the 26th d type flip flop, described 27 d type flip flops, the 28th d type flip flop, the 29th d type flip flop, the 30th D triggering The triggering of 17th D described in the circuit structure diagram of device, the 31st d type flip flop and the 30th 2-D trigger Device is identical.The circuit is the d type flip flop for the edging trigger being made of positive and negative register, it is not easy to enter metastable state, to clock weight It folds insensitive, reduces the power consumption of d type flip flop, can reduce the overall power of digital circuit.

The moderator PUF includes the identical 128 switch unit circuits of structure and a moderator, the arbitration Device has first input end, the second input terminal and output end, and the switch unit circuit has first input end, the second input End, control terminal, the first output end and second output terminal, the first input end of switch unit circuit described in the 1st and second defeated Enter end connection and its connecting pin for the input terminal of the moderator PUF, first of switch unit circuit described in j-th exports End is connected with the first input end of switch unit circuit described in jth+1, and the second of switch unit circuit is defeated described in j-th Outlet is connected with the second input terminal of switch unit circuit described in jth+1, j=1, and 2 ... ..., 127；Described in 128th First output end of switch unit circuit is connected with the first input end of the moderator, switch unit described in the 128th The second output terminal of circuit is connected with the second input terminal of the moderator, and the output end of the moderator is described secondary The output end of device PUF is cut out, switch unit circuit described in control terminal, kth+16 of switch unit circuit described in k-th The control terminal of switch unit circuit described in control terminal, control terminal, the kth+48 of switch unit circuit described in kth+32, Control terminal, the kth+96 of switch unit circuit described in control terminal, kth+80 of switch unit circuit described in kth+64 The control terminal of a switch unit circuit is connected with the control terminal of switch unit circuit described in kth+112 and it is connected Kth position of the end for the 16 parallel-by-bit control terminals of the moderator PUF, k=1,2,3 ..., 16；The switch unit circuit Including the 7th data selector, the 8th data selector, the 17th phase inverter, eighteen incompatibilities phase device, the 19th phase inverter and 20 phase inverters, the 7th data selector and the 8th data selector are respectively two input data selectors, 7th data selector and the 8th data selector are respectively provided with first input end, the second input terminal, control End and output end, the first input end of the 7th data selector and the first input end of the 8th data selector Connection and its connecting pin are the first input end of the switch unit circuit, the second input of the 7th data selector End is connected with the second input terminal of the 8th data selector and its connecting pin is the second of the switch unit circuit The control terminal of input terminal, the 7th data selector is connected with the control terminal of the 8th data selector and it is connected End is the control terminal of the switch unit circuit, the output end of the 7th data selector and the 17th reverse phase The input terminal of device connects, and the output end of the 17th phase inverter is connected with the input terminal of the eighteen incompatibilities phase device, institute The output end for the eighteen incompatibilities phase device stated is the first output end of the switch unit single channel, the 8th data selector Output end connected with the input terminal of the 19th phase inverter, the output end of the 19th phase inverter and described The input terminals of 20 phase inverters connects, and the output end of the 20th phase inverter is the second defeated of the switch unit single channel Outlet.Moderator PUF has 128 identical switch unit circuits, transmission path complete phase of the data in switch unit Together, the delay only influence by process deviation that data generate in the transmission, the delay inequality of 128 bit switch units accumulation can have Effect overcomes the settling time of d type flip flop, the randomness of output is improved, since the path select signal of switch unit circuit is by linear The output of feedback shift register provides, and is updated according to clock signal, can be realized the continuous output of key.

Compared with the prior art, the advantages of the present invention are as follows pass through storage-type stochastic source, linear feedback shift register, string Turn and module and moderator PUF construct the restructural PUF element circuit of multimodal fusion, 8 parallel-by-bit output ends of storage-type stochastic source It connects one to one with 8 parallel-by-bit input terminals of linear feedback shift register, the Serial output of linear feedback shift register End turns with string and the serial input terminal of module connects, and 16 of the 16 parallel-by-bit output ends and moderator PUF of string turn and module are simultaneously Row control terminal connects one to one；Storage-type stochastic source includes identical eight storage units of structure, each storage unit difference With control terminal, enable end and output end, the control terminal of eight storage units is connected and its connecting pin is storage-type stochastic source Control terminal, the enable end of enable end connection and its connecting pin for storage-type stochastic source of eight storage units, m-th of storage unit Output end be m, m=1 of 8 parallel-by-bit output ends of storage-type stochastic source, 2 ..., 8, storage unit includes the first PMOS Pipe, the second PMOS tube, third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the first NMOS tube, the 2nd NMOS Pipe, third NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS Pipe, the one or two input nand gate, the two or two input nand gate and the first phase inverter；The present invention is defeated by storage-type stochastic source Selection signal of the excitation as linear feedback shift register out improves linear feedback shift register using storage-type stochastic source The randomness for generating random sequence, can generate 120 times more than normal linear feedback shift register of signal, improve The randomness of moderator PUF path select signal improves input signal to the complexity of output response, has circuit higher Randomness and safety.

Detailed description of the invention

Fig. 1 is the principle of the present invention structural block diagram；

Fig. 2 is the circuit diagram of storage-type stochastic source of the invention；

Fig. 3 is the circuit diagram of storage unit in storage-type stochastic source of the invention；

Fig. 4 is the circuit diagram of linear feedback shift register of the invention；

Fig. 5 is the circuit diagram of the first d type flip flop in linear feedback shift register of the invention；

Fig. 6 is the circuit diagram that string of the invention turns simultaneously module；

Fig. 7 is the circuit diagram that string of the invention turns the 17th d type flip flop in simultaneously module；

Fig. 8 is the circuit diagram of moderator PUF of the invention；

Fig. 9 is the circuit diagram of switch unit circuit in moderator PUF of the invention；

Figure 10 is analogous diagram of the invention；

Figure 11 is the quantity statistics figure of O and 1 in output response of the invention.

Specific embodiment

The present invention will be described in further detail below with reference to the embodiments of the drawings.

Embodiment one: as shown in Figure 1, Figure 2 and Figure 3, a kind of restructural PUF unit electricity of multimodal fusion based on linear feedback Road, including storage-type stochastic source, linear feedback shift register, string turn simultaneously module and moderator PUF, storage-type stochastic source and have Control terminal, enable end and 8 parallel-by-bit output ends；Linear feedback shift register have 8 parallel-by-bit input terminals, serial output terminal, Clear terminal sets several ends and clock end；String turns and module has serial input terminal, clock end and 16 parallel-by-bit output ends；Moderator PUF has input terminal, 16 parallel-by-bit control terminals and output end；The control terminal of storage-type stochastic source is for accessing word line control signal WL, the enable end of storage-type stochastic source is for accessing enable signal SAE, and the clear terminal of linear feedback shift register is for accessing Reset signal CN, linear feedback shift register set several ends for access set several signal SN, linear feedback shift register Clock end and string turn and the input terminal of the clock end equal incoming clock signal CLK, moderator PUF of module access input signal IN, The output end of moderator PUF is moved for exporting PUF output response, the 8 parallel-by-bit output ends and linear feedback of storage-type stochastic source 8 parallel-by-bit input terminals of bit register connect one to one, and the serial output terminal and string of linear feedback shift register turn simultaneously mould The serial input terminal of block connects, and string turns 16 parallel-by-bit control terminals of the simultaneously 16 parallel-by-bit output ends and moderator PUF of module one by one It is correspondingly connected with；Storage-type stochastic source includes the identical eight storage units cell1~cell8 of structure, each storage unit difference With control terminal, enable end and output end, the control terminal of eight storage units is connected and its connecting pin is storage-type stochastic source Control terminal, the enable end of enable end connection and its connecting pin for storage-type stochastic source of eight storage units, m-th of storage unit Output end be m, m=1 of 8 parallel-by-bit output ends of storage-type stochastic source, 2 ..., 8；Storage unit includes the first PMOS Pipe P1, the second PMOS tube P2, third PMOS tube P3, the 4th PMOS tube P4, the 5th PMOS tube P5, the 6th PMOS tube P6, first NMOS tube N1, the second NMOS tube N2, third NMOS tube N3, the 4th NMOS tube N4, the 5th NMOS tube N5, the 6th NMOS tube N6, Seven NMOS tube N7, the 8th NMOS tube N8, the 9th NMOS tube N9, the one or two input nand gate A1, the two or two input nand gate A2 and First phase inverter B1；One or two input nand gate A1 and the two or two input nand gate A2 is respectively provided with first input end, second defeated Enter end and output end, the source electrode of the first PMOS tube P1, the source electrode of the second PMOS tube P2, the source electrode of third PMOS tube P3, the 4th The source electrode of the source electrode of PMOS tube P4, the source electrode of the 5th PMOS tube P5 and the 6th PMOS tube P6 accesses power supply, the first PMOS tube P1 Grid, the drain electrode of the second PMOS tube P2, the drain electrode of the second NMOS tube N2, third NMOS tube N3 grid and the 4th NMOS tube N4 Drain electrode connection, the drain electrode of the first PMOS tube P1, the grid of the second PMOS tube P2, the drain electrode of the first NMOS tube N1, the 3rd NMOS The drain electrode of pipe N3 is connected with the grid of the 4th NMOS tube N4, the grid connection of the grid of the first NMOS tube N1 and the second NMOS tube N2 And its connecting pin is the control terminal of storage unit, and the source electrode of the first NMOS tube N1 and the grid of the 7th NMOS tube N7 connect, and second The connection of the grid of the source electrode of NMOS tube N2 and the 8th NMOS tube N8, the source electrode of third NMOS tube N3 and the source electrode of the 4th NMOS tube N4 It is grounded, the grid connection and its connection of the grid of third PMOS tube P3, the grid of the 6th PMOS tube P6 and the 9th NMOS tube N9 End be storage unit enable end, the drain electrode of third PMOS tube P3, the drain electrode of the 4th PMOS tube P4, the 5th PMOS tube P5 grid Pole, the drain electrode of the 5th NMOS tube N5, the first input end connection of the grid of the 6th NMOS tube N6 and the one or two input nand gate A1, The grid of 4th PMOS tube P4, the drain electrode of the 5th PMOS tube P5, the drain electrode of the 6th PMOS tube P6, the 5th NMOS tube N5 grid, The drain electrode of 6th NMOS tube N6 is connected with the second input terminal of the two or two input nand gate A2, the source electrode of the 5th NMOS tube N5 and The drain electrode of seven NMOS tube N7 connects, the drain electrode connection of the source electrode and the 8th NMOS tube N8 of the 6th NMOS tube N6, the 7th NMOS tube N7 Source electrode, the 8th NMOS tube N8 source electrode and the 9th NMOS tube N9 drain electrode connection, the 9th NMOS tube N9 source electrode ground connection, first The output end connection of the second input terminal and the two or two input nand gate A2 of two input nand gate A1, the one or two input nand gate A1 Output end, the two or two input nand gate A2 first input end and the first phase inverter B1 input terminal connection, the first phase inverter The output end of B1 is the output end of storage unit.

Embodiment two: the present embodiment is basically the same as the first embodiment, and difference is:

As shown in figure 4, linear feedback shift register includes the first data selector MUX1, the second number in the present embodiment According to selector MUX2, third data selector MUX3, the 4th data selector MUX4, the 5th data selector MUX5, the 6th number According to selector MUX6, the one or two input XOR gate C1, the first d type flip flop DFF1, the second d type flip flop DFF2, third d type flip flop DFF3, four d flip-flop DFF4, the 5th d type flip flop DFF5, the 6th d type flip flop DFF6, the 7th d type flip flop DFF7, the 8th D touching Send out device DFF8, the 9th d type flip flop DFF9, the tenth d type flip flop DFF10, the 11st d type flip flop DFF11, the tenth 2-D trigger DFF12, the tenth 3d flip-flop DFF13, the tenth four d flip-flop DFF14, the 15th d type flip flop DFF15 and the 16th d type flip flop DFF16, the first data selector MUX1, the second data selector MUX2, third data selector MUX3 and the selection of the 4th data Device MUX4 is four input data selectors, the first data selector MUX1, the second data selector MUX2, the selection of third data Device MUX3 and the 4th data selector MUX4 is respectively provided with first input end, the second input terminal, third input terminal, the 4th input End, the first control terminal, the second control terminal and output end, the 5th data selector MUX5 and the 6th data selector MUX6 are two Input data selector, the 5th data selector MUX5 and the 6th data selector MUX6 are respectively provided with first input end, second Input terminal, control terminal and output end, the one or two input XOR gate C1 have first input end, the second input terminal and output end, the One d type flip flop DFF1, the second d type flip flop DFF2, third d type flip flop DFF3, four d flip-flop DFF4, the 5th d type flip flop DFF5, the 6th d type flip flop DFF6, the 7th d type flip flop DFF7, the 8th d type flip flop DFF8, the 9th d type flip flop DFF9, the tenth D touching Send out device DFF10, the 11st d type flip flop DFF11, the tenth 2-D trigger DFF12, the tenth 3d flip-flop DFF13, the 14th D touching Hair device DFF14, the 15th d type flip flop DFF15 and the 16th d type flip flop DFF16 be respectively provided with input terminal, clock end, set several ends, Clear terminal, output end and reversed-phase output, the clock end of the first d type flip flop DFF1, the clock end of the second d type flip flop DFF2, The clock end of 3d flip-flop DFF3, the clock end of four d flip-flop DFF4, the clock end of the 5th d type flip flop DFF5, the 6th D touching Send out the clock end of device DFF6, the clock end of the 7th d type flip flop DFF7, the clock end of the 8th d type flip flop DFF8, the 9th d type flip flop The clock end of DFF9, the clock end of the tenth d type flip flop DFF10, the clock end of the 11st d type flip flop DFF11, the 12nd D triggering The clock end of device DFF12, the clock end of the tenth 3d flip-flop DFF13, the clock end of the tenth four d flip-flop DFF14, the 15th D The clock end of trigger DFF15 is connected with the clock end of the 16th d type flip flop DFF16 and its connecting pin is posted for linear feedback shift The clock end of storage；First d type flip flop DFF1's sets several ends, the clear terminal of the second d type flip flop DFF2, third d type flip flop DFF3 Set several ends, four d flip-flop DFF4 set several ends, the clear terminal of the 5th d type flip flop DFF5, the 6th d type flip flop DFF6 are set Number ends, the clear terminal of the 7th d type flip flop DFF7, the 8th d type flip flop DFF8 set several ends, the 9th d type flip flop DFF9 clear terminal, The clearing for setting several ends, the tenth 2-D trigger DFF12 for setting several ends, the 11st d type flip flop DFF11 of tenth d type flip flop DFF10 End, the clear terminal of the tenth 3d flip-flop DFF13, the tenth four d flip-flop DFF14 clear terminal, the 15th d type flip flop DFF15 are set Number ends connects with the clear terminal of the 16th d type flip flop DFF16 and several ends for linear feedback shift register are set in its connecting pin；The The clear terminal DFF1 of one d type flip flop, the second d type flip flop DFF2 set several ends, the clear terminal of third d type flip flop DFF3, the 4th D touching Send out the clear terminal of device DFF4, the 5th d type flip flop DFF5 sets several ends, the clear terminal of the 6th d type flip flop DFF6, the 7th d type flip flop DFF7 set several ends, the clear terminal of the 8th d type flip flop DFF8, the 9th d type flip flop DFF9 set several ends, the tenth d type flip flop DFF10 Clear terminal, the clear terminal of the 11st d type flip flop DFF11, the tenth 2-D trigger DFF12 set several ends, the tenth 3d flip-flop The clear terminal and the 16th D for setting several ends, the 15th d type flip flop DFF15 for setting several ends, the tenth four d flip-flop DFF14 of DFF13 Trigger sets several end connections and its connecting pin as the clear terminal of linear feedback shift register；First data selector MUX1's The input terminal of first input end, the output end of the first d type flip flop DFF1 and the second d type flip flop DFF2 connects, the selection of the first data The second input terminal of device MUX1, the second d type flip flop DFF2 output end connected with the input terminal of third d type flip flop DFF3, first The input terminal of the third input terminal of data selector MUX1, the output end of third d type flip flop DFF3 and four d flip-flop DFF4 connects It connects, the 4th input terminal of the first data selector MUX1, the output end of four d flip-flop DFF4 and the 5th d type flip flop DFF5 Input terminal connection, the first input end of the second data selector MUX2, the output end of the 5th d type flip flop DFF5 and the 6th D triggering The input terminal of device DFF6 connects, the second input terminal of the second data selector MUX2, the output end of the 6th d type flip flop DFF6 and the The input terminal of seven d type flip flop DFF7 connects, the third input terminal of the second data selector MUX2, the 7th d type flip flop DFF7 it is defeated Outlet is connected with the input terminal of the 8th d type flip flop DFF8, the 4th input terminal, the 8th d type flip flop of the second data selector MUX2 The connection of the input terminal of the output end of DFF8 and the 9th d type flip flop DFF9, the first input end of third data selector MUX3, the 9th The connection of the input terminal of the output end of d type flip flop DFF9 and the tenth d type flip flop DFF10, the second of third data selector MUX3 are defeated Enter the input terminal connection of end, the output end of the tenth d type flip flop DFF10 and the 11st d type flip flop DFF11, third data selector The input terminal of the third input terminal of MUX3, the output end of the 11st d type flip flop DFF11 and the tenth 2-D trigger DFF12 connects, The output end and the tenth 3d flip-flop DFF13 of the 4th input terminal of third data selector MUX3, the tenth 2-D trigger DFF12 Input terminal connection, the output end and the tenth of the first input end of the 4th data selector MUX4, the tenth 3d flip-flop DFF13 The input terminal of four d flip-flop DFF14 connects, the second input terminal, the tenth four d flip-flop DFF14 of the 4th data selector MUX4 Output end and the 15th d type flip flop DFF15 input terminal connection, the third input terminal of the 4th data selector MUX4, the tenth The connection of the input terminal of the output end of five d type flip flop DFF15 and the 16th d type flip flop DFF16, the of the 4th data selector MUX4 The connection of the output end of four input terminals and the 16th d type flip flop DFF16 and its connecting pin are the serial of linear feedback shift register Output end, the first input end connection of the output end and the 5th data selector MUX5 of the first data selector MUX1, the second number It is connected according to the output end of selector MUX2 and the second input terminal of the 5th data selector MUX5, third data selector MUX3's The connection of the first input end of output end and the 6th data selector MUX6, the output end of the 4th data selector MUX4 and the 6th number It is connected according to the second input terminal of selector MUX6, the output end of the 5th data selector MUX5 and the one or two inputs XOR gate C1's The second input terminal of first input end connection, the output end of the 6th data selector MUX6 and the one or two input XOR gate C1 connect It connects, the input terminal connection of the output end and the first d type flip flop DFF1 of the one or two input XOR gate C1, the first data selector MUX1 The first control terminal be the 1st of 8 parallel-by-bit input terminals of linear feedback shift register, the of the first data selector MUX1 Two control terminals are the 2nd of 8 parallel-by-bit input terminals of linear feedback shift register, the first control of the second data selector MUX2 End processed is the 3rd of 8 parallel-by-bit input terminals of linear feedback shift register, the second control terminal of the second data selector MUX2 It is the 4th of 8 parallel-by-bit input terminals of linear feedback shift register, the first control terminal of third data selector MUX3 is line Property the 5th of 8 parallel-by-bit input terminals of feedback shift register, the second control terminal of third data selector MUX3 is linear anti- The 6th for presenting 8 parallel-by-bit input terminals of shift register, the first control terminal of the 4th data selector MUX4 and the choosing of the 5th data The connecting pin for selecting the control terminal of device MUX5 is the 7th of 8 parallel-by-bit input terminals of linear feedback shift register, the choosing of the 4th data The connecting pin for selecting the second control terminal of device MUX4 and the control terminal of the 6th data selector MUX6 is linear feedback shift register The 8th of 8 parallel-by-bit input terminals.

As shown in figure 5, in the present embodiment, the first d type flip flop DFF1 includes the 7th PMOS tube P7, the 8th PMOS tube P8, the Nine PMOS tube P9, the tenth PMOS tube P10, the 11st PMOS tube P11, the 12nd PMOS tube P12, the 13rd PMOS tube P13, the tenth Four PMOS tube P14, the tenth NMOS tube N10, the 11st NMOS tube N11, the 12nd NMOS tube N12, the 13rd NMOS tube N13, 14 NMOS tube N14, the 15th NMOS tube N15, the 16th NMOS tube N16, the 17th NMOS tube N17, the second phase inverter B2, Three phase inverter B3, the 4th phase inverter B4, the 5th phase inverter B5, hex inverter B6, the 7th phase inverter B7, the 8th phase inverter B8 and 9th phase inverter B9, the source electrode difference of the source electrode of the 7th PMOS tube P7, the source electrode of the 8th PMOS tube P8 and the 12nd PMOS tube P12 Power supply is accessed, the grid of the 7th PMOS tube P7 and the grid of the 13rd NMOS tube N13 connect and its connecting pin is the first d type flip flop The drain electrode of the clear terminal of DFF1, the 7th PMOS tube P7 is connected with the source electrode of the 9th PMOS tube P9, the grid of the 8th PMOS tube P8, The source electrode of 13 PMOS tube P13, the grid of the 15th NMOS tube N15, the 16th NMOS tube N16 source electrode and the 4th phase inverter B4 Output end connection, the drain electrode of the 8th PMOS tube P8 connects with the source electrode of the tenth PMOS tube P10, the grid of the 9th PMOS tube P9, The grid of 14th NMOS tube N14, the grid of the 16th NMOS tube N16, the 14th PMOS tube P14 grid and third phase inverter The output end of B3 connects, the drain electrode of the 9th PMOS tube P9, the drain electrode of the tenth NMOS tube N10, the drain electrode of the 11st PMOS tube P11, The drain electrode of tenth PMOS tube P10, the drain electrode of the 14th NMOS tube N14 are connected with the input terminal of the 4th phase inverter B4, the tenth PMOS The grid of pipe P10, the grid of the tenth NMOS tube N10, the grid of the 13rd PMOS tube P13, the 17th NMOS tube N17 grid, The output end of second phase inverter B2 is connected with the input terminal of third phase inverter B3, the source electrode and the 12nd of the 11st PMOS tube P11 The drain electrode of PMOS tube P12 connects, the grid connection and its connection of the grid and the 11st NMOS tube N11 of the 11st PMOS tube P11 End is the input terminal of the first d type flip flop DFF1, the grid and the 9th of the grid of the 12nd PMOS tube P12, the 12nd NMOS tube N12 The output end of phase inverter B9 connects, drain electrode, the drain electrode of the 16th NMOS tube N16, the 14th PMOS tube of the 13rd PMOS tube P13 The input terminal of the source electrode of P14, the source electrode of the 17th NMOS tube N17 and the 5th phase inverter B5 connects, the leakage of the 14th PMOS tube P14 Pole, the drain electrode of the 17th NMOS tube N17, the input terminal connection of the output end of hex inverter B6 and the 7th phase inverter B7, the tenth The drain electrode of the source electrode of NMOS tube N10, the 11st NMOS tube N11 is connected with the drain electrode of the 12nd NMOS tube N12, the 11st NMOS tube The drain electrode of the source electrode of N11, the source electrode of the 12nd NMOS tube N12 and the 13rd NMOS tube N13 connects, the 13rd NMOS tube N13's The source grounding of source electrode and the 15th NMOS tube N15, the leakage of the source electrode and the 15th NMOS tube N15 of the 14th NMOS tube N14 Pole connection, the input terminal of the second phase inverter B2 are the clock end of the first d type flip flop DFF1, the output end of the 5th phase inverter B5, the The connection of the input terminal of the input terminal of hex inverter B6 and the 8th phase inverter B8, the output end of the 7th phase inverter B7 are the first D triggering The reversed-phase output of device DFF1, the output end of the 8th phase inverter B8 are the output end of the first d type flip flop DFF1, the 9th phase inverter B9 Input terminal be that the first d type flip flop DFF1 sets several ends, the second d type flip flop DFF2, third d type flip flop DFF3, four d flip-flop DFF4, the 5th d type flip flop DFF5, the 6th d type flip flop DFF6, the 7th d type flip flop DFF7, the 8th d type flip flop DFF8, the 9th D touching Send out device DFF9, the tenth d type flip flop DFF10, the 11st d type flip flop DFF11, the tenth 2-D trigger DFF12, the tenth 3d flip-flop The circuit structure and of DFF13, the tenth four d flip-flop DFF14, the 15th d type flip flop DFF15 and the 16th d type flip flop DFF16 One d type flip flop DFF1 is identical.

As shown in fig. 6, string turns and module includes the 17th d type flip flop DFF17, the 18th d type flip flop in the present embodiment DFF18, the 19th d type flip flop DFF19, the 20th d type flip flop DFF20, the 21st d type flip flop DFF21, the 22nd D touching Send out device DFF22, the 20th 3d flip-flop DFF23, the 20th four d flip-flop DFF24, the 25th d type flip flop DFF25, second 16 d type flip flop DFF26, the 27th d type flip flop DFF27, the 28th d type flip flop DFF28, the 29th d type flip flop DFF29, the 30th d type flip flop DFF30, the 31st d type flip flop DFF31 and the 30th 2-D trigger DFF32, the 17th D touching Send out device DFF17, the 18th d type flip flop DFF18, the 19th d type flip flop DFF19, the 20th d type flip flop DFF20, the 21st D Trigger DFF21, the 20th 2-D trigger DFF22, the 20th 3d flip-flop DFF23, the 20th four d flip-flop DFF24, 25 d type flip flop DFF25, the 26th d type flip flop DFF26, the 27th d type flip flop DFF27, the 28th d type flip flop DFF28, the 29th d type flip flop DFF29, the 30th d type flip flop DFF30, the 31st d type flip flop DFF31 and the 32nd D Trigger DFF32 is respectively provided with input terminal, clock end, output end and reversed-phase output, the input of the 17th d type flip flop DFF17 End turns for string and the serial input terminal of module, the clock end of the 17th d type flip flop DFF17, the 18th d type flip flop DFF18 when Zhong Duan, the clock end of the 19th d type flip flop DFF19, the clock end of the 20th d type flip flop DFF20, the 21st d type flip flop The clock end of DFF21, the clock end of the 20th 2-D trigger DFF22, the clock end of the 20th 3d flip-flop DFF23, second The clock end of ten four d flip-flop DFF24, the clock end of the 25th d type flip flop DFF25, the 26th d type flip flop DFF26 Clock end, the clock end of the 27th d type flip flop DFF27, the clock end of the 28th d type flip flop DFF28, the 29th D touching Send out the clock end of device DFF29, the clock end of the 30th d type flip flop DFF30, the clock end of the 31st d type flip flop DFF31 and the The clock end of 30 2-D trigger DFF32 connects and its connecting pin is the clock end that string turns simultaneously module, the 17th d type flip flop The connecting pin of the input terminal of the output end of DFF17 and the 18th d type flip flop DFF18 is the 16 parallel-by-bit output ends that string turns simultaneously module The 1st, the connecting pin of the input terminal of the output end and the 19th d type flip flop DFF19 of the 18th d type flip flop DFF18 is that string turns And the 2nd of 16 parallel-by-bit output ends of module, the output end and the 20th d type flip flop DFF20 of the 19th d type flip flop DFF19 The connecting pin of input terminal be that string turns and the 3rd of 16 parallel-by-bit output ends of module, the output of the 20th d type flip flop DFF20 The connecting pin of the input terminal of end and the 21st d type flip flop DFF21 is the 4th that string turns simultaneously 16 parallel-by-bit output ends of module, The connecting pin of the input terminal of the output end and the 20th 2-D trigger DFF22 of 21st d type flip flop DFF21 is that string turns simultaneously mould The 5th of 16 parallel-by-bit output ends of block, the output end and the 20th 3d flip-flop DFF23 of the 20th 2-D trigger DFF22 The connecting pin of input terminal be that string turns and the 6th of 16 parallel-by-bit output ends of module, the 20th 3d flip-flop DFF23's is defeated The connecting pin of the input terminal of outlet and the 20th four d flip-flop DFF24 is that string turns the 7th of simultaneously 16 parallel-by-bit output ends of module Position, the connecting pin of the input terminal of the output end and the 25th d type flip flop DFF25 of the 20th four d flip-flop DFF24 are that string turns simultaneously The 8th of 16 parallel-by-bit output ends of module, the output end and the 26th d type flip flop of the 25th d type flip flop DFF25 The connecting pin of the input terminal of DFF26 is the 9th that string turns simultaneously 16 parallel-by-bit output ends of module, the 26th d type flip flop DFF26 Output end and the 27th d type flip flop DFF27 input terminal connecting pin be string turn and module 16 parallel-by-bit output ends 10th, the connecting pin of the input terminal of the output end and the 28th d type flip flop DFF28 of the 27th d type flip flop DFF27 is string Turn the 11st of simultaneously 16 parallel-by-bit output ends of module, the output end of the 28th d type flip flop DFF28 and the 29th D triggering The connecting pin of the input terminal of device DFF29 is the 12nd that string turns simultaneously 16 parallel-by-bit output ends of module, the 29th d type flip flop The connecting pin of the input terminal of the output end of DFF29 and the 30th d type flip flop DFF30 is the 16 parallel-by-bit output ends that string turns simultaneously module The 13rd, the connecting pin of the input terminal of the output end and the 31st d type flip flop DFF31 of the 30th d type flip flop DFF30 is string Turn the 14th of simultaneously 16 parallel-by-bit output ends of module, the output end of the 31st d type flip flop DFF31 and the 32nd D triggering The connecting pin of the input terminal of device DFF32 is the 15th that string turns simultaneously 16 parallel-by-bit output ends of module, the 30th 2-D trigger The output end of DFF32 is the 16th that string turns simultaneously 16 parallel-by-bit output ends of module.

As shown in fig. 7, the 17th d type flip flop DFF17 includes the 15th PMOS tube P15, the 16th PMOS in the present embodiment Pipe P16, the 17th PMOS tube P17, the 18th PMOS tube P18, the 19th PMOS tube P19, the 20th PMOS tube P20, the 18th NMOS tube N18, the 19th NMOS tube N19, the 20th NMOS tube N20, the 21st NMOS tube N21, the 22nd NMOS tube N22, the 23rd NMOS tube N23, the tenth phase inverter B10, the 11st phase inverter B11, the 12nd phase inverter B12, the 13rd are instead Phase device B13, the 14th phase inverter B14, the 15th phase inverter B15 and the tenth hex inverter B16, the source of the 15th PMOS tube P15 The source electrode of pole and the 16th PMOS tube P16 access power supply, and the drain electrode of the 15th PMOS tube P15 is with the 17th PMOS tube P17's Source electrode connection, the grid of the 15th PMOS tube P15, the grid of the 19th NMOS tube N19, the 22nd NMOS tube N22 grid, The connection of the output end of the grid of 20th PMOS tube P20 and the 11st phase inverter B11, the drain electrode of the 16th PMOS tube P16 and the The source electrode of 18 PMOS tube P18 connects, the grid of the 16th PMOS tube P16, the output end of the 12nd phase inverter B12, the 20th The source electrode of the grid of one NMOS tube N21, the source electrode of the 19th PMOS tube P19 and the 22nd NMOS tube N22 connects, and the 17th The connection of the grid of the grid of PMOS tube P17 and the 18th NMOS tube N18 and its connecting pin are the defeated of the 17th d type flip flop DFF17 Enter end, the drain electrode of the 17th PMOS tube P17, the drain electrode of the 18th NMOS tube N18, the drain electrode of the 18th PMOS tube P18, the 19th The drain electrode of NMOS tube N19 is connected with the input terminal of the 12nd phase inverter B12, grid, the 20th NMOS of the 18th PMOS tube P18 The grid of pipe N20, the grid of the 19th PMOS tube P19, the 23rd NMOS tube N23 grid, the tenth phase inverter B10 output End is connected with the input terminal of the 11st phase inverter B11, the drain electrode of the 19th PMOS tube P19, the leakage of the 22nd NMOS tube N22 Pole, the source electrode of the 20th PMOS tube P20, the source electrode of the 23rd NMOS tube N23 and the 13rd phase inverter B13 input terminal connect It connects, the drain electrode of the 20th PMOS tube P20, the drain electrode of the 23rd NMOS tube N23, the output end of the 14th phase inverter B14 and The input terminal of 15 phase inverter B15 connects, the drain electrode connection of the source electrode and the 20th NMOS tube N20 of the 18th NMOS tube N18, the The drain electrode connection of the source electrode and the 21st NMOS tube N21 of 19 NMOS tube N19, the source electrode and second of the 20th NMOS tube N20 The source grounding of 11 NMOS tube N21, the input terminal of the tenth phase inverter B10 are the clock end of the 17th d type flip flop DFF17, The input terminal of the output end of 13rd phase inverter B13, the input terminal of the 14th phase inverter B14 and the tenth hex inverter B16 connects, The output end of 15th phase inverter B15 is the reversed-phase output of the 17th d type flip flop DFF17, the output of the tenth hex inverter B16 End is the output end of the 17th d type flip flop DFF17；18th d type flip flop DFF18, the 19th d type flip flop DFF19, the 20th D Trigger DFF20, the 21st d type flip flop DFF21, the 20th 2-D trigger DFF22, the 20th 3d flip-flop DFF23, 20 four d flip-flop DFF24, the 25th d type flip flop DFF25, the 26th d type flip flop DFF26, the 27th d type flip flop DFF27, the 28th d type flip flop DFF28, the 29th d type flip flop DFF29, the 30th d type flip flop DFF30, the 31st D The 17th d type flip flop DFF17 of circuit structure diagram of trigger DFF31 and the 30th 2-D trigger DFF32 is identical.

As shown in Figure 8 and Figure 9, in the present embodiment, moderator PUF includes the identical 128 switch unit circuits S1 of structure ~S128 and moderator, moderator have first input end, the second input terminal and output end, and switch unit circuit has the One input terminal, the second input terminal, control terminal, the first output end and second output terminal, the first of the 1st switch unit circuit S1 are defeated Enter that end is connected with the second input terminal and its connecting pin is the input terminal of moderator PUF, the first of j-th of switch unit circuit Sj be defeated Outlet is connected with the first input end of+1 switch unit circuit S (j+1) of jth, the second output of j-th of switch unit circuit Sj End is connected with the second input terminal of+1 switch unit circuit S (j+1) of jth, j=1, and 2 ... ..., 127；128th switch unit The first output end of circuit S128 is connected with the first input end of moderator, and the second of the 128th switch unit circuit S128 is defeated Outlet is connected with the second input terminal of moderator, and the output end of moderator is the output end of moderator PUF, k-th of switch unit + 32 switch unit circuit S (k+ of control terminal, kth of+16 switch unit circuit S (k+16) of control terminal, kth of circuit Sk 32)+64 switch unit circuit S (k+64) of control terminal, kth of+48 switch unit circuit S (k+48) of control terminal, kth Control terminal ,+80 switch unit circuit S (k+80) of kth+96 switch unit circuit S (k+96) of control terminal, kth control End is connected with the control terminal of+112 switch unit circuit S (k+112) of kth and its connecting pin is 16 parallel-by-bits of moderator PUF The kth position of control terminal, k=1,2,3 ..., 16；Each switch unit circuit respectively includes the 7th data selector MUX7, the 8th Data selector MUX8, the 17th phase inverter B17, eighteen incompatibilities phase device B18, the 19th phase inverter B19 and the 20th phase inverter B20, the 7th data selector MUX7 and the 8th data selector MUX8 are respectively two input data selectors, the selection of the 7th data Device MUX7 and the 8th data selector MUX8 is respectively provided with first input end, the second input terminal, control terminal and output end, the 7th number It is switch according to the first input end connection and its connecting pin of the first input end and the 8th data selector MUX8 of selector MUX7 The second of the first input end of element circuit, the second input terminal of the 7th data selector MUX7 and the 8th data selector MUX8 Input terminal connection and its connecting pin are the second input terminal of switch unit circuit, the control terminal of the 7th data selector MUX7 and the The control terminal of eight data selector MUX8 connects and its connecting pin is the control terminal of switch unit circuit, the 7th data selector The connection of the input terminal of the output end of MUX7 and the 17th phase inverter B17, the output end and eighteen incompatibilities phase of the 17th phase inverter B17 The input terminal of device B18 connects, and the output end of eighteen incompatibilities phase device B18 is the first output end of switch unit single channel, the 8th data The connection of the input terminal of the output end of selector MUX8 and the 19th phase inverter B19, the output end and second of the 19th phase inverter B19 The input terminal of ten phase inverter B20 connects, and the output end of the 20th phase inverter B20 is the second output terminal of switch unit single channel.

Under TSMC 65nm CMOS technology, designs and to verify the multimodal fusion of the invention based on linear feedback restructural The function of PUF element circuit.Wherein, storage-type stochastic source uses Full-custom design, and remaining circuit uses standard cell design.This The simulation waveform of the restructural PUF element circuit of the multimodal fusion based on linear feedback of invention is as shown in Figure 10.Analysis chart 10 can Know, the restructural PUF element circuit delay of the multimodal fusion of the invention based on linear feedback is 18.14ns or so, moderator PUF Path delay time be 8.13ns.Due to the certainty of process deviation, the specific delay meeting random fluctuation of circuit, especially The path delay variation of moderator PUF circuit is more significant.

The quantity statistics of O and 1 are as shown in figure 11 in output response of the invention.Known to analysis chart 11: right in the case where mutually motivating The restructural PUF element circuit of multimodal fusion based on linear feedback of the invention carries out 2048 Monte-Carlo Simulations, obtains 2048 output responses, wherein the quantity that 0 quantity is 985,1 is 1063, and the randomness for calculating of the invention is 96.2%.

Claims

1. a kind of restructural PUF element circuit of multimodal fusion based on linear feedback, it is characterised in that including storage-type stochastic source, Linear feedback shift register, string turns and module and moderator PUF, and the storage-type stochastic source has control terminal, enable end With 8 parallel-by-bit output ends；The linear feedback shift register have 8 parallel-by-bit input terminals, serial output terminal, clear terminal, Set several ends and clock end；The string turns and module has serial input terminal, clock end and 16 parallel-by-bit output ends；Described is secondary Cutting out device PUF has input terminal, 16 parallel-by-bit control terminals and output end；The control terminal of the storage-type stochastic source is for accessing word Line control signal, the enable end of the storage-type stochastic source is for accessing enable signal, the linear feedback shift register The clear terminal of device for accessing reset signal, the linear feedback shift register set several ends for access set several signals, The clock end of the linear feedback shift register and the string turn the equal incoming clock signal of clock end of simultaneously module, described The input terminal of moderator PUF access input signal, the output end of the moderator PUF is for exporting PUF output response, institute 8 parallel-by-bit input terminals of 8 parallel-by-bit output ends of the storage-type stochastic source stated and the linear feedback shift register are one by one It is correspondingly connected with, the serial output terminal of the linear feedback shift register and the string turn and the serial input terminal of module connect It connects, the string turns and the 16 parallel-by-bit control terminals of 16 parallel-by-bit output ends of module and the moderator PUF correspond Connection；

The storage-type stochastic source includes identical eight storage units of structure, and each storage unit is respectively provided with control End, enable end and output end processed, storage unit described in eight control terminal connection and its connecting pin be the storage-type with The enable end of the control terminal in machine source, storage unit described in eight connects and its connecting pin is making for the storage-type stochastic source Energy end, the output end of storage unit described in m-th are m of 8 parallel-by-bit output ends of the storage-type stochastic source, m =1,2 ..., 8；The storage unit includes the first PMOS tube, the second PMOS tube, third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the first NMOS tube, the second NMOS tube, third NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube, the one or two input nand gate, the two or two input nand gate and One phase inverter；One or two input nand gate and the two or two input nand gate are respectively provided with first input end, Two input terminals and output end, the source electrode of first PMOS tube, the source electrode of second PMOS tube, the 3rd PMOS The source electrode of pipe, the source electrode of the 4th PMOS tube, the source electrode of the 5th PMOS tube and the source of the 6th PMOS tube Extremely access power supply, the grid of first PMOS tube, the drain electrode of second PMOS tube, second NMOS tube It drains, the grid of the third NMOS tube is connected with the drain electrode of the 4th NMOS tube, the leakage of first PMOS tube Pole, the grid of second PMOS tube, the drain electrode of first NMOS tube, the drain electrode of the third NMOS tube and described The 4th NMOS tube grid connection, the grid of first NMOS tube is connected with the grid of second NMOS tube and it Connecting pin is the control terminal of the storage unit, the grid of the source electrode of first NMOS tube and the 7th NMOS tube Connection, the source electrode of second NMOS tube are connected with the grid of the 8th NMOS tube, the source of the third NMOS tube The source grounding of pole and the 4th NMOS tube, the grid of the grid of the third PMOS tube, the 6th PMOS tube Pole is connected with the grid of the 9th NMOS tube and its connecting pin is the enable end of the storage unit, the third The drain electrode of PMOS tube, the drain electrode of the 4th PMOS tube, the grid of the 5th PMOS tube, the 5th NMOS tube Drain electrode, the 6th NMOS tube grid connected with the first input end of the one or two input nand gate, described the The grid of four PMOS tube, the drain electrode of the 5th PMOS tube, the drain electrode of the 6th PMOS tube, the 5th NMOS tube The drain electrode of grid, the 6th NMOS tube connected with the second input terminal of the two or two input nand gate, it is described The source electrode of 5th NMOS tube is connected with the drain electrode of the 7th NMOS tube, the source electrode of the 6th NMOS tube and described The drain electrodes of eight NMOS tubes connects, the source electrode and the described the 9th of the source electrode of the 7th NMOS tube, the 8th NMOS tube The drain electrode of NMOS tube connects, the source electrode ground connection of the 9th NMOS tube, the second input of the one or two input nand gate End is connected with the output end of the two or two input nand gate, the output end of the one or two input nand gate, described The first input end of two or two input nand gate is connected with the input terminal of first phase inverter, first phase inverter Output end is the output end of the storage unit.

2. the restructural PUF unit of a kind of multimodal fusion based on linear feedback according to claim 1, it is characterised in that institute The linear feedback shift register stated includes the first data selector, the second data selector, third data selector, the 4th number According to selector, the 5th data selector, the 6th data selector, the one or two input XOR gate, the first d type flip flop, the 2nd D triggering Device, third d type flip flop, four d flip-flop, the 5th d type flip flop, the 6th d type flip flop, the 7th d type flip flop, the 8th d type flip flop, Nine d type flip flops, the tenth d type flip flop, the 11st d type flip flop, the tenth 2-D trigger, the tenth 3d flip-flop, the 14th D triggering Device, the 15th d type flip flop and the 16th d type flip flop, first data selector, second data selector, institute The third data selector and the 4th data selector stated are four input data selectors, the first data choosing Device, second data selector, the third data selector and the 4th data selector is selected to be respectively provided with First input end, the second input terminal, third input terminal, the 4th input terminal, the first control terminal, the second control terminal and output end, institute The 5th data selector and the 6th data selector stated are two input data selectors, the 5th data choosing It selects device and the 6th data selector is respectively provided with first input end, the second input terminal, control terminal and output end, it is described One or two input XOR gate has first input end, the second input terminal and an output end, first d type flip flop, described the 2-D trigger, the third d type flip flop, the four d flip-flop, the 5th d type flip flop, the 6th D touching Send out device, the 7th d type flip flop, the 8th d type flip flop, the 9th d type flip flop, the tenth d type flip flop, 11st d type flip flop, the tenth 2-D trigger, the tenth 3d flip-flop, the 14th D triggering Device, the 15th d type flip flop and the 16th d type flip flop are respectively provided with input terminal, clock end, set several ends, clearing End, output end and reversed-phase output, the clock end of first d type flip flop, the clock end of second d type flip flop, institute The clock end for the third d type flip flop stated, the clock end of the four d flip-flop, the clock end of the 5th d type flip flop, The clock end of 6th d type flip flop, the clock end of the 7th d type flip flop, the 8th d type flip flop clock End, the clock end of the 9th d type flip flop, the clock end of the tenth d type flip flop, the 11st d type flip flop Clock end, the clock end of the tenth 2-D trigger, the clock end of the tenth 3d flip-flop, the 14th D The clock end of trigger, the clock end of the 15th d type flip flop connected with the clock end of the 16th d type flip flop and Its connecting pin is the clock end of the linear feedback shift register, and first d type flip flop sets several ends, described the The clear terminal of 2-D trigger, the third d type flip flop set several ends, the four d flip-flop sets several ends, described The clear terminal, described for setting several ends, the 7th d type flip flop of the clear terminal of 5th d type flip flop, the 6th d type flip flop The 8th d type flip flop set several ends, the clear terminal of the 9th d type flip flop, the tenth d type flip flop set several ends, institute The 11st d type flip flop stated set several ends, the clear terminal of the tenth 2-D trigger, the tenth 3d flip-flop it is clear Zero end, the tenth four d flip-flop clear terminal, the 15th d type flip flop set several ends and described 16th D triggering The clear terminal of device connects and its connecting pin is that the linear feedback shift register sets several ends；First d type flip flop Clear terminal, second d type flip flop set several ends, the clear terminal of the third d type flip flop, described 4th D triggering The clear terminal of device, the 5th d type flip flop set several ends, the clear terminal of the 6th d type flip flop, described 7th D touching Hair device set several ends, the clear terminal of the 8th d type flip flop, the 9th d type flip flop set several ends, the tenth D The clear terminal of trigger, the clear terminal of the 11st d type flip flop, the tenth 2-D trigger set several ends, described The clear terminal for setting several ends, the 15th d type flip flop for setting several ends, the tenth four d flip-flop of tenth 3d flip-flop With the 16th d type flip flop set several ends connect and its connecting pin be the linear feedback shift register clearing End；The first input end of first data selector, the output end of first d type flip flop and the 2nd D touching Send out device input terminal connection, the second input terminal of first data selector, second d type flip flop output end and The input terminal of the third d type flip flop connects, the third input terminal of first data selector, the 3rd D touching The output end of hair device is connected with the input terminal of the four d flip-flop, the 4th input terminal of first data selector, The output end of the four d flip-flop is connected with the input terminal of the 5th d type flip flop, second data selector First input end, the 5th d type flip flop output end connected with the input terminal of the 6th d type flip flop, it is described The input of second input terminal of the second data selector, the output end of the 6th d type flip flop and the 7th d type flip flop End connection, the output end and the described the 8th of the third input terminal of second data selector, the 7th d type flip flop The input terminal of d type flip flop connects, the output of the 4th input terminal, the 8th d type flip flop of second data selector End is connected with the input terminal of the 9th d type flip flop, the first input end of the third data selector, the described the 9th The output end of d type flip flop is connected with the input terminal of the tenth d type flip flop, the second input of the third data selector It holds, the output end of the tenth d type flip flop is connected with the input terminal of the 11st d type flip flop, the third data The input terminal of the third input terminal of selector, the output end of the 11st d type flip flop and the tenth 2-D trigger connects It connects, the output end and the described the 13rd of the 4th input terminal of the third data selector, the tenth 2-D trigger The input terminal of d type flip flop connects, the first input end of the 4th data selector, the tenth 3d flip-flop it is defeated Outlet is connected with the input terminal of the tenth four d flip-flop, the second input terminal of the 4th data selector, described The output end of tenth four d flip-flop is connected with the input terminal of the 15th d type flip flop, the 4th data selector Third input terminal, the 15th d type flip flop output end connected with the input terminal of the 16th d type flip flop, it is described The 4th input terminal of the 4th data selector connected with the output end of the 16th d type flip flop and its connecting pin is described Linear feedback shift register serial output terminal, the output end of first data selector and the 5th data The first input end of selector connects, and the of the output end of second data selector and the 5th data selector The first input end of the connection of two input terminals, the output end of the third data selector and the 6th data selector connects It connects, the output end of the 4th data selector is connected with the second input terminal of the 6th data selector, described The output end of 5th data selector is connected with the first input end of the one or the two input XOR gate, the 6th data The output end of selector is connected with the second input terminal of the one or the two input XOR gate, the one or the two input XOR gate Output end connected with the input terminal of first d type flip flop, the first control terminal of first data selector is institute The 1st of 8 parallel-by-bit input terminals of the linear feedback shift register stated, the second control terminal of first data selector It is the 2nd of 8 parallel-by-bit input terminals of the linear feedback shift register, the first control of second data selector End processed is the 3rd of 8 parallel-by-bit input terminals of the linear feedback shift register, the of second data selector Two control terminals are the 4th of 8 parallel-by-bit input terminals of the linear feedback shift register, the third data selector The first control terminal be the 5th of 8 parallel-by-bit input terminals of the linear feedback shift register, the third data choosing The second control terminal for selecting device is the 6th of 8 parallel-by-bit input terminals of the linear feedback shift register, the 4th number Connecting pin according to the control terminal of the first control terminal and the 5th data selector of selector is that the linear feedback is moved The 7th of 8 parallel-by-bit input terminals of bit register, the second control terminal of the 4th data selector and the 6th number Connecting pin according to the control terminal of selector is the 8th of 8 parallel-by-bit input terminals of the linear feedback shift register.

3. the restructural PUF element circuit of a kind of multimodal fusion based on linear feedback according to claim 2, feature exist Include the 7th PMOS tube, the 8th PMOS tube, the 9th PMOS tube, the tenth PMOS tube, the 11st PMOS in first d type flip flop Pipe, the 12nd PMOS tube, the 13rd PMOS tube, the 14th PMOS tube, the tenth NMOS tube, the 11st NMOS tube, the 12nd NMOS Pipe, the 13rd NMOS tube, the 14th NMOS tube, the 15th NMOS tube, the 16th NMOS tube, the 17th NMOS tube, the second reverse phase Device, third phase inverter, the 4th phase inverter, the 5th phase inverter, hex inverter, the 7th phase inverter, the 8th phase inverter and the 9th are anti- Phase device,

The source electrode of the source electrode of 7th PMOS tube, the source electrode of the 8th PMOS tube and the 12nd PMOS tube point Not Jie Ru power supply, the grid of the 7th PMOS tube is connected with the grid of the 13rd NMOS tube and its connecting pin is institute The drain electrode of the clear terminal for the first d type flip flop stated, the 7th PMOS tube is connected with the source electrode of the 9th PMOS tube, institute The grid for the 8th PMOS tube stated, the source electrode of the 13rd PMOS tube, the 15th NMOS tube grid, described The source electrode of 16th NMOS tube is connected with the output end of the 4th phase inverter, the drain electrode of the 8th PMOS tube and described The tenth PMOS tube source electrode connection, the grid, described of the grid of the 9th PMOS tube, the 14th NMOS tube The grid of 16th NMOS tube, the 14th PMOS tube grid connected with the output end of the third phase inverter, institute The drain electrode for the 9th PMOS tube stated, the drain electrode of the tenth NMOS tube, the drain electrode of the 11st PMOS tube, described The drain electrode of ten PMOS tube, the drain electrode of the 14th NMOS tube are connected with the input terminal of the 4th phase inverter, described The grid of tenth PMOS tube, the grid of the tenth NMOS tube, the grid of the 13rd PMOS tube, the described the 17th The grid of NMOS tube, second phase inverter output end connected with the input terminal of the third phase inverter, described The source electrode of 11 PMOS tube is connected with the drain electrode of the 12nd PMOS tube, the grid of the 11st PMOS tube and described The 11st NMOS tube grid connection and its connecting pin be first d type flip flop input terminal, the described the 12nd The grid of PMOS tube, the 12nd NMOS tube grid connected with the output end of the 9th phase inverter, described The drain electrode of 13 PMOS tube, the drain electrode of the 16th NMOS tube, the source electrode of the 14th PMOS tube, the described the tenth The source electrode of seven NMOS tubes is connected with the input terminal of the 5th phase inverter, the drain electrode of the 14th PMOS tube, described The drain electrode of 17th NMOS tube, the output end of the hex inverter are connected with the input terminal of the 7th phase inverter, institute The drain electrode of the source electrode for the tenth NMOS tube stated, the 11st NMOS tube is connected with the drain electrode of the 12nd NMOS tube, The drain electrode of the source electrode of 11st NMOS tube, the source electrode of the 12nd NMOS tube and the 13rd NMOS tube connects It connects, the source electrode of the 13rd NMOS tube and the source grounding of the 15th NMOS tube, the 14th NMOS The source electrode of pipe is connected with the drain electrode of the 15th NMOS tube,

The input terminal of second phase inverter be first d type flip flop clock end, the 5th phase inverter it is defeated Outlet, the hex inverter input terminal connected with the input terminal of the 8th phase inverter, the 7th phase inverter Output end be first d type flip flop reversed-phase output, the output end of the 8th phase inverter is the first D The output end of trigger, the input terminal of the 9th phase inverter are several ends of setting of first d type flip flop, described second D type flip flop, the third d type flip flop, the four d flip-flop, the 5th d type flip flop, the 6th D triggering Device, the 7th d type flip flop, the 8th d type flip flop, the 9th d type flip flop, the tenth d type flip flop, institute The 11st d type flip flop, the tenth 2-D trigger, the tenth 3d flip-flop, the 14th D triggering stated The circuit structure of device, the 15th d type flip flop and the 16th d type flip flop is identical as first d type flip flop.

4. the restructural PUF element circuit of a kind of multimodal fusion based on linear feedback according to claim 1, feature exist Turn in the string and module includes the 17th d type flip flop, the 18th d type flip flop, the 19th d type flip flop, the 20th D triggering Device, the 21st d type flip flop, the 20th 2-D trigger, the 20th 3d flip-flop, the 20th four d flip-flop, the 25th D Trigger, the 26th d type flip flop, the 27th d type flip flop, the 28th d type flip flop, the 29th d type flip flop, the 30th D type flip flop, the 31st d type flip flop and the 30th 2-D trigger, the 17th d type flip flop, the 18th D touching Send out device, the 19th d type flip flop, the 20th d type flip flop, the 21st d type flip flop, described second Ten 2-D triggers, the 20th 3d flip-flop, the 20th four d flip-flop, the 25th D triggering Device, the 26th d type flip flop, the 27th d type flip flop, the 28th d type flip flop, described 29 d type flip flops, the 30th d type flip flop, the 31st d type flip flop and the 32nd D triggering Device is respectively provided with input terminal, clock end, output end and reversed-phase output, and the input terminal of the 17th d type flip flop is described String turn and the serial input terminal of module, the clock end of the 17th d type flip flop, the 18th d type flip flop when Zhong Duan, the clock end of the 19th d type flip flop, the clock end of the 20th d type flip flop, the 21st D The clock end of trigger, the clock end of the 20th 2-D trigger, the clock end of the 20th 3d flip-flop, institute The clock end for the 20th four d flip-flop stated, the clock end of the 25th d type flip flop, the 26th D triggering It is the clock end of device, the clock end of the 27th d type flip flop, the clock end of the 28th d type flip flop, described The clock end of 29th d type flip flop, the clock end of the 30th d type flip flop, the 31st d type flip flop when Zhong Duan is connected with the clock end of the 30th 2-D trigger and its connecting pin is the clock end that the string turns simultaneously module, The connecting pin of the input terminal of the output end and the 18th d type flip flop of 17th d type flip flop turns for the string And the 1st of 16 parallel-by-bit output ends of module, the output end of the 18th d type flip flop and the 19th D triggering The connecting pin of the input terminal of device is the 2nd that the string turns simultaneously 16 parallel-by-bit output ends of module, the 19th D triggering The connecting pin of the input terminal of the output end of device and the 20th d type flip flop is that the string turns and 16 parallel-by-bits of module are defeated The 3rd of outlet, the connection of the input terminal of the output end and the 21st d type flip flop of the 20th d type flip flop End is the 4th that the string turns simultaneously 16 parallel-by-bit output ends of module, the output end of the 21st d type flip flop and institute The connecting pin of the input terminal for the 20th 2-D trigger stated is the 5th that the string turns simultaneously 16 parallel-by-bit output ends of module, The connecting pin of the input terminal of the output end and the 20th 3d flip-flop of 20th 2-D trigger is described String turns the 6th of simultaneously 16 parallel-by-bit output ends of module, the output end and the described the 20th of the 20th 3d flip-flop The connecting pin of the input terminal of four d flip-flop is that the described string turns and the 7th of 16 parallel-by-bit output ends of module, described second The connecting pin of the input terminal of the output end of ten four d flip-flops and the 25th d type flip flop is that the string turns simultaneously module The 8th of 16 parallel-by-bit output ends, the output end and the 26th d type flip flop of the 25th d type flip flop The connecting pin of input terminal be that the described string turns and the 9th of 16 parallel-by-bit output ends of module, the 26th D triggering The connecting pin of the input terminal of the output end of device and the 27th d type flip flop is 16 parallel-by-bits that the string turns simultaneously module The 10th of output end, the input terminal of the output end and the 28th d type flip flop of the 27th d type flip flop Connecting pin is the 11st that the string turns simultaneously 16 parallel-by-bit output ends of module, the output of the 28th d type flip flop The connecting pin of the input terminal of end and the 29th d type flip flop is the string turn and 16 parallel-by-bit output ends of module 12nd, the connecting pin of the input terminal of the output end and the 30th d type flip flop of the 29th d type flip flop is institute The string stated turns and the 13rd of 16 parallel-by-bit output ends of module, the output end of the 30th d type flip flop and described the The connecting pin of the input terminal of 31 d type flip flops is the 14th that the string turns simultaneously 16 parallel-by-bit output ends of module, described The 31st d type flip flop output end and the 30th 2-D trigger input terminal connecting pin be the string turn And the 15th of 16 parallel-by-bit output ends of module, the output end of the 30th 2-D trigger are that the string turns simultaneously mould The 16th of 16 parallel-by-bit output ends of block.

5. the restructural PUF element circuit of a kind of multimodal fusion based on linear feedback according to claim 4, feature exist In the 17th d type flip flop include the 15th PMOS tube, the 16th PMOS tube, the 17th PMOS tube, the 18th PMOS tube, 19th PMOS tube, the 20th PMOS tube, the 18th NMOS tube, the 19th NMOS tube, the 20th NMOS tube, the 21st NMOS Pipe, the 22nd NMOS tube, the 23rd NMOS tube, the tenth phase inverter, the 11st phase inverter, the 12nd phase inverter, the 13rd Phase inverter, the 14th phase inverter, the 15th phase inverter and the tenth hex inverter, the source electrode of the 15th PMOS tube and described The source electrode of the 16th PMOS tube access power supply, the drain electrode of the 15th PMOS tube and the 17th PMOS tube Source electrode connection, the grid of the 15th PMOS tube, the grid of the 19th NMOS tube, the 22nd NMOS The grid of pipe, the 20th PMOS tube grid connected with the output end of the 11st phase inverter, the described the tenth The drain electrode of six PMOS tube is connected with the source electrode of the 18th PMOS tube, the grid of the 16th PMOS tube, described The output end of 12nd phase inverter, the grid of the 21st NMOS tube, the source electrode of the 19th PMOS tube and institute The source electrode for the 22nd NMOS tube stated connects, the grid of the 17th PMOS tube and the grid of the 18th NMOS tube Pole connection and its connecting pin are the input terminal of the 17th d type flip flop, the drain electrode of the 17th PMOS tube, described The drain electrode of 18th NMOS tube, the drain electrode of the 18th PMOS tube, the drain electrode of the 19th NMOS tube and described The input terminal of 12nd phase inverter connects, the grid of the 18th PMOS tube, the grid of the 20th NMOS tube, institute The grid for the 19th PMOS tube stated, the grid of the 23rd NMOS tube, the tenth phase inverter output end and The input terminal of 11st phase inverter connects, the drain electrode of the 19th PMOS tube, the 22nd NMOS tube Drain electrode, the source electrode of the 20th PMOS tube, the source electrode of the 23rd NMOS tube and the 13rd reverse phase The input terminal of device connects, the drain electrode of the 20th PMOS tube, the drain electrode of the 23rd NMOS tube, the described the tenth The output end of four phase inverters is connected with the input terminal of the 15th phase inverter, the source electrode of the 18th NMOS tube and institute The drain electrode for the 20th NMOS tube stated connects, the source electrode of the 19th NMOS tube and the leakage of the 21st NMOS tube Pole connection, the source electrode of the 20th NMOS tube and the source grounding of the 21st NMOS tube, the described the tenth The input terminal of phase inverter is the clock end of the 17th d type flip flop, the output end of the 13rd phase inverter, described The input terminal of 14th phase inverter is connected with the input terminal of the tenth hex inverter, the output of the 15th phase inverter End is the reversed-phase output of the 17th d type flip flop, and the output end of the tenth hex inverter is the 17th D The output end of trigger；18th d type flip flop, the 19th d type flip flop, the 20th d type flip flop, institute The 21st d type flip flop, the 20th 2-D trigger, the 20th 3d flip-flop, the described the 20th stated Four d flip-flop, the 25th d type flip flop, the 26th d type flip flop, the 27th d type flip flop, 28th d type flip flop, the 29th d type flip flop, the 30th d type flip flop, the described the 30th 17th d type flip flop described in circuit structure diagram of one d type flip flop with the 30th 2-D trigger is identical.

6. the restructural PUF element circuit of a kind of multimodal fusion based on linear feedback according to claim 1, feature exist It include that the identical 128 switch unit circuits of structure and a moderator, the moderator have in the moderator PUF First input end, the second input terminal and output end, the switch unit circuit have first input end, the second input terminal, control End, the first output end and second output terminal processed, the first input end of switch unit circuit described in the 1st and the second input terminal connect It connects and its connecting pin is the input terminal of the moderator PUF, the first output end of switch unit circuit described in j-th and the The first input end connection of the j+1 described switch unit circuit, the second output terminal of switch unit circuit described in j-th and Second input terminal of switch unit circuit described in jth+1 connects, j=1, and 2 ... ..., 127；Switch list described in 128th First output end of first circuit is connected with the first input end of the moderator, switch unit circuit described in the 128th Second output terminal is connected with the second input terminal of the moderator, and the output end of the moderator is the moderator The output end of PUF, the control of switch unit circuit described in control terminal, kth+16 of switch unit circuit described in k-th End, switch unit circuit described in kth+32 control terminal, kth+48 described in the control terminal of switch unit circuit, kth+ + 96 institutes of control terminal, kth of switch unit circuit described in control terminal, the kth+80 of switch unit circuit described in 64 The control terminal for the switch unit circuit stated is connected with the control terminal of switch unit circuit described in kth+112 and its connecting pin is The kth position of the 16 parallel-by-bit control terminals of the moderator PUF, k=1,2,3 ..., 16；The switch unit circuit includes 7th data selector, the 8th data selector, the 17th phase inverter, eighteen incompatibilities phase device, the 19th phase inverter and the 20th Phase inverter, the 7th data selector and the 8th data selector are respectively two input data selectors, described The 7th data selector and the 8th data selector be respectively provided with first input end, the second input terminal, control terminal and The first input end of output end, the 7th data selector is connected with the first input end of the 8th data selector And its connecting pin be the switch unit circuit first input end, the second input terminal of the 7th data selector and Second input terminal of the 8th data selector connects and its connecting pin is the second input of the switch unit circuit End, the control terminal of the 7th data selector is connected with the control terminal of the 8th data selector and its connecting pin is The control terminal of the switch unit circuit, the output end of the 7th data selector and the 17th phase inverter Input terminal connection, the output end of the 17th phase inverter is connected with the input terminal of the eighteen incompatibilities phase device, described The output end of eighteen incompatibilities phase device be the switch unit single channel the first output end, the 8th data selector it is defeated Outlet is connected with the input terminal of the 19th phase inverter, the output end and the described the 20th of the 19th phase inverter The input terminal of phase inverter connects, and the output end of the 20th phase inverter is the second output of the switch unit single channel End.